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Event cameras such as the Dynamic Vision Sensor (DVS) are useful because of their low latency, sparse output, and high dynamic range. In this paper, we propose a DVS+FPGA camera platform and use it to demonstrate the hardware implementation of event-based corner keypoint detection and adaptive block-matching optical flow. To adapt sample rate dynamically, events are accumulated in event slices using the area event count slice exposure method. The area event count is feedback controlled by the average optical flow matching distance. Corners are detected by streaks of accumulated events on event slice rings of radius 3 and 4 pixels. Corner detection takes about 6 clock cycles (16 MHz event rate at the 100MHz clock frequency) At the corners, flow vectors are computed in 100 clock cycles (1 MHz event rate). The multiscale block match size is $25\times 25$ pixels and the flow vectors span up to 30-pixel match distance. The FPGA processes the sum-of-absolute distance block matching at 123 GOp/s, the equivalent of 1230 Op/clock cycle. EDFLOW is several times more accurate on MVSEC drone and driving optical flow benchmarking sequences than the previous best DVS FPGA optical flow implementation, and achieves similar accuracy to the CNN-based EV-Flownet, although it burns about 100 times less power. The EDFLOW design and benchmarking videos are available at https://sites.google.com/view/edflow21/home. [ABSTRACT FROM AUTHOR]

Conventionalliterature on array signal processing (ASP) is based on the “capture first, process later” philosophy and to this end, signal processing algorithms are typically decoupled from the hardware. This poses fundamental limitations because if the sensors result in information loss, the algorithms may no longer be able to achieve their guaranteed performance. In this paper, our goal is to overcome the barrier of information loss via sensor saturation and clipping. This is a significant problem in application areas including physiological monitoring and extra-terrestrial exploration where the amplitudes may be unknown or larger than the dynamic range of the sensor. To overcome this fundamental bottleneck, we propose “computational arrays” which are based on a co-design approach so that a collaboration between the sensor array hardware and algorithms can be harnessed. Our work is inspired by the recently introduced unlimited sensing framework. In this context, our computational arrays encode the high-dynamic-range information by folding the signal amplitudes, thus introducing a new form of information loss in terms of the modulo measurements. On the decoding front, we develop mathematically guaranteed recovery algorithms for spatio-temporal array signal processing tasks that include DoA estimation, beamforming and signal reconstruction. Numerical examples corroborate the applicability of our approach and pave a path for the development of novel computational arrays for ASP. [ABSTRACT FROM AUTHOR]

Depth estimation is crucial in several computer vision applications, and a recent trend in this field aims at inferring such a cue from a single camera. Unfortunately, despite the compelling results achieved, state-of-the-art monocular depth estimation methods are computationally demanding, thus precluding their practical deployment in several application contexts characterized by low-power constraints. Therefore, in this paper, we propose a lightweight Convolutional Neural Network based on a shallow pyramidal architecture, referred to as $\mu $ PyD-Net, enabling monocular depth estimation on microcontrollers. The network is trained in a peculiar self-supervised manner leveraging proxy labels obtained through a traditional stereo algorithm. Moreover, we propose optimization strategies aimed at performing computations with quantized 8-bit data and map the high-level description of the network to low-level layers optimized for the target microcontroller architecture. Exhaustive experimental results on standard datasets and an in-depth evaluation with a device belonging to the popular Arm Cortex-M family confirm that obtaining sufficiently accurate monocular depth estimation on microcontrollers is feasible. To the best of our knowledge, our proposal is the first one enabling such remarkable achievement, paving the way for the deployment of monocular depth cues onto the tiny end-nodes of distributed sensor networks. [ABSTRACT FROM AUTHOR]

The function of an image dehazing algorithm restores a hazy image back to a clear one. This technique can be equipped in Advanced Driver Assistance Systems (ADAS) to further improve driving safety. Advanced display resolutions and high frame rates are critical to improve the reliability of ADAS. However, they cause a serious limitation on the hardware realization of an image dehazing algorithm. In this paper, an algorithm and architecture design of a hardware-efficient image dehazing engine are proposed. This dehazing algorithm comprises two core techniques: a low-complexity airlight estimation (LAE) and an independent transmission rate estimation (ITRE). LAE can efficiently predict the airlight without massive sorting processes and a computationally intensive filtering. Moreover, in its hardware architecture, a preluded airlight estimation is proposed to yield an efficient data scheduling. Being independent of the airlight, ITRE is able to solely predict transmission rates. This enables LAE and ITRE to be concurrently processed, improving the throughput of their hardware architectures. Compared with other sophisticated studies, this study demonstrates a competitive performance in peak signal-to-noise ratio, structural similarity, contrast distortion, and computational efficiency. The hardware architecture is realized using Taiwan Semiconductor Manufacturing Company CMOS 0.18- $\mu \text{m}$ technology, and logic gate count is 32.6 K. Its working frequency is 200 MHz with a power consumption of 16.5 mW. The maximum throughput is as high as 600 megapixels/s, which can support $4\,096\times 2\,160$ at 60 frames/s. The experimental results indicate that this paper demonstrates superior energy and area efficiencies. [ABSTRACT FROM AUTHOR]

In the scope of vehicular communication networks, the nature of exchanged safety/warning messages renders itself highly location dependent, as it is usually for incident reporting. Vehicles are required to periodically exchange beacon messages that include speed, time, and GPS location information. Reported position information must be accurate and authentic. To mitigate the potential risk of location spoofing/falsifying attack, this paper presents Angle-of-Arrival (AoA) estimation as a physical layer authentication scheme for cross verification of the reported location information. We consider a multi-antenna road side unit under location spoofing attack. Within the considered vehicular communication settings, fundamental limits of AoA estimation are developed in terms of its Cramer–Rao Bound and existence of efficient estimator. The problem of deciding whether the received signal originated from the claimed GPS location is formulated as a two-sided hypotheses testing problem whose solution is given by Wald test statics. We give correct decision $P_D$ and false alarm $P_F$ probabilities in a closed form. To offset the gap between information theoretical studies and practical implementations of physical layer security architectures, theoretical results presented in this paper are further supported by detailed hardware implantation using software-defined radios and field experimental results. We show that the keystone for obtaining reliable AoA measurements is the accurate characterization of the array response vector. Our hardware measurements showed that, unlike idealized models, hardware imperfections leave the actual array response vector of non-structured form. To address this problem, we introduce the method for obtaining the actual array response vector empirically, which led to accurate and stable AoA measurements. Field experimental results shows the feasibility of the proposed AoA authentication scheme. [ABSTRACT FROM AUTHOR]

Timing skews among channels degrade seriously the time-interleaved analog-to-digital converter (TIADC) performance, which can be improved by the blind timing skew estimation (TSE) technique. In this paper, we proposed the all-phase fast Fourier transform (ApFFT) based on spectrum sparsity signal phase relationship blind TSE (ApFFT-SSPR-BLTSE) algorithm. The ApFFT-SSPR-BLTSE algorithm reduces computational complexity based on the phase relationship of the total output from TIADC and the corresponding reference channel output compared with the existing spectrum sparsity blind TSE (SS-BLTSE) algorithm. We also utilized the ApFFT technique to increase the accuracy of phase spectral estimation. Simulation results show that the proposed ApFFT-SSPR-BLTSE algorithm, which as a reduced number of fast Fourier transforms (FFTs) and low hardware complexity, has higher accuracy for blind TSE compared to the existing SS-BLTSE algorithm. In addition, this paper presents an efficient hardware architecture of the ApFFT-SSPR-BLTSE algorithm on the Xilinx Virtex-6 vlx550tff1759 field-programmable gate array (FPGA) chip for the blind TSE of the four-channel 400-MHz 14-bit TIADC real system. The validation results show that the proposed algorithm uses only a few percent of the hardware resources of the FPGA chip, and the mismatch spurs were suppressed to better than −81.54 dB. [ABSTRACT FROM AUTHOR]

In recent years, software defined radio and digital signal processing have been widely used in communication and radar. As a result, the hardware and RF front-end for radar and wireless communication tends to be similar. Thus, using the same RF and hardware platform for joint radar-communication becomes viable. Joint radar-communication would bring more efficient plan and usage for the radio spectral resource. Furthermore, it could enable new applications that require information exchange and precise localization at the same time. In this paper, cyclic prefixed single carrier (CP-SC) and its variations are chosen as the waveforms for joint radar-communication. CP-SC waveform and its variations are popular in wireless communication and have been chosen by a few standards like IEEE 802.11ad and LTE-advanced. Efficient algorithms are proposed to use such waveforms for range and speed detection/estimation of targets. The proposed algorithms are derived from the maximum likelihood (ML) principle and have low computational complexity. Simulations show that the estimation performance of the proposed method is almost the same as that of ML and is much better than that of the channel estimation based method. [ABSTRACT FROM AUTHOR]

Depth image-based rendering (DIBR) techniques have recently drawn more attention in various 3D applications. In this paper, a real-time high-quality DIBR system that consists of disparity estimation and view synthesis is proposed. For disparity estimation, a local approach that focuses on depth discontinuities and disparity smoothness is presented to improve the disparity accuracy. For view synthesis, a method that contains view interpolation and extrapolation is proposed to render high-quality virtual views. Moreover, the system is designed with an optimized parallelism scheme to achieve a high throughput, and can be scaled up easily. It is implemented on an Altera Stratix IV FPGA at a processing speed of 45 frames per second for 1080p resolution. Evaluated on selected image sets of the Middlebury benchmark, the average error rate of the disparity maps is 6.02%; the average peak signal to noise ratio and structural similarity values of the virtual views are 30.07 dB and 0.9303, respectively. The experimental results indicate that the proposed DIBR system has the top-performing processing speed and its accuracy performance is among the best of state-of-the-art hardware implementations. [ABSTRACT FROM AUTHOR]

Defogging is an essential preprocessing technique for object detection in computer vision-based systems and has been widely used in outdoor surveillance system applications. This paper proposes an efficient defogging algorithm for both static images and videos. Considering real-time applications, the proposed defogging algorithm involves a low-cost hardware oriented design that is based on an atmospheric scattering model and dark channel prior. Compared with previous low-complexity techniques, simulation results indicated that the proposed design demonstrated superior performance in terms of quantitative and qualitative evaluations. A weighting technique and a contour preserving estimation approach are adopted alternately to refine the factors in the defogging process. Furthermore, in the atmospheric light estimation, an adjuster is applied to the video for preventing “flicker” which means that the brightness changes dramatically between two neighbor frames in the video. Hence, the proposed algorithm is suitable for video defogging applications, which have not been dealt with in previous approaches. To achieve the requirement of real-time applications for both static and dynamic images, an implementation of seven-stage very-large-scale integration architecture for the proposed algorithm is presented. By using TSMC 0.13- $\mu {\mathrm{ m}}$ technology, the design yielded a processing rate of approximately 200 Mpixels/s. [ABSTRACT FROM AUTHOR]

We consider the problem of channel estimation for uplink multiuser massive MIMO systems, where, in order to significantly reduce the hardware cost and power consumption, one-bit analog-to-digital converters (ADCs) are used at the base station to quantize the received signal. In this paper, we study the problem of optimal one-bit quantization design for channel estimation in one-bit massive MIMO systems. Our analysis reveals that, if the quantization thresholds are optimally devised, using one-bit ADCs can achieve an estimation error close to (with an increase by a factor of $\pi /2$) that of an ideal estimator that has access to the unquantized data. Since the optimal quantization thresholds are dependent on the unknown channel parameters, we introduce an adaptive quantization scheme in which the thresholds are adaptively adjusted, and a random quantization scheme that randomly generates a set of thresholds based on some statistical prior knowledge of the channel. Simulation results show that our proposed schemes presents a significant performance improvement over the conventional fixed quantization scheme that uses a fixed (typically zero) threshold. [ABSTRACT FROM AUTHOR]

It is a promising solution for real-time multitarget tracking to implement particle cardinality balanced multitarget multi-Bernoulli (CBMeMBer) filters in hardware platforms. However, this solution is difficult to materialize since there is a contradiction between the time-varying number of Bernoulli intensity components in CBMeMBer filters and the limited number of particles in hardware platforms. Moreover, real-time hardware implementation requires a resampling procedure that is suitable for parallel processing, while the existing parallel resampling algorithms oversimplify this procedure, resulting in estimation performance degradation. In this paper, we propose an optimization algorithm of particle allocation to overcome the above-mentioned contradiction, and a parallel resampling algorithm to improve the estimation performance. Numerical experiments demonstrate the effectiveness of the proposed algorithms in multitarget tracking. [ABSTRACT FROM AUTHOR]

Detection of moving objects in videos is a crucial step toward successful surveillance and monitoring applications. A key component for such tasks is called background subtraction and tries to extract regions of interest from the image background for further processing or action. For this reason, its accuracy and real-time performance are of great significance. Although effective background subtraction methods have been proposed, only a few of them take into consideration the special characteristics of thermal imagery. In this paper, we propose a background subtraction scheme, which models the thermal responses of each pixel as a mixture of Gaussians with unknown number of components. Following a Bayesian approach, our method automatically estimates the mixture structure, while simultaneously it avoids over-/underfitting. The pixel density estimate is followed by an efficient and highly accurate updating mechanism, which permits our system to be automatically adapted to dynamically changing operation conditions. We propose a reference implementation of our method in reconfigurable hardware achieving both adequate performance and low-power consumption. Adopting a high-level synthesis design and demanding floating point arithmetic operations are mapped in reconfigurable hardware, demonstrating fast prototyping and on-field customization at the same time. [ABSTRACT FROM AUTHOR]

Visible light cameras commonly used for surveillance applications usually have a limited field of view (FoV). To acquire a broader FoV, distributed aperture systems (DASs) combine views from multiple cameras. Although some commercial or proprietary systems already exist, the open literature in this field reports solely the performance and/or hardware architecture of the respective systems, and omits the required details for a reimplementation. In this paper we present a low-cost, personal-computer-based 360° DAS, with a full description of the hardware architecture and the software implementation details. In particular, we describe in detail two problems, the offline estimation of the orientations of the cameras of the proposed DAS and the online synthesis of a virtual view in real time. For the first problem, we propose an area-based bundle adjuster by combining the forward additive Lucas–Kanade algorithm with a bundle adjustment strategy. The color virtual view of up to $2048\times 1024$ pixels is synthesized online at 39 frames/s. A large majority of the workload of the online phase is implemented on the graphic processing unit. The techniques and methods proposed in this paper are generic and independent on the arrangement of cameras. [ABSTRACT FROM PUBLISHER]

Object recognition is widely used in vision computing for various applications. Traditional CPU and application specific integrated circuit for vision computing cannot provide high performance and enough flexibility, which limit the use of vision systems. In this paper, a hierarchical and parallel pipelined heterogeneous chip for object recognition is proposed to achieve high flexibility, high performance, and area efficiency. In addition, a reformulation of 3D position estimation is proposed. The method uses single precision to achieve the short computing time and accuracy requirement. The hardware resource is small. Application-specific components, such as connected component information extractor and information extraction accelerator, are designed for high performance. Reconfiguration processors and application-specific instruction set processor are introduced to improve flexibility. These components are connected to hierarchical parallel buses. The chip is fabricated in 180-nm CMOS technology and occupies 72.25 mm2 with 1.09M bits on-chip memory. It delivers 204 GOPS + 665M FLOPS operations. The results show that this hierarchical and parallel pipelined heterogeneous chip is suitable for embedded vision systems. [ABSTRACT FROM AUTHOR]

In this paper, we present a bit stream feature-based energy model that accurately estimates the energy required to decode a given High Efficiency Video Coding-coded bit stream. Therefore, we take a model from literature and extend it by explicitly modeling the in-loop filters, which was not done before. Furthermore, to prove its superior estimation performance, it is compared with seven different energy models from the literature. By using a unified evaluation framework, we show how accurately the required decoding energy for different decoding systems can be approximated. We give thorough explanations on the model parameters and explain how the model variables are derived. To show the modeling capabilities in general, we test the estimation performance for different decoding software and hardware solutions, where we find that the proposed model outperforms the models from the literature by reaching framewise mean estimation errors of less than 7% for software and less than 15% for hardware-based systems. [ABSTRACT FROM PUBLISHER]

Polar codes have gained significant amount of attention during the past few years and have been selected as a coding scheme for the next generation of mobile broadband standard. Among decoding schemes, successive-cancellation list (SCL) decoding provides a reasonable tradeoff between the error-correction performance and hardware implementation complexity when used to decode polar codes, at the cost of limited throughput. The simplified SCL (SSCL) and its extension SSCL-SPC increase the speed of decoding by removing redundant calculations when encountering particular information and frozen bit patterns (rate one and single parity check codes), while keeping the error-correction performance unaltered. In this paper, we improve SSCL and SSCL-SPC by proving that the list size imposes a specific number of path splitting required to decode rate one and single parity check codes. Thus, the number of splitting can be limited while guaranteeing exactly the same error-correction performance as if the paths were forked at each bit estimation. We call the new decoding algorithms Fast-SSCL and Fast-SSCL-SPC. Moreover, we show that the number of path forks in a practical application can be tuned to achieve desirable speed, while keeping the error-correction performance almost unchanged. Hardware architectures implementing both algorithms are then described and implemented: It is shown that our design can achieve \mathbf 1.86 Gb/s throughput, higher than the best state-of-the-art decoders. [ABSTRACT FROM PUBLISHER]

The nonlinear energy operator (NEO) algorithm has been commonly implemented in hardware for neural spike detection. However, the traditional method to set the threshold is sensitive to the spike firing rate. In this paper, a new approach is presented to automatically set the threshold, in real time, in a manner that is robust to the spike firing rate and suitable for a neural implant. The presented threshold calculation method statistically analyzes the neural signal standard deviation and root-mean-square frequency and can update the threshold of each channel sequentially every few seconds. Hardware efficient architectures to estimate the threshold calculation statistical parameters are also presented. This automatic thresholding method for NEO spike detection shows robust performance for firing rates from 10 to 100, occupies only 0.021 mm2 in 130 nm CMOS, and consumes only 50 nW in simulations with a 20-kHz clock. [ABSTRACT FROM PUBLISHER]

Compressive sensing (CS) is able to measure sparse signals with fewer measurements than Nyquist rate. The reconstruction of sparse signals in CS is an underdetermined problem. For realistic applications, the sparsity information may not be available, the measurements are used to be disturbed by noise, and efficient hardware realization is important. Existing CS reconstruction algorithms are tradeoff between noise tolerance and low complexity. In this paper, we propose a novel reconstruction algorithm called stochastic gradient pursuit (SGP). The stochastic gradient approach is applied to replace least square process of well-known orthogonal matching pursuit (OMP) algorithm. Since stochastic gradient approach iterates toward a minimum mean square error solution, proposed algorithm shows robustness against noise. Furthermore, proposed algorithm inherits the low-complexity property of OMP and shows feasibility of hardware implementation. The SGP algorithm can achieve 36% higher success rate as well as 27% less complexity than OMP when SNR is 20 dB. Finally, we implement the algorithm with designed hardware sharing architecture in TSMC 90 nm technology. The postlayout result shows that the core size is only 1.08 mm 2 at 150 MHz operation frequency. Compared with state-of-the-art ASIC designs, the proposed engine achieves 29% higher throughput-to-area ratio. [ABSTRACT FROM AUTHOR]

Computational time and hardware resource are key issues in hardware implementation of any signal-processing algorithm. This paper presents the design and implementation of a polyphase-decomposition-based new architecture of wavelet filter for power system harmonics estimation using discrete wavelet packet transform (DWPT). Usually, DWPT provides coefficients as the output; however, the proposed architecture also includes provision for providing root mean square values directly. The proposed method reduces computational requirements and save memory resources. Xilinx system generator, a higher abstraction level tool, has been used to simulate and implement the proposed scheme on the Xilinx Artix-7 field-programming gate array AC701 board. Performance of the proposed architecture has been validated and compared through hardware cosimulation with variety of synthetic and experimental signals. [ABSTRACT FROM PUBLISHER]

A novel air-to-ground (ATG) communication system, which is based on adaptive modulation and beamforming enabled by automatic dependent surveillance—broadcast (ADS-B) and multilateration techniques, is presented in this paper. From an aircraft geolocation perspective, the proposed multilateration technique uses the time-difference-of-arrival (TDOA), angle-of-arrival (AOA), and frequency-difference-of-arrival (FDOA) features within the ADS-B signal to implement the hybrid geolocation mechanism. Moreover, this hybrid mechanism aims for the optimal selection of multilateration sensors to provide a precise aircraft geolocation estimate by minimizing the geometric dilution-of-precision (GDOP) metric and imparts significant resilience to the current ADS-B-based geolocation framework to withstand any form of attack involving aircraft impersonation and ADS-B message infringement. From an ATG communication perspective, the ground base stations can use this hybrid aircraft geolocation estimate to dynamically adapt their modulation parameters and transmission beampattern in an effort to provide a high-data-rate secure ATG communication link. Additionally, we develop a hardware prototype that is highly accurate in estimating AOA data and facilitating TDOA and FDOA extraction associated with the received ADS-B signal. This hardware setup for the ADS-B-based ATG system is analytically established and validated with commercially available universal software-defined radio peripheral units. This hardware setup displays 1.5° AOA estimation accuracy, whereas the simulated geolocation accuracy is approximately 30 m over 100 nautical miles for a typical aircraft trajectory. The adaptive modulation and beamforming approach assisted by the proposed GDOP-minimization-based multilateration strategy achieves significant enhancement in throughput and reduction in packet error rate. [ABSTRACT FROM AUTHOR]

Improved video coding techniques introduced in the H.265/High Efficiency Video Coding (HEVC) standard allow video encoders to achieve better compression efficiencies. On the other hand, the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions. This paper presents a computationally scalable algorithm and its hardware architecture able to support intra encoding up to 2160p@30 frames/s resolution. The scalability allows a tradeoff between the throughput and the compression efficiency. In particular, the encoder is able to check a variable number of candidate modes. The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate–distortion analysis and enable the evaluation of a great number of candidate intra modes. The encoder preselects candidate modes by the processing of $8\times 8$ predictions computed from original samples. The preselection shares hardware resources used for the processing of predictions generated from reconstructed samples. To support intra $4\times 4$ modes for the 2160p@30 frames/s resolution, the encoder incorporates a separate reconstruction loop. The processing of blocks with different sizes is interleaved to compensate for the delay of reconstruction loops. Implementation results show that the encoder utilizes 1086k gates and 52-kB on-chip memories for TSMC 90 nm. The main reconstruction loop can operate at 400 MHz, whereas the remaining modules work at 200 MHz. For 2160p@30 frames/s videos, the average BD-rate is 5.46% compared with that of the HM software. [ABSTRACT FROM PUBLISHER]

Linear spectral unmixing is nowadays an essential tool to analyze remotely sensed hyperspectral images. Although many different contributions have been uncovered during the last two decades, the majority of them are based on dividing the whole process of linearly unmixing a given hyperspectral image into three sequential steps: 1) estimation of the number of endmembers that are present in the hyperspectral image under consideration; 2) extraction of these endmembers from the hyperspectral data set; and 3) calculation of the abundances associated with the endmembers induced in the previous step per each mixed pixel of the image. Although this de facto processing chain has proven to be accurate enough for unmixing most of the images collected by hyperspectral remote sensors, it is also true that it is not exempt of drawbacks, such as the fact that all the possible combinations of algorithms in order to fully unmix a hyperspectral image according to the aforementioned processing chain demand a formidable computational effort, which tends to be higher the better the performance of the designed unmixing chain is. This troublesome issue unfortunately prevents the use of hyperspectral imaging technology in applications under real-time constraints, in which hyperspectral images have to be analyzed in a short period of time. Hence, there is a clear need to face the challenge of fully exploiting the unquestionable benefits of the hyperspectral imaging technology for these applications, but concurrently overcoming the limitations imposed by the computationally complex nature of the processes involved. For this purpose, this paper introduces a novel algorithm named fast algorithm for linearly unmixing hyperspectral images (FUN), which is capable of fully unmixing a hyperspectral image with at least the same accuracy than state-of-the-art approaches while demanding a much lower computational effort, independent of the characteristics of the image under analysis. The FUN algorithm is based on the concept of orthogonal projections and allows performing the estimation of the number of endmembers and their extraction simultaneously, using the modified Gram–Schmidt method. The operations performed by the FUN algorithm are simple and can be easily parallelized. Moreover, this algorithm is able to calculate the abundances using very similar operations, also based on orthogonal projections, which makes it easier to achieve a hardware implementation to perform the entire unmixing process. The benefits of our proposal are demonstrated with a diverse set of artificially generated hyperspectral images and with the well-known AVIRIS Cuprite image, for which the proposed FUN algorithm is able to reduce in a factor of more than 31 times the time required for processing it, while providing a better unmixing performance than traditional methods. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new hardware-efficient adaptive binary range coder (ABRC) and its very-large-scale integration (VLSI) architecture. To achieve this, we follow an approach that allows to reduce the bit capacity of the multiplication needed in the interval division part and shows how to avoid the need to use a loop in the renormalization part of ABRC. The probability estimation in the proposed ABRC is based on a lookup table free virtual sliding window. To obtain a higher compression performance, we propose a new adaptive window size selection algorithm. In comparison with an ABRC with a single window, the proposed system provides a faster probability adaptation at the initial encoding/decoding stage, and more accurate probability estimation for very low entropy binary sources. We show that the VLSI architecture of the proposed ABRC attains a throughput of 105.92 MSymbols/s on the FPGA platform, and consumes 18.15 mW for the dynamic part power. In comparison with the state-of-the-art MQ-coder (used in JPEG2000 standard) and the M-coder (used in H.264/Advanced Video Coding and H.265/High Efficiency Video Coding standards), the proposed ABRC architecture provides comparable throughput, reduced memory, and power consumption. Experimental results obtained for a wavelet video codec with JPEG2000-like bit-plane entropy coder show that the proposed ABRC allows to reduce the bit rate by 0.8%–8% in comparison with the MQ-coder and from 1.0%–24.2% in comparison with the M-coder. [ABSTRACT FROM PUBLISHER]

To exploit the abundant computational power of the world’s fastest supercomputers, an even workload distribution to the typically heterogeneous compute devices is necessary. While relatively accurate performance models exist for conventional CPUs, accurate performance estimation models for modern GPUs do not exist. This paper presents two accurate models for modern GPUs: a sampling-based linear model, and a model based on machine-learning (ML) techniques which improves the accuracy of the linear model and is applicable to modern GPUs with and without caches. We first construct the sampling-based linear model to predict the runtime of an arbitrary OpenCL kernel. Based on an analysis of NVIDIA GPUs’ scheduling policies we determine the earliest sampling points that allow an accurate estimation. The linear model cannot capture well the significant effects that memory coalescing or caching as implemented in modern GPUs have on performance. We therefore propose a model based on ML techniques that takes several compiler-generated statistics about the kernel as well as the GPU’s hardware performance counters as additional inputs to obtain a more accurate runtime performance estimation for modern GPUs. We demonstrate the effectiveness and broad applicability of the model by applying it to three different NVIDIA GPU architectures and one AMD GPU architecture. On an extensive set of OpenCL benchmarks, on average, the proposed model estimates the runtime performance with less than 7 percent error for a second-generation GTX 280 with no on-chip caches and less than 5 percent for the Fermi-based GTX 580 with hardware caches. On the Kepler-based GTX 680, the linear model has an error of less than 10 percent. On an AMD GPU architecture, Radeon HD 6970, the model estimates with 8 percent of error rates. The proposed technique outperforms existing models by a factor of 5 to 6 in terms of accuracy. [ABSTRACT FROM AUTHOR]