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Hidayetoğlu et al. propose a novel memory-centric algorithm to reconstruct X-ray CT images in the SC19 article entitled “MemXCT: Memory-Centric X-ray CT Reconstruction with Massive Parallelization”. They formulate the reconstruction with several SpMVs, and propose two memory-centric optimizations to improve cache locality for better memory bandwidth utilization, i.e., a two-level pseudo-Hilbert ordering and a multi-stage input buffering. In this article, we present our results on reproducing that article to show its effectiveness and generality, as part of the SC20 Student Cluster Competition Reproducibility Challenge. We reproduce the execution time and memory bandwidth tests in that article on various architectures, including Intel CPUs, AMD CPUs, and NVIDIA GPUs. We further analyze the bottleneck on different architectures by comparing the achieved memory bandwidth with the peak bandwidth on those architectures. We then reproduce the strong scaling test on CPU and GPU clusters with different scales, and use the proposed algorithm to reconstruct three new X-ray computed tomograms. [ABSTRACT FROM AUTHOR]

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits. [ABSTRACT FROM AUTHOR]

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

This paper introduces video domain generalization where most video classification networks degenerate due to the lack of exposure to the target domains of divergent distributions. We observe that the global temporal features are less generalizable, due to the temporal domain shift that videos from other unseen domains may have an unexpected absence or misalignment of the temporal relations. This finding has motivated us to solve video domain generalization by effectively learning the local-relation features of different timescales that are more generalizable, and exploiting them along with the global-relation features to maintain the discriminability. This paper presents the VideoDG framework with two technical contributions. The first is a new deep architecture named the Adversarial Pyramid Network, which improves the generalizability of video features by capturing the local-relation, global-relation, and cross-relation features progressively. On the basis of pyramid features, the second contribution is a new and robust approach of adversarial data augmentation that can bridge different video domains by improving the diversity and quality of augmented data. We construct three video domain generalization benchmarks in which domains are divided according to different datasets, different consequences of actions, or different camera views, respectively. VideoDG consistently outperforms the combinations of previous video classification models and existing domain generalization methods on all benchmarks. [ABSTRACT FROM AUTHOR]

Availability of a common, shared benchmark to provide repeatable, quantifiable, and comparable results is an added value for any scientific community. International consortia provide benchmarks in a wide range of domains, being normally used by industry, vendors, and researchers for evaluating their software products. In this regard, a benchmark of untimed Petri net models was developed to be used in a yearly software competition driven by the Petri net community. However, to the best of our knowledge there is not a similar benchmark to evaluate solution techniques for Petri nets with timing extensions. In this paper, we propose an evaluation framework for the comparative analysis of generalized stochastic Petri nets (GSPNs) simulation techniques. Although we focus on simulation techniques, our framework provides a baseline for a comparative analysis of different GSPN solvers (e.g., simulators, numerical solvers, or other techniques). The evaluation framework encompasses a set of 50 GSPN models including test cases and case studies from the literature, and a set of evaluation guidelines for the comparative analysis. In order to show the applicability of the proposed framework, we carry out a comparative analysis of steady-state simulators implemented in three academic software tools, namely, GreatSPN, PeabraiN, and TimeNET. The results allow us to validate the trustfulness of these academic software tools, as well as to point out potential problems and algorithmic optimization opportunities. [ABSTRACT FROM AUTHOR]

In this paper, an expression for the Cramér–Rao bound (CRB) on the frequency and damping of electromechanical modes is derived. This provides an invaluable tool when documenting the performance capabilities of mode meter algorithms, as the CRB is used as a benchmark to which mode meter variance may be compared. It is shown that the derived CRB expression is supported by several well-known mode estimation phenomena, and it is numerically validated using the asymptotically efficient Prediction Error Method (PEM) on Monte Carlo simulations of an autoregressive moving average (ARMA) model. Finally, a practical use case is given, in which the CRB on the frequency and damping of an inter-area mode from the miniWECC system is used to compare the performance of several well-known mode meters in a study of how sample size affects accuracy. [ABSTRACT FROM AUTHOR]

The vanilla Few-shot Learning (FSL) learns to build a classifier for a new concept from one or very few target examples, with the general assumption that source and target classes are sampled from the same domain. Recently, the task of Cross-Domain Few-Shot Learning (CD-FSL) aims at tackling the FSL where there is a huge domain shift between the source and target datasets. Extensive efforts on CD-FSL have been made via either directly extending the meta-learning paradigm of vanilla FSL methods, or employing massive unlabeled target data to help learn models. In this paper, we notice that in the CD-FSL task, the few labeled target images have never been explicitly leveraged to inform the model in the training stage. However, such a labeled target example set is very important to bridge the huge domain gap. Critically, this paper advocates a more practical training scenario for CD-FSL. And our key insight is to utilize a few labeled target data to guide the learning of the CD-FSL model. Technically, we propose a novel Generalized Meta-learning based Feature-Disentangled Mixup network, namely GMeta-FDMixup. We make three key contributions of utilizing GMeta-FDMixup to address CD-FSL. Firstly, we present two mixup modules – mixup-P and mixup-M that help facilitate utilizing the unbalanced and disjoint source and target datasets. These two novel modules enable diverse image generation for training the model on the source domain. Secondly, to narrow the domain gap explicitly, we contribute a novel feature disentanglement module that learns to decouple the domain-irrelevant and domain-specific features. By stripping the domain-specific features, we alleviate the negative effects caused by the domain inductive bias. Finally, we repurpose a new contrastive learning module, dubbed ConL. ConL prevents the model from only capturing category-related features via introducing contrastive loss. Thus, the generalization ability on novel categories is improved. Extensive experimental results on two benchmarks show the superiority of our setting and the effectiveness of our method. Code and models will be released. [ABSTRACT FROM AUTHOR]

Extracting robust and discriminative local features from images plays a vital role for long term visual localization, whose challenges are mainly caused by the severe appearance differences between matching images due to the day-night illuminations, seasonal changes, and human activities. Existing solutions resort to jointly learning both keypoints and their descriptors in an end-to-end manner, leveraged on large number of annotations of point correspondence which are harvested from the structure from motion and depth estimation algorithms. While these methods show improved performance over non-deep methods or those two-stage deep methods, i.e., detection and then description, they are still struggled to conquer the problems encountered in long term visual localization. Since the intrinsic semantics are invariant to the local appearance changes, this paper proposes to learn semantic-aware local features in order to improve robustness of local feature matching for long term localization. Based on a state of the art CNN architecture for local feature learning, i.e., ASLFeat, this paper leverages on the semantic information from an off-the-shelf semantic segmentation network to learn semantic-aware feature maps. The learned correspondence-aware feature descriptors and semantic features are then merged to form the final feature descriptors, for which the improved feature matching ability has been observed in experiments. In addition, the learned semantics embedded in the features can be further used to filter out noisy keypoints, leading to additional accuracy improvement and faster matching speed. Experiments on two popular long term visual localization benchmarks (Aachen Day and Night v1.1, Robotcar Seasons) and one challenging indoor benchmark (InLoc) demonstrate encouraging improvements of the localization accuracy over its counterpart and other competitive methods. [ABSTRACT FROM AUTHOR]

As the rate at which scientific work is published continues to increase, so does the need to discern high-impact publications. In recent years, there have been several approaches that seek to rank publications based on their expected citation-based impact. Despite this level of attention, this research area has not been systematically studied. Past literature often fails to distinguish between short-term impact, the current popularity of an article, and long-term impact, the overall influence of an article. Moreover, the evaluation methodologies applied vary widely and are inconsistent. In this work, we aim to fill these gaps, studying impact-based ranking theoretically and experimentally. First, we provide explicit definitions for short-term and long-term impact, and introduce the associated ranking problems. Then, we identify and classify the most important ideas employed by state-of-the-art methods. After studying various evaluation methodologies of the literature, we propose a specific benchmark framework that can help us better differentiate effectiveness across impact aspects. Using this framework we investigate: (1) the practical difference between ranking by short- and long-term impact, and (2) the effectiveness and efficiency of ranking methods in different settings. To avoid reporting results that are discipline-dependent, we perform our experiments using four datasets from different scientific disciplines. [ABSTRACT FROM AUTHOR]

RDF is being increasingly considered in a broad range of information management scenarios. Governments, large corporations, startups, and other organizations around the world are using RDF as a data model to represent and share knowledge. However, there is still a long evolutionary track with multiple challenges for RDF reaching the scale of the most recent Big Data intensive applications (e.g., Smart Cities, Sensor Networks, eHealth, Internet of Things). In this survey, we review the usage of NoSQL databases to the storage of large RDF graphs by rehearsing the latest surveys and expanding their findings by updating proposals and bringing light to aspects such as model mapping between RDF and NoSQL, triple indexing and partitioning, graph fragmentation and data caching. Moreover, we explain how the surveyed works extended the RDF capabilities so the datasets can benefit of the characteristics of scalability, schemaless data, and better overall performance of NoSQL databases. The survey summarizes the current state of art, discusses open problems, and proposes a Reference Architecture (RA). For the best of our knowledge, this is the first survey where the focus is solely on papers that use one or more NoSQL systems for the RDF persistence. [ABSTRACT FROM AUTHOR]

In this paper, a compact log-periodic dipole array (LPDA) antenna is developed at 0.5–10 GHz. This LPDA structure constitutes fewer dipole elements than a conventional LPDA antenna that exhibits similar resonant frequencies. In the design of a miniaturized LPDA antenna, various size-reduction techniques have been proposed in the open literature to decrease the lateral size of a conventional LPDA. However, little or no attention has been focused on reducing the size of the LPDA antenna by shortening the boom or axial length. In pursuit of reducing the total length of a conventional LPDA, a dual-band dipole antenna is proposed as the radiating elements for the LPDA antenna in this paper. The proposed dipole structure is a printed half-wave principal dipole loaded with a pair of resistive structures via subfeeding lines. A pair of resistive loads forms the auxiliary (secondary) dipole of the proposed dipole antenna. The structure of the proposed dual-band dipole is achieved without a ground plane as opposed to many existing dual-band antenna types. As a result, the dipole antenna has a simple geometry with omnidirectional characteristics. Also, the feeding structure of this dipole can provide an extra degree of freedom to tune the antenna for matching purposes. A 25-element LPDA antenna is designed with a much reduced boom length compared with existing LPDA structures. To confirm the feasibility of the technique, the experimental results of the proposed LPDA prototype were analyzed and juxtaposed with a benchmark LPDA. [ABSTRACT FROM AUTHOR]

Electrical incidents provide valuable learning opportunities if root causes are identified. Incident investigations which are unable to identify all root causes and address the shortcomings in the safety management system may result in recurring incidents. It is important that the entire incident investigation programme be guided by proven techniques and executed in a well-established manner. In a white paper titled “The Development of Questions to Determine the Effectiveness of the Incident Investigation Process for Electrical Incidents,” the authors analyzed commonly applied incident investigation techniques and suggested six salient incident investigation process requirements irrespective of the techniques used. This paper also suggested eight constructs, which could be used to determine the effectiveness of the incident investigation process. This paper utilizes the established learning and applies it to a large steel plant. A number of serious electrical incidents spanning many years at different operating units were analytically reviewed. A study of the organizational policy and one completed incident investigation report is analyzed to determine the effectiveness of the incident investigation process. Shortcomings in the process are discussed and possible salient practices that derogate from effective investigations are proposed. This paper forms part of a larger research project to determine the effectiveness of the application of the incident investigation process. The results and recommendations from the study aim to provide generic benchmarking of the incident investigation process, which could be used by organizations to improve its electrical safety performance. [ABSTRACT FROM AUTHOR]

Recent work has shown that convolutional networks can be substantially deeper, more accurate, and efficient to train if they contain shorter connections between layers close to the input and those close to the output. In this paper, we embrace this observation and introduce the Dense Convolutional Network (DenseNet), which connects each layer to every other layer in a feed-forward fashion. Whereas traditional convolutional networks with $L$ L layers have $L$ L connections—one between each layer and its subsequent layer—our network has $\frac{L(L+1)}{2}$ L (L + 1) 2 direct connections. For each layer, the feature-maps of all preceding layers are used as inputs, and its own feature-maps are used as inputs into all subsequent layers. DenseNets have several compelling advantages: they alleviate the vanishing-gradient problem, encourage feature reuse and substantially improve parameter efficiency. We evaluate our proposed architecture on four highly competitive object recognition benchmark tasks (CIFAR-10, CIFAR-100, SVHN, and ImageNet). DenseNets obtain significant improvements over the state-of-the-art on most of them, whilst requiring less parameters and computation to achieve high performance. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

In high-throughput drug screening applications, as manual drug sample delivery is time-consuming and error-prone, there is an urgent need for accurate and efficient drug sample delivery biochip for large-scale microwell arrays. This paper proposes a new microfluidic biochip architecture, where drugs are automatically prepared with different concentration values, and then delivered into multiple microwells. For large-scale drug sample delivery biochips, the routing of drug sample delivery channels is a very challenging task without effective routing solutions. This paper proposes an ultrafast rule-based escape routing method, called URBER, to address the large-scale routing of drug sample delivery channels, which scales well in both runtime and memory even for a very large problem size. URBER runs very fast because it routes channels based on a set of predefined rules, which avoids runtime consumed in solution space exploration. All benchmarks for 30 ${\le }~{N}$ , ${M} {\le }~100$ have been tested, where ${N}$ and ${M}$ are the number of columns and rows of the terminal array. Among these benchmarks, about ~91.9% are routed with optimal solutions, and the runtime is order of magnitudes faster than optimal min-cost flow-based methods (speedup is from ~600 to ~340 k). Specifically, for all benchmarks with (${M}/{N}$) ${\in }$ ((3/4), (4/3)), optimal routing solutions are always obtained. URBER also shows promise of routing large-scale designs with up to 500 k terminals efficiently. [ABSTRACT FROM AUTHOR]

While early AutoML frameworks focused on optimizing traditional ML pipelines and their hyperparameters, a recent trend in AutoML is to focus on neural architecture search. In this paper, we introduce Auto-PyTorch, which brings together the best of these two worlds by jointly and robustly optimizing the network architecture and the training hyperparameters to enable fully automated deep learning (AutoDL). Auto-PyTorch achieves state-of-the-art performance on several tabular benchmarks by combining multi-fidelity optimization with portfolio construction for warmstarting and ensembling of deep neural networks (DNNs) and common baselines for tabular data. To thoroughly study our assumptions on how to design such an AutoDL system, we additionally introduce a new benchmark on learning curves for DNNs, dubbed LCBench, and run extensive ablation studies of the full Auto-PyTorch on typical AutoML benchmarks, eventually showing that Auto-PyTorch performs better than several state-of-the-art competitors. [ABSTRACT FROM AUTHOR]

This paper presents an approach to obtain high torque density in induction motor (IM) design by optimizing the search algorithms and processes. Optimal design of electrical machines has many sub-optimal peaks and requires significant computation time. To solve this problem, this paper proposes a new cost pattern value method (CPVM) for local search algorithms employed in optimal design. The CPVM concept is an intelligent strategy that digitizes the gradient over the searching region by sharing information between neighboring points. When the algorithm converges quickly to local optimum by a normalized weight method, it provides a mechanism to escape from that region. The validity of the proposed approach was evaluated using a benchmark function, and it was applied to optimal design of a 260 kW IM to maximize torque production based on a finite-element analysis. For better accuracy, we employ slip-frequency analysis compatible with vector control for an IM numerical analysis. [ABSTRACT FROM AUTHOR]

In this paper, we present positionable photonic waveguide arrays that are developed for optical chip-to-chip alignment. Partly suspended photonic structures, based on the Si3N4/SiO2 material platform, are equipped with thermal actuators enabling the free end of the structures to be positioned with submicrometer accuracy. A finite-element model is developed to provide insight in the way the design of the system affects the performance. The modeling results show that the expected vertical deflection and rotation are highly dependent on the array design. Measurements of fabricated devices confirm the trends that follow from the model and are used to assess the positioning performance. Moreover, the finite-element analysis gives guidelines for the design parameters of an optimal positionable photonic waveguide array. By following these guidelines, all the requirements for the intended photonic alignment can be fulfilled, which is validated by measurements. The stability over time of the positioning system is experimentally determined and is also sufficient. Measured mode field profiles of partly suspended waveguide beams with 1 \mu \textm \,\, \times 220 nm (width $\times $ thickness) sized waveguide cores show correct waveguiding functionality. Finally, an alignment experiment demonstrates how three adjacent waveguide beams within a positionable waveguide array can be actively aligned with the channels of another photonic chip. [2017-0046] [ABSTRACT FROM PUBLISHER]

This paper investigates the design of non-binary protograph low-density parity-check codes for the Poisson channel with $m$ -ary pulse position modulation. The field order over which the code is constructed is matched to the pulse position modulation order yielding a coded modulation scheme. The optimization of the low-density parity-check code structure is performed via protograph density evolution on a surrogate $m$ -ary erasure channel. The surrogate design is illustrated to be not only accurate, but also robust for a range of practical values of channel background noise and various modulation orders. As a result the proposed codes show excellent performance over the Poisson channel with pulse position modulation outperforming competing schemes. As a side-product of this paper, finite-length benchmarks on the block error probability are provided, together with a union bound to characterize the code performance in the error floor region. [ABSTRACT FROM AUTHOR]

Weight sharing promises to make neural architecture search (NAS) tractable even on commodity hardware. Existing methods in this space rely on a diverse set of heuristics to design and train the shared-weight backbone network, a.k.a. the super-net. Since heuristics substantially vary across different methods and have not been carefully studied, it is unclear to which extent they impact super-net training and hence the weight-sharing NAS algorithms. In this paper, we disentangle super-net training from the search algorithm, isolate 14 frequently-used training heuristics, and evaluate them over three benchmark search spaces. Our analysis uncovers that several commonly-used heuristics negatively impact the correlation between super-net and stand-alone performance, whereas simple, but often overlooked factors, such as proper hyper-parameter settings, are key to achieve strong performance. Equipped with this knowledge, we show that simple random search achieves competitive performance to complex state-of-the-art NAS algorithms when the super-net is properly trained. [ABSTRACT FROM AUTHOR]

Timing-based side and covert channels in processor caches continue to be a threat to modern computers. This work shows for the first time, a systematic, large-scale analysis of Arm devices and the detailed results of attacks the processors are vulnerable to. Compared to x86, Arm uses different architectures, microarchitectural implementations, cache replacement policies, etc., which affects how attacks can be launched, and how security testing for the vulnerabilities should be done. To evaluate security, this paper presents security benchmarks specifically developed for testing Arm processors and their caches. The benchmarks are evaluated with sensitivity tests, which examine how sensitive the benchmarks are to having a correct configuration in the testing phase. Further, to evaluate a large number of devices, this work leverages a novel approach of using a cloud-based Arm device testbed for architectural and security research on timing channels and runs the benchmarks on 34 different physical devices. In parallel, there has been much interest in secure caches to defend the various attacks. Consequently, this paper also investigates secure cache architectures using proposed benchmarks. Especially, this paper implements and evaluates secure PL and RF caches, showing the security of PL and RF caches, but also uncovers new weaknesses. [ABSTRACT FROM AUTHOR]

The empirical nature of Information Retrieval (IR) mandates strong experimental practices. A keystone of such experimental practices is the Cranfield evaluation paradigm. Within this paradigm, the collection of relevance judgments has been the subject of intense scientific investigation. This is because, on one hand, consistent, precise, and numerous judgements are keys to reducing evaluation uncertainty and test collection bias; on the other hand, however, relevance judgements are costly to collect. The selection of which documents to judge for relevance, known as pooling method, has therefore a great impact on IR evaluation. In this paper we focus on the bias introduced by the pooling method, known as pool bias, which affects the reusability of test collections, in particular when building test collections with a limited budget. In this paper we formalize and evaluate a set of 22 pooling strategies based on: traditional strategies, voting systems, retrieval fusion methods, evaluation measures, and multi-armed bandit models. To do this we run a large-scale evaluation by considering a set of 9 standard TREC test collections, in which we show that the choice of the pooling strategy has significant effects on the cost needed to obtain an unbiased test collection. We also identify the least biased pooling strategy in terms of pool bias according to three IR evaluation measures: AP, NDCG, and P@10. [ABSTRACT FROM AUTHOR]

In this paper, we make the first benchmark effort to elaborate on the superiority of using RAW images in the low light enhancement and develop a novel alternative route to utilize RAW images in a more flexible and practical way. Inspired by a full consideration on the typical image processing pipeline, we are inspired to develop a new evaluation framework, Factorized Enhancement Model (FEM), which decomposes the properties of RAW images into measurable factors and provides a tool for exploring how properties of RAW images affect the enhancement performance empirically. The empirical benchmark results show that the Linearity of data and Exposure Time recorded in meta-data play the most critical role, which brings distinct performance gains in various measures over the approaches taking the sRGB images as input. With the insights obtained from the benchmark results in mind, a RAW-guiding Exposure Enhancement Network (REENet) is developed, which makes trade-offs between the advantages and inaccessibility of RAW images in real applications in a way of using RAW images only in the training phase. REENet projects sRGB images into linear RAW domains to apply constraints with corresponding RAW images to reduce the difficulty of modeling training. After that, in the testing phase, our REENet does not rely on RAW images. Experimental results demonstrate not only the superiority of REENet to state-of-the-art sRGB-based methods and but also the effectiveness of the RAW guidance and all components. [ABSTRACT FROM AUTHOR]

Full projector compensation aims to modify a projector input image to compensate for both geometric and photometric disturbance of the projection surface. Traditional methods usually solve the two parts separately and may suffer from suboptimal solutions. In this paper, we propose the first end-to-end differentiable solution, named CompenNeSt++, to solve the two problems jointly. First, we propose a novel geometric correction subnet, named WarpingNet, which is designed with a cascaded coarse-to-fine structure to learn the sampling grid directly from sampling images. Second, we propose a novel photometric compensation subnet, named CompenNeSt, which is designed with a siamese architecture to capture the photometric interactions between the projection surface and the projected images, and to use such information to compensate the geometrically corrected images. By concatenating WarpingNet with CompenNeSt, CompenNeSt++ accomplishes full projector compensation and is end-to-end trainable. Third, to improve practicability, we propose a novel synthetic data-based pre-training strategy to significantly reduce the number of training images and training time. Moreover, we construct the first setup-independent full compensation benchmark to facilitate future studies. In thorough experiments, our method shows clear advantages over prior art with promising compensation quality and meanwhile being practically convenient. [ABSTRACT FROM AUTHOR]

Timing analysis and timing closure are critical steps in digital circuit design. To ensure an error-free design, timing constraints are usually set-based upon the longest path delay from static timing analysis. However, a circuit could have dramatically different internal activity because of the variation of input workload. The path with the longest delay may not be active for certain input workloads, which would enable timing speculation for increased performance. This paper describes an approach to identify the greatest contributors of timing errors and mitigate those errors by replacing certain standard cells in the design. We evaluated our mitigation for several benchmark designs and demonstrated an error-free performance gain up to 37%. The entire design flow uses Synopsys electronic design automation tools and customized scripts, which can be adapted for other designs. [ABSTRACT FROM AUTHOR]

Smartphones dominate the consumer electronics market. Heterogeneous multicore processors are nowadays often integrated into smartphones. The power and performance evaluation of mobile multicore processors is a key issue in their design. This paper is the first to address the issue of improving the power and performance in modern, multicore smartphones by revisiting existing benchmarks used for evaluating these devices. Unlike earlier computers, modern consumer devices execute workloads that are characterized by heterogeneous concurrently running processes, which are launched at different times. Yet, modern smartphones architecture designs are still being evaluated using representative benchmark suites comprised of individual programs. This method of evaluation can be very misleading, as it does not represent the way these devices are actually being used. This paper first proposes a novel learning framework that identifies representative usage patterns of various real workloads, where each representative pattern represents a single class in a heterogeneous collection of actual usage patterns. We then use these representative patterns to optimize the power and performance of common multicore computer architectures integrated into smartphones. Our experiments show that using our representative patterns for optimization results in,on average, 11.5% and 16.7% power and performance improvements, respectively, compared to the state-of-art optimization methods. [ABSTRACT FROM AUTHOR]

Tremendous improvements in the fabrication technology have allowed to scale the physical dimensions of the transistors and also to develop different promising 3-D architectures that may allow continuing Moore’s law. In this paper, we perform a comparative delay analysis of different 3-D device architectures and study the impact of surface roughness and self-heating on the on-current using a comprehensive in-house simulation framework comprising Schrödinger, Poisson, and Boltzmann transport equation solvers and comprising relevant scattering mechanisms and self-heating. Our results highlight that parasitic capacitance can alter the relative ranking of the architectures from delay point of view. We demonstrate that surface roughness can cause architecture and material-dependent current degradation, and hence, it is necessary to account for it in simulation-based benchmarking different architectures. [ABSTRACT FROM AUTHOR]

It was shown earlier that certain primary input values have a negative effect on the fault coverage of a functional test sequence when they appear repeatedly in the sequence. A gate-level sequential test generation procedure based on this observation computed a primary input cube c with preferred values, and generated random functional test sequences that conformed to c with a high probability 0.5 \leq p < 1 . This procedure selected values for p out of a set of possible values, and assigned the same value of p to all the primary inputs. Motivated by the low computational complexity of this procedure, this paper addresses the selection of p and the possibility of using different values of p for different primary inputs. The goal is to increase the fault coverage and reduce the number of functional test sequences. The procedure described in this paper adjusts a functional test sequence to a circuit by complementing values that conflict with c . The procedure requires fewer functional test sequences to reach or exceed the fault coverage of the earlier procedure for benchmark circuits. The procedure can be applied to any functional test sequence or set of functional test sequences. [ABSTRACT FROM AUTHOR]

Low-power is one of the key driving forces in modern very large scale integration systems. Recent studies show that 3-D integrated circuits (ICs) offer a significant power saving over 2-D ICs. However, these studies are mainly limited to two-tier (2-tier) designs. Thus, in this paper, we extend our target to three-tier (3-tier) 3-D ICs. This paper first shows that the one additional tier available in 3-tier 3-D ICs does offer more power saving compared with their 2-tier 3-D IC counterparts, but more careful floorplanning, through-silicon via management, and block folding considerations are required. Second, we find that the 3-tiers can be bonded in several different ways: 1) face-to-back only; 2) face-to-face and face-to-back combined; and 3) back-to-back and face-to-face combined. This paper shows that these choices pose additional challenges in design optimizations for more power saving. Lastly, we develop effective computer-aided-design solutions that are seamlessly integrated into commercial 2-D IC tools to handle 3-tier 3-D IC power optimization under various bonding style options. With our low-power design methods combined, our 3-tier 3-D ICs provide −14.8% more power reduction over 2-tier 3-D ICs, and −36.0% over 2-D ICs in microprocessor cores under the same performance. In full-chip microprocessors, our 3-tier 3-D ICs provide −27.2% more power reduction over 2-D ICs. [ABSTRACT FROM PUBLISHER]

Visual localization enables autonomous vehicles to navigate in their surroundings and augmented reality applications to link virtual to real worlds. Practical visual localization approaches need to be robust to a wide variety of viewing conditions, including day-night changes, as well as weather and seasonal variations, while providing highly accurate six degree-of-freedom (6DOF) camera pose estimates. In this paper, we extend three publicly available datasets containing images captured under a wide variety of viewing conditions, but lacking camera pose information, with ground truth pose information, making evaluation of the impact of various factors on 6DOF camera pose estimation accuracy possible. We also discuss the performance of state-of-the-art localization approaches on these datasets. Additionally, we release around half of the poses for all conditions, and keep the remaining half private as a test set, in the hopes that this will stimulate research on long-term visual localization, learned local image features, and related research areas. Our datasets are available at visuallocalization.net , where we are also hosting a benchmarking server for automatic evaluation of results on the test set. The presented state-of-the-art results are to a large degree based on submissions to our server. [ABSTRACT FROM AUTHOR]

In this paper, we introduce the idea of blockwise classification to count objects. The current mainstream method for counting objects is to regress the density map or to regress the redundant count map via a deep convolutional neural network (CNN). However, these methods suffer from two critical issues: inaccurately generated regression targets and serious sample imbalances. First, the ground truth density map is generated by convolving the dot map using a Gaussian kernel. Because an inappropriate kernel can cover the background or uncover objects, this approach introduces a form of noise, and therefore results in ambiguities when training the networks. Second, inhomogeneously distributed objects often exist in images, which gives rise to a data collection bias. This leads to a long-tailed distribution of region counts, which is a typical characteristic that occurs with imbalanced samples; therefore, underestimations in high-density regions and overestimations in low-density regions are common. In this paper, we address these two issues within one framework—blockwise count level classification. The intuition behind this idea is that while it may not be possible to provide an exact count of pixels or patches, it is possible to provide a count of a region that falls within a certain interval with high confidence. Our method classifies the count levels of each block produced by nonlinearly quantizing the continuous counts, thus transforming the imbalance of sample patch counts into a class imbalance of count levels. Consequently, an information-entropy-inspired loss can be applied to alleviate this issue. Through ablative studies, we analyze the impact of imbalanced data, Gaussian kernel sizes, quantization errors, and the effectiveness of each module in our method. Without bells and whistles, our method outperforms or performs competitively with other state-of-the-art approaches on seven object-counting benchmarks, including four crowd-counting datasets from ShanghaiTech, WorldExpo’10, UCF-QNRF and UCF_CC_50, one vehicle-counting dataset (TRANCOS), one maize-tassel-counting dataset (MTC), and one challenging sonar fish-counting dataset that we constructed. The results suggest that our framework provides a strong and improved baseline for object counting. [ABSTRACT FROM AUTHOR]

Image retargeting techniques adjust images into different sizes and have attracted much attention recently. Objective quality assessment (OQA) of image retargeting results is often desired to automatically select the best results. Existing OQA methods train a model using some benchmarks (e.g., RetargetMe), in which subjective scores evaluated by users are provided. Observing that it is challenging even for human subjects to give consistent scores for retargeting results of different source images (diff-source-results), in this paper we propose a learning-based OQA method that trains a General Regression Neural Network (GRNN) model based on relative scores—which preserve the ranking—of retargeting results of the same source image (same-source-results). In particular, we develop a novel training scheme with provable convergence that learns a common base scalar for same-source-results. With this source specific offset, our computed scores not only preserve the ranking of subjective scores for same-source-results, but also provide a reference to compare the diff-source-results. We train and evaluate our GRNN model using human preference data collected in RetargetMe. We further introduce a subjective benchmark to evaluate the generalizability of different OQA methods. Experimental results demonstrate that our method outperforms ten representative OQA methods in ranking prediction and has better generalizability to different datasets. [ABSTRACT FROM AUTHOR]

Fault diagnosis of bearings using classification techniques plays an important role in industrial applications, and, hence, has received increasing attention. Recently, significant efforts have been made to develop various methods for bearing fault classification and the application of Case Western Reserve University (CWRU) data for validation has become a standard reference to test the fault classification algorithms. However, a systematic research for evaluating bearing fault classification performance using the CWRU data is still lacking. This paper aims to provide a comprehensive benchmark analysis of the CWRU data using various entropy and classification methods. The main contribution of this paper is applying entropy-based fault classification methods to establish a benchmark analysis of entire CWRU datasets, aiming to provide a proper assessment of any new classification methods. Recommendations are provided for the selection of the CWRU data to aid in testing new fault classification algorithms, which will enable the researches to develop and evaluate various diagnostic algorithms. In the end, the comparison results and discussion are reported as a useful baseline for future research. [ABSTRACT FROM AUTHOR]

Wide-area data and algorithms in large power systems are creating new opportunities for implementation of measurement-based dynamic load modeling techniques. These techniques improve the accuracy of dynamic load models, which are an integral part of transient stability analysis. Measurement-based load modeling techniques commonly assume response error is correlated to system or model accuracy. Response error is the difference between simulation output and phasor measurement units (PMUs) samples. This paper investigates similarity measures, output types, simulation time spans, and disturbance types used to generate response error and the correlation of the response error to system accuracy. This paper aims to address two hypotheses: 1) can response error determine the total system accuracy? and 2) can response error indicate if a dynamic load model being used at a bus is sufficiently accurate? The results of the study show only specific combinations of metrics yield statistically significant correlations, and there is a lack of pattern of combinations of metrics that deliver significant correlations. Less than 20% of all simulated tests in this study resulted in statistically significant correlations. These outcomes highlight concerns with common measurement-based load modeling techniques, raising awareness to the importance of careful selection and validation of similarity measures and response output metrics. Naive or untested selection of metrics can deliver inaccurate and misleading results. [ABSTRACT FROM AUTHOR]

Recently, much attention has been paid to approximate computing, a novel design paradigm for error-tolerant applications. It can significantly reduce area, power, and delay of circuits by introducing an acceptable amount of error. In this paper, we propose a new heuristic method for two-level approximate logic synthesis. The problem is to identify an approximate sum-of-product (SOP) expression under a given error rate (ER) constraint so that it has the fewest literals. The basic idea of our method is to find an optimal set of input combinations for 0-to-1 output complement (SICC). For this purpose, we first identify all prime SICCs, which are fundamental SICCs in the sense that the optimal SICC is very likely to be a union of a subset of the prime SICCs. Then, we search among all subsets of the prime SICCs the optimal subset, which leads to a final good approximate SOP. We further propose four speed-up techniques. The experiments on benchmarks showed that our method is better than the previous state-of-the-art method and our speed-up techniques are effective. For an ER threshold of 0.8%, our method can reduce 15.8% literals on average. [ABSTRACT FROM AUTHOR]

Social-spider optimization (SSO) is a new nature-inspired algorithm of the swarm intelligence field to global optimization applications, which is based on the simulation of cooperative behavior of social spiders. To enhance the performance of the standard SSO, a modified SSO (MSSO) approach based on beta distribution and natural gradient local search was proposed in this paper. In order to verify the performance of the MSSO, tests using Loney’s solenoid benchmark and a brushless direct current motor benchmark are realized comparing the effectiveness of the SSO and the proposed MSSO. The results of this paper demonstrated that the MSSO performance is promising in electromagnetics optimization. [ABSTRACT FROM AUTHOR]

Placement and packing are two important but separated optimization steps in a conventional field programmable gate array (FPGA) implementation flow. A packing engine clusters logic elements, like lookup tables and flip-flops, into configurable logic blocks, while a placement engine determines their physical locations in FPGA layouts. This paper presents a new paradigm for FPGA placement without an explicit packing stage. In the proposed framework, the solution spaces of placement and packing are simultaneously explored in a smooth and elegant way. Our experiments on ISPD 2016 and 2017 benchmark suites demonstrate the effectiveness of the proposed framework. [ABSTRACT FROM AUTHOR]

In this paper, a new hybrid permanent magnet (PM) synchronous motor with two-part rotor is proposed. The new motor is composed of surface mounted and interior magnet rotor segments on a stepped skewed shaft. The hybrid topology has wider constant power speed ratio than conventional surface mounted PM motors with relatively the same torque density. No-load and on-load finite-element analyses (FEA) are performed independently for both surface PM and interior PM synchronous motor. Superposition of the results is gathered to obtain the actual performance of the hybrid motor. The 2-D FEA results with skewed models are also performed at the final stage of the design. A prototype motor is manufactured and experimental results are obtained. Good agreement is observed between the simulations and test data for the proposed motor. [ABSTRACT FROM AUTHOR]

Unsupervised domain adaptation addresses the problem of transferring knowledge from a well-labeled source domain to an unlabeled target domain where the two domains have distinctive data distributions. Thus, the essence of domain adaptation is to mitigate the distribution divergence between the two domains. The state-of-the-art methods practice this very idea by either conducting adversarial training or minimizing a metric which defines the distribution gaps. In this paper, we propose a new domain adaptation method named adversarial tight match (ATM) which enjoys the benefits of both adversarial training and metric learning. Specifically, at first, we propose a novel distance loss, named maximum density divergence (MDD), to quantify the distribution divergence. MDD minimizes the inter-domain divergence (“match” in ATM) and maximizes the intra-class density (“tight” in ATM). Then, to address the equilibrium challenge issue in adversarial domain adaptation, we consider leveraging the proposed MDD into adversarial domain adaptation framework. At last, we tailor the proposed MDD as a practical learning loss and report our ATM. Both empirical evaluation and theoretical analysis are reported to verify the effectiveness of the proposed method. The experimental results on four benchmarks, both classical and large-scale, show that our method is able to achieve new state-of-the-art performance on most evaluations. [ABSTRACT FROM AUTHOR]

This paper studies the optimization of mechanics and resource allocation in linear vibration energy harvesters operating under an overall size constraint. In such harvesters, the volume aspect ratio and the stroke direction should be carefully selected to maximize output power and power density. Further, because the proof mass and spring stroke must share the available size along the stroke direction, a mass-stroke design trade-off results; the trade-off is optimized here. The optimization further leads to a universal metric the enables the comparison of linear vibration energy harvesters designed to operate in a limited volume. Examination of this metric results in guidelines and best practices for selecting harvester dimensions and shape for a given volume constraint, all based on the dimensional harvester optimization for maximum size-constrained output power. This paper offers several key contributions. First, it provides an evaluation and optimization of the impact that volume shaping and volumetric resource allocation have on the output power of linear vibration energy harvesters. Second, it develops a “universal normalized surface” relating output power to dimensional harvester design. The surface expresses the performance limit of space-constrained linear vibration energy harvesters in terms of their output power density. This leads to universal guidelines for harvester design. Finally, benchmarking harvesters reported in the literature against the universal surface demonstrates that their output performances lie on or below the surface, despite large variations in their exogenous design variables such as vibration amplitude, frequency, volume etc. Thus, this paper offers an effective method to evaluate mechanical design and optimization in state-of-the-art linear vibration energy harvesters under volume constraints, a scenario suited for IoT applications. [2021-0074] [ABSTRACT FROM AUTHOR]

Partial multi-label learning (PML) deals with the problem where each training example is associated with an overcomplete set of candidate labels, among which only some candidate labels are valid. The task of PML naturally arises in learning scenarios with inaccurate supervision, and the goal is to induce a multi-label predictor which can assign a set of proper labels for unseen instance. The PML training procedure is prone to be misled by false positive labels concealed in the candidate label set, which serves as the major modeling difficulty for partial multi-label learning. In this paper, a novel two-stage PML approach is proposed which works by eliciting credible labels from the candidate label set for model induction. In the first stage, the labeling confidence of candidate label for each PML training example is estimated via iterative label propagation. In the second stage, by utilizing credible labels with high labeling confidence, multi-label predictor is induced via pairwise label ranking coupled with virtual label splitting or maximum a posteriori (MAP) reasoning. Experimental studies show that the proposed approach can achieve highly competitive generalization performance by excluding most false positive labels from the training procedure via credible label elicitation. [ABSTRACT FROM AUTHOR]

This paper is concerned with the problem of Security-Constrained Unit Commitment (SCUC) which is a long-standing challenge in power system engineering faced by system operators and utility companies on a daily basis. We consider a detailed variant of this problem that suffers from complexities posed by the presence of binary variables, the uncertainty of renewable sources and security constraints. A convex relaxation is formulated which is capable of finding feasible solutions within a provable distance from global optimality. We demonstrate the performance of this approach on detailed and challenging instances of SCUC with IEEE and PEGASE benchmark cases from Matpower. The proposed approach is able to handle over 12,000 binary variables and 2 million continuous variables with significant improvement in solution quality over commonly-used off-the-shelf solvers and other methods of convex relaxation. [ABSTRACT FROM AUTHOR]

Layout synthesis, an important step in quantum computing, processes quantum circuits to satisfy device layout constraints. In this paper, we construct QUEKO benchmarks for this problem, which have known optimal depths and gate counts. We use QUEKO to evaluate the optimality of current layout synthesis tools, including Cirq from Google, Qiskit from IBM, ⟨t|ket〉 from Cambridge Quantum Computing, and a recent academic work. To our surprise, despite over a decade of research and development by academia and industry on compilation and synthesis for quantum circuits, we are still able to demonstrate large optimality gaps: 1.5-12x on average on a smaller device and 5-45x on average on a larger device. This suggests substantial room for improvement of the efficiency of quantum computer by better layout synthesis tools. Finally, we also prove the NP-completeness of the layout synthesis problem for quantum computing. We have made the QUEKO benchmarks open-source. [ABSTRACT FROM AUTHOR]

In order to improve the availability of wind turbines and to avoid catastrophic consequences, the detection of faults in their earlier occurrence is fundamental. This paper proposes the development of a fault diagnosis scheme relying on identified fuzzy models. The fuzzy theory is exploited since it allows approximating uncertain models and managing noisy data. These fuzzy models, in the form of Takagi–Sugeno prototypes, represent the residual generators used for fault detection and isolation (FDI). A wind turbine benchmark is used to validate the achieved performances of the designed FDI scheme. Finally, extensive comparisons with different fault diagnosis methods highlight the features of the suggested solution. [ABSTRACT FROM PUBLISHER]

Automatic identification of custom instructions (CI) is the process of supporting the programmer in choosing automatically beneficial parts of the application source code that can then be synthesized and run on dedicated hardware. Identification is typically modeled as choosing a subgraph from a graph, representing the application, that has the highest speedup potential when implemented in custom hardware, and that fulfills the constraints of convexity and of a given maximum number of inputs and outputs. Existing algorithms for CI identification either enumerate all the valid subgraphs under the constraints of convexity and I/O, or return the subset of all maximal valid subgraphs with respect to convexity only. The downside of the former approach is that enumerating all valid subgraphs is costly, especially for large values of input and output constraints, while we may be interested in the subgraphs which obtain the best speedup only. Instead, the latter approach may fail to find a feasible solution, since the valid subgraphs with respect to convexity only can be too large to be useful. In this paper, we present a novel approach which attempts to fill the gap between the existing methods. In particular, we present an algorithm that enumerates the subset of all maximum valid subgraphs with respect to convexity and number of inputs and outputs. Our method revisits and combines the existing approaches and yields an algorithm which is effective and outperforms the state-of-the-art for large values of input and output constraints. [ABSTRACT FROM PUBLISHER]

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I – V and G – V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: gm/{I}\text {d} , gm/gds , fT and fT/{I}d{V}d , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40~\text V^-1 , for currents lower than 10 nA/ \mu \textm ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ \mu \textm . [ABSTRACT FROM PUBLISHER]

This correspondence paper proposes an improved version of the self-constructing neural fuzzy inference network (SONFIN), called soft-boosted SONFIN (SB-SONFIN). The design softly boosts the learning process of the SONFIN in order to decrease the error rate and enhance the learning speed. The SB-SONFIN boosts the learning power of the SONFIN by taking into account the numbers of fuzzy rules and initial weights which are two important parameters of the SONFIN, SB-SONFIN advances the learning process by: 1) initializing the weights with the width of the fuzzy sets rather than just with random values and 2) improving the parameter learning rates with the number of learned fuzzy rules. The effectiveness of the proposed soft boosting scheme is validated on several real world and benchmark datasets. The experimental results show that the SB-SONFIN possesses the capability to outperform other known methods on various datasets. [ABSTRACT FROM PUBLISHER]

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. [ABSTRACT FROM PUBLISHER]

We present a practical implementation of a leaky-wave thinned phased array in printed circuit board (PCB) technology. In this paper, we demonstrate that a reduction of the grating lobes, and therefore an improved gain in a thinned phased array, with respect to standard solutions, is achieved by virtue of the angular filtering introduced by a leaky-wave cavity in the far field. The presented array is designed in PCB and integrated with an inductive partial reflective surface. A full study of the performances of the $7\times 7$ phased array antenna for several scanning angles and frequencies is presented. This paper shows an improved gain, directivity, grating lobe level, back lobe level, beam efficiency, and active reflection coefficient with respect to a reference solution based on $2\times 2$ subarrays. The results are validated via the measurements of a $3\times 3$ array prototype. [ABSTRACT FROM PUBLISHER]

The heterogeneity in recently published knowledge graph embedding models’ implementations, training, and evaluation has made fair and thorough comparisons difficult. To assess the reproducibility of previously published results, we re-implemented and evaluated 21 models in the PyKEEN software package. In this paper, we outline which results could be reproduced with their reported hyper-parameters, which could only be reproduced with alternate hyper-parameters, and which could not be reproduced at all, as well as provide insight as to why this might be the case. We then performed a large-scale benchmarking on four datasets with several thousands of experiments and 24,804 GPU hours of computation time. We present insights gained as to best practices, best configurations for each model, and where improvements could be made over previously published best configurations. Our results highlight that the combination of model architecture, training approach, loss function, and the explicit modeling of inverse relations is crucial for a model’s performance and is not only determined by its architecture. We provide evidence that several architectures can obtain results competitive to the state of the art when configured carefully. We have made all code, experimental configurations, results, and analyses available at https://github.com/pykeen/pykeen and https://github.com/pykeen/benchmarking. [ABSTRACT FROM AUTHOR]