Search

This paper proposes a new approach to above- $f_{max}$ power detection, using harmonic injection locking of a cross-coupled oscillator and the resulting change in oscillation amplitude. The paper starts with the development of a theoretical framework for this receiver. Two previous methodologies are combined: analyzing an injection-locked oscillator as an active device in a positive feedback loop with a frequency selective network; and the more recently proposed way of modeling non-linearities by using inter-harmonic translation coefficients. Using this framework, a compact equation for the expected voltage response of the receiver is derived. Finally, the design of a receiver consisting of a 200 GHz cross-coupled oscillator with a 600 GHz folded dipole antenna as its tank inductor is discussed. A Noise Equivalent Power (NEP) of 2.3 pW/ $\sqrt {\text {Hz}}$ is achieved with the proposed receiver. [ABSTRACT FROM AUTHOR]

In this paper, we describe a design of a mixed-signal circuit for an binary neuron (a.k.a perceptron, threshold logic gate) and a methodology for automatically embedding such cells in ASICs. The binary neuron, referred to as an FTL (flash threshold logic) uses floating gate or flash transistors whose threshold voltages serve as a proxy for the weights of the neuron. Algorithms for mapping the weights to the flash transistor threshold voltages are presented. The threshold voltages are determined to maximize both the robustness of the cell and its speed. The performance, power, and area of a single FTL cell are shown to be significantly smaller (79.4%), consume less power (61.6%), and operate faster (40.3%) compared to conventional CMOS logic equivalents. Also included are the architecture and the algorithms to program the flash devices of an FTL. The FTL cells are implemented as standard cells, and are designed to allow commercial synthesis and P&R tools to automatically use them in synthesis of ASICs. Substantial reductions in area and power without sacrificing performance are demonstrated on several ASIC benchmarks by the automatic embedding of FTL cells. The paper also demonstrates how FTL cells can be used for fixing timing errors after fabrication [ABSTRACT FROM AUTHOR]

This paper presents a mixed-signal SRAM-based in-memory computing (IMC) macro for processing binarized neural networks. The IMC macro consists of $128\times 128$ (16K) SRAM-based bitcells. Each bitcell consists of a standard 6T SRAM bitcell, an XNOR-based binary multiplier, and a pseudo-differential voltage-mode driver (i.e., an accumulator unit). Multiply-and-accumulate (MAC) operations between 64 pairs of inputs and weights (stored in the first 64 SRAM bitcells) are performed in 128 rows of the macro, all in parallel. A weight-stationary architecture, which minimizes off-chip memory accesses, effectively reduces energy-hungry data communications. A row-by-row analog-to-digital converter (ADC) based on 32 replica bitcells and a sense amplifier reduces the ADC area overhead and compensates for nonlinearity and variation. The ADC converts the MAC result from each row to an N-bit digital output taking 2N-1 cycles per conversion by sweeping the reference level of 32 replica bitcells. The remaining 32 replica bitcells in the row are utilized for offset calibration. In addition, this paper presents a pseudo-differential voltage-mode accumulator to address issues in the current-mode or single-ended voltage-mode accumulator. A test chip including a 16Kbit SRAM IMC bitcell array is fabricated using a 65nm CMOS technology. The measured energy- and area-efficiency is 741-87TOPS/W with 1-5bit ADC at 0.5V supply and 3.97TOPS/mm2, respectively. [ABSTRACT FROM AUTHOR]

SRAM based computing-in-memory (SRAM-CIM) techniques have been widely studied for neural networks (NNs) to solve the “Von Neumann bottleneck”. However, as the scale of the NN model increasingly expands, the weight cannot be fully stored on-chip owing to the big device size (limited capacity) of SRAM. In this case, the NN weight data have to be frequently loaded from external memories, such as DRAM and Flash memory, which results in high energy consumption and low efficiency. In this paper, we propose a hybrid-device computing-in-memory (HD-CIM) architecture based on SRAM and MRAM (magnetic random-access memory). In our HD-CIM, the NN weight data are stored in on-chip MRAM and are loaded into SRAM-CIM core, significantly reducing energy and latency. Besides, in order to improve the data transfer efficiency between MRAM and SRAM, a high-speed pipelined MRAM readout structure is proposed to reduce the BL charging time. Our results show that the NN weight data loading energy in our design is only 0.242 pJ/bit, which is 289 $\times $ less in comparison with that from off-chip DRAM. Moreover, the energy breakdown and efficiency are analyzed based on different NN models, such as VGG19, ResNet18 and MobileNetV1. Our design can improve $\mathbf {58\times \,\,to\,\,124\times }$ energy efficiency. [ABSTRACT FROM AUTHOR]

The performance of nanoscale semiconductor technologies has become susceptible to high temperatures and aging phenomena. While guard-bands have conventionally been used to combat degradation-induced timing violations, approximations have recently been leveraged to compensate for degradations in lieu of adding timing guard-bands, without a loss in performance. However, only simple approximation techniques such as truncation have been considered in prior work. In this paper, a wide range of approximate arithmetic circuits including adders and multipliers using various sophisticated approximation techniques are investigated to cope with aging- and temperature-induced degradations. To this end, approximate circuits are first characterized for their delay increase under degradations. With this, we then determine the approximation level required to compensate for guard-bands under different degradations. Degradation-aware logic synthesis results show that the simple use of truncated arithmetic circuits leads to a higher quality loss compared to using other approximate circuits. However, a truncated multiplier has the lowest error distance towards a reliable operation in 10 years. The approximate multipliers with configurable error recovery are most suitable when the level of degradation is higher, e.g., at a temperature of 70 °C. The characterization of degradation at the circuit level is then used for design exploration at the architecture level without the need for further gate-level simulations. For three different image processing applications, experimental results show that guard-bands can be mitigated while maintaining an output result with a high visual quality. [ABSTRACT FROM AUTHOR]

This paper presents a tunable new deadtime control circuit providing an optimal delay for power converter optimization. Our method can reduce the deadtime loss while improving the efficiency and power density of a given power converter. The circuit presents a reconfigurable delay element to generate a wide range of deadtime for different power conversion applications with varying loads and input voltages. The optimal deadtime equation for buck converters is derived, and its dependency on the input voltage and load is discussed. Experimental results show that the presented circuit can provide a wide range of deadtime delays, ranging from 9.2 ns to 1000 ns. The power consumption of the presented circuit is measured for different capacitive loads ($\text{C}_{\mathrm {L}}$) and operating frequencies (${f}_{\mathrm {s}}$). The circuit consumed a power between 610 $\mu \text{W}$ and $850~\mu \text{W}$ across the measured deadtime ranges while $\text{C}_{\mathrm {L}} =12$ pF, $\text{V}_{\mathrm {dd}} =3.3$ V, and $\text{f}_{\mathrm {s}}=200$ kHz. The proposed deadtime generator can operate up to 18 MHz when the minimum deadtime of 9.2 ns is selected. The presented circuit occupies an area of $150\mu $ m $\times 260\mu \text{m}$. The fabricated chip is connected to a buck converter to validate the operation of the proposed circuit. The efficiency of a typical buck converter with minimum $\text{T}_{\mathrm {DLH}}$ and optimal $\text{T}_{\mathrm {DHL}}$ at $\text{I}_{\mathrm {Load}} =25$ mA is improved by 12% compared to a converter with a fixed deadtime of $\text{T}_{\mathrm {DLH}} =\,\,\text{T}_{\mathrm {DHL}} =12$ ns. [ABSTRACT FROM AUTHOR]

This paper presents a low-power constant subthreshold transconductance reference circuit that produces a constant transconductance by subtracting the output currents of two independent transconductance references. By taking the difference between the output currents of the two independent transconductance references, process, voltage and temperature variations are reduced by minimizing the effects of channel length modulation and drain-induced barrier lowering without relying on feedback to regulate the drain voltage. The proposed reference, fabricated in TSMC’s 130 nm process and testing with off-chip temperature-insensitive resistors, can provide a constant transconductance over a temperature range of −30 to 120°C, and a supply voltage range of 0.5 to 1.7 V. The experimental result of the proposed transconductance reference shows an average variation of ±0.8% over temperature for the entire operating voltage range and an average variation of ±1.97% over voltage for the entire operating temperature range. Through the subtraction, the proposed circuit also shows less variation across process corners compared to the conventional constant transconductance reference. The proposed constant transconductance reference exhibits the highest power efficiency (transconductance over power consumption) amongst the reported constant transconductance references. At 0.5 V, the proposed transconductance reference produces a transconductance of 21.46 $\mu \text{S}$ , while consuming 1.95 $\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This paper proposes CMOS synapse and neuron for use in spiking neural networks to perform cognitive functions in a bio-inspired manner. The proposed synapse can trace the eligibility of the timing relationship between pre- and post-synaptic spikes, supporting a bio-plausible local learning rule called the spike timing-dependent plasticity (STDP) in an energy- and area-efficient manner. The proposed neuron can support neural functions such as synaptic current integration, threshold-based firing, neuronal leaking, membrane potential resetting, and adjustable refractory period with improved energy and area efficiency. The STDP curve shape of the synapse and the firing rate of the neuron can be adjusted as desired. Their variability due to process, voltage, and temperature (PVT) variations can also be minimized. The proposed CMOS neuron and synapse circuits were designed in a 28-nm CMOS process. The performance evaluation results indicate that the proposed synapse reduces energy consumption and area by up to 94% and 43% compared to conventional CMOS synapses. They also indicate that the proposed neuron achieves energy and area reductions of 37% and 23%, respectively, compared to conventional CMOS neurons. An associative neural network composed of the proposed neuron and synapse was designed to verify that they together work well for performing a cognitive function of associative learning and inferencing. [ABSTRACT FROM AUTHOR]

In this paper, we present an integrator-differentiator transimpedance amplifier (I-D-TIA) with a dc compensation, which incorporates widely tunable multi-element pseudo-resistors (MEPRs) in its dc servo loop and ac signal path. The implemented MEPR in the dc path is continuously tunable from $460 \,\mathrm {k\Omega }$ to $300 \,\mathrm {G\Omega }$ allowing the TIA to process dc currents with a dynamic range of more than $100 \,\mathrm {dB}$. The MEPR in the differentiator ac signal path provides a tunable resistance between $0.3 \,\mathrm {M\Omega }$ and $100 \,\mathrm {M\Omega }$ , resulting in an overall ac transimpedance between $3 \,\mathrm {M\Omega }$ and $1 \,\mathrm {G\Omega }$. For the lowest ac transimpedance, a bandwidth of $10 \,\mathrm {MHz}$ is achieved. The TIA provides a minimum input-referred current noise density of $1.6\,\mathrm {fA}/\mathrm {\sqrt {Hz}}$. The implemented MEPR has been optimized regarding its high-frequency noise by minimizing its parasitic capacitances. The MEPR shows an inherent shot noise suppression such that its noise stays close to the theoretical thermal noise limit and significantly below the theoretical shot noise limit, even for large dc currents. By using a sub-VSS supply for the MEPR, the asymmetry in its output characteristic is greatly reduced, leading to a linear signal swing of $1.5\,\mathrm {V_{pp}}$ with a THD below $1 \mathrm {\%}$ on a $1.8-\mathrm {V}$ supply. Thanks to this high linearity, large bandwidth, and high dc current dynamic range, the proposed TIA can be used in a wide variety of applications from high-sensitivity, low-bandwidth lock-in detection to transient current sensing with sub-microsecond timing resolutions. [ABSTRACT FROM AUTHOR]

The robustness of current and voltage references to process, voltage and temperature (PVT) variations is paramount to the operation of integrated circuits in real-world conditions. However, while recent voltage references can meet most of these requirements with a handful of transistors, current references remain rather complex, requiring significant design time and silicon area. In this paper, we present a family of simple current references consisting of a two-transistor (2T) ultra-low-power voltage reference, buffered onto a voltage-to-current converter by a single transistor. Two topologies are fabricated in a 0.18- $\mu \text{m}$ partially-depleted silicon-on-insulator (SOI) technology and measured over 10 dies. First, a 7T nA-range proportional-to-absolute-temperature (PTAT) reference intended for constant- $g_{m}$ biasing of subthreshold operational amplifiers demonstrates a 0.096-nA current with a line sensitivity (LS) of 1.48 %/V, a temperature coefficient (TC) of 0.75 %/°C, and a variability $(\sigma /\mu)$ of 1.66 %. Then, two 4T+1R $\mu \text{A}$ -range constant-with-temperature (CWT) references with (resp. without) TC calibration exhibit a 1.09- $\mu \text{A}$ (resp. 0.99- $\mu \text{A}$) current with a 0.21-%/V (resp. 0.20-%/V) LS, a 38-ppm/°C (resp. 290-ppm/°C) TC, and a 0.87-% (resp. 0.65-%) $(\sigma /\mu)$. In addition, portability to common scaled CMOS technologies, such as 65-nm bulk and 28-nm fully-depleted SOI, is discussed and validated through post-layout simulations. [ABSTRACT FROM AUTHOR]

This paper presents a rigorous transfer function analysis of the power supply rejection ratio (PSRR) of low-dropout (LDO) regulators and the LDO with the feed-forward ripple cancellation (FFRC) scheme. Four main noise sources of conventional LDOs are first clarified. An efficient and accurate model is proposed to facilitate the analysis, and the transfer function, along with the poles and zeros, is derived based on the simplified model. Software simulation results and numerical plots are both demonstrated and compared to verify the analytical results, with respect to two specific design examples. The widely-used FFRC scheme for PSRR enhancement is also reinvestigated based on the proposed model. With the inclusion of the FFRC circuit, the new transfer function with new poles and zeros is presented. The working principles of the FFRC scheme are illustrated and the optimal FFRC case is clarified. The proposed model and the derived transfer function match well with the simulation results and the measurement results in prior works. The proposed model and the analytical results serve as the theoretical foundation of the design of high-PSRR LDOs. The recommended simulation methodology could be helpful during the circuit design phase. [ABSTRACT FROM AUTHOR]

Approximate computing (AC) has been considered as a promising paradigm to improve the energy-efficiency of computing hardware for error-tolerant applications, with negligible quality degradation to the output. Dividers frequently limit the performance of a computing system; however, they have not received as much attention as multipliers and adders in AC. In this paper, an energy-efficient and high-performance approximate divider is proposed based on logarithmic conversion and piecewise constant approximation. In this design, the range for the conversion between binary and logarithmic numbers is first expanded from $\mathbf {[{0,1}]}$ to $\mathbf {[-0.5,1]}$. A heuristic search algorithm is then devised to find the most accurate constant set to approximate the reciprocal of the divisor, by minimizing a statistical error. The hardware implementation is presented for both floating-point (FP) and integer dividers. With a high configurability, the proposed divider results in a mean relative error distance (MRED) from 2.78% to 0.046%, indicating a high accuracy among state-of-the-art approximate dividers. Compared to the half-precision FP divider, the proposed divider with a MRED of 0.74% can achieve nearly $\mathbf {90\times }$ improvement in PDP. Moreover, compared to state-of-the-art approximate dividers, the proposed design is in the Pareto Frontier in terms of power delay product (PDP) and MRED. The three image processing application results demonstrate that the proposed divider can result in the highest peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) even with truncation. [ABSTRACT FROM AUTHOR]

Many energy harvesters (EH) deliver an ac voltage and require a rectifier as a consequence. This paper describes how the rectifier affects the power flow transmitted from the EH to the load and how to tackle the different voltage amplitudes. This study has been performed using analytical calculations, numerical modeling and experiments. To reach the maximum power transfer, conventional methods apply a fraction of the open-circuit voltage delivered by the EH. In contrast, this study points out that the optimum operating point must be shifted by a quantity depending on the rectifier characteristics. This difference is particularly important when the EH provides relatively small ac voltages. Two classic rectifiers are covered: a diode bridge (DB) and a MOSFET bridge (MB). An approximated solution of the analytical model is proposed and allows to optimize the EH without cumbersome numerical computations. Experiments are conducted first with a function generator and then with an electromagnetic EH prototype. The outcomes from the analytical model and the numerical model are in good agreement with the experimental results. A new regulation method is proposed for maximizing the power transferred from the ac EH to the load. [ABSTRACT FROM AUTHOR]

This paper presents two high-efficiency charge pumps (CPs) by utilizing the gate voltage boosting technique (GVBT). Unlike traditional bulk-CMOS and all-NMOS CPs, an input bias voltage is independently applied to the gate terminal, and it improves the current driving capability without the need of large pumping capacitors or high-frequency clocks. Meanwhile, the GVBT decouples the state of transistors from the clocks connected to the pumping capacitor, and it can eliminate the reversion loss in both main and auxiliary circuits. Fabricated in a 0.18- $\mu \text{m}$ standard CMOS technology, the single-stage all-NMOS CP achieved a maximum output voltage of 6.589 V and a peak power efficiency of 80.08%. We also implemented the bulk-CMOS CP with GBVT for comparison, the single-stage all-NMOS CP achieved $\sim 1.24\times $ more output voltage than the bulk-CMOS CP under a load current of 1.5 mA. The voltage errors of the all-NMOS CP between the analytical and the measured results are less than 7%. [ABSTRACT FROM AUTHOR]

In this paper, an analysis method is presented to mathematically characterize the harmonic current generated by the voltage at fundamental or harmonic frequency in the transistor of a high-frequency harmonic oscillator. Using this analysis method, the relationship between the second harmonic voltages and the fourth harmonic drain current in the transistor is investigated, and the requirement on the second harmonic voltages for fourth harmonic boosting is found. Moreover, an approach of modeling the voltage-current relationship in the transistor of a high-frequency harmonic oscillator at harmonic frequency as an equivalent linear relationship is proposed. This modeling method facilitates the design of the second harmonic embedding network around the transistor, thus helping to propose a harmonic oscillator topology in which the requirement on the second harmonic voltages for fourth harmonic boosting is fulfilled. Using the proposed fourth harmonic boosting technique, a 0.6-THz radiator array is designed in 40-nm bulk CMOS. In measurement, the 0.68- $\text {mm}^{2}$ radiator array achieves a radiated power of 0 dBm and a DC-to-THz efficiency of 0.08% at 586.7 GHz under a 0.9-V supply voltage. [ABSTRACT FROM AUTHOR]

This paper presents the analysis and design of an oscillator-doubler architecture which is used to generate THz signals. In this architecture, the doubler obtains the optimum fundamental-frequency load impedance for second harmonic generation without causing problems related to instability. The oscillator creates voltages close to the optimum voltage condition, which leads to maximum power being delivered to the doubler connected to the oscillator tank. Compared to a signal generator composed of an oscillator and a conventional doubler with short-circuit load at the fundamental frequency, the proposed circuit has higher output power and DC-to-THz conversion efficiency. Based on this architecture, a 0.3-THz signal generator is designed in 40-nm CMOS. In this 0.3-THz signal generator, an inductor-sharing configuration is proposed to increase the transistor size in the cross-coupled oscillator, thus increasing the power density of the signal generator. Besides, the impact of the doubler fundamental-frequency load impedance on the conversion gain of the doubler is introduced. Also, a method of suppressing the unwanted mode in the cross-coupled oscillator is proposed. The output of this circuit is radiated through on-chip antennas. The measured radiated power and the DC-to-THz efficiency of the chip are -3.8 dBm and 0.37%, respectively, with an output frequency tuning range of 4.8%. [ABSTRACT FROM AUTHOR]

In this paper, a highly efficient gallium nitride (GaN) monolithic microwave integrated circuit (MMIC) Doherty power amplifier (DPA) from 4.6 to 5.5 GHz with the consideration of the influence of the peaking transistor’s output capacitor $(C_{\mathrm {out}}$) operated in Class-C state is presented. Based on the load-modulation behavior analysis, the effect of the $C_{\mathrm {out}}$ of the peaking transistor on the performance of the wideband DPA has been theoretically analyzed for the first time by directly evaluating the value of the peaking transistor’s $C_{\mathrm {out}}$. A hybrid matching technique has been proposed to ensure that the DPA can realize a proper load-modulation with high back-off efficiency in a wide bandwidth. In this method, the peaking transistor is matched using a simple T-shape band-pass type network with the $C_{\mathrm {out}}$ of the peaking transistor in Class-C operation state compensated properly, while the carrier transistor is matched using a 2-point matching method. For verification, a wideband GaN MMIC DPA with the frequency range of 4.6 to 5.5 GHz was designed using a 0.25- $\mu {\mathrm{ m}}$ GaN on silicon-carbon high-electron-mobility transistor process. Experimental results show that the fabricated DPA can realize the output power of 41.1-41.6 dBm and the drain efficiency (DE) of 57.6%-63.3% at saturation in the whole frequency band. The measured DE at 6-dB power back-off is 51%-56.4%. Good linearity with high average efficiency performance was obtained when excited by a 160-MHz modulated signal after linearization. [ABSTRACT FROM AUTHOR]

Back-bias control is a new degree of freedom brought by fully-depleted silicon-on-insulator (FDSOI) CMOS technologies, which can be used to control the oscillation frequency of voltage-controlled ring oscillators (VCROs). The resulting VCRO architecture is called a back-bias-controlled oscillator (BBCO). This paper compares it with the conventional current-starved ring oscillator (CSRO) topology in terms of power consumption and phase noise figure-of-merit (FoM), while taking practical design constraints of process-voltage-temperature (PVT) robustness and frequency tuning range into account. The proposed comprehensive analysis takes advantage of relevant and compact analytical models, as well as extensive pre-layout simulation results. The comparison is made at four different target oscillation frequencies, which are representative of frequency synthesis for WiFi/Bluetooth/LPWAN wireless communications and of clock generation for smartphone/Internet-of-Things processors: 300 MHz, 868 MHz, 2.45 GHz, and 5.18 GHz. In 28-nm FDSOI technology, the results demonstrate that BBCOs can intrinsically reach 1.69 to $4.63\times $ lower minimum power consumption and slightly better FoM values than CSROs. [ABSTRACT FROM AUTHOR]

With the advancement of technology, the size of transistors and the distance between them are reducing rapidly. Therefore, the critical charge of sensitive nodes is reducing, making SRAM cells, used for aerospace applications, more vulnerable to soft-error. If a radiation particle strikes a sensitive node of the standard 6T SRAM cell, the stored data in the cell are flipped, causing a single-event upset (SEU). Therefore, in this paper, a Soft-Error-Aware Read-Stability-Enhanced Low-Power 12T (SARP12T) SRAM cell is proposed to mitigate SEUs. To analyze the relative performance of SARP12T, it is compared with other recently published soft-error-aware SRAM cells, QUCCE12T, QUATRO12T, RHD12T, RHPD12T and RSP14T. All the sensitive nodes of SARP12T can regain their data even if the node values are flipped due to a radiation strike. Furthermore, SARP12T can recover from the effect of single-event multi-node upsets (SEMNUs) induced at its storage node-pair. Along with these advantages, the proposed cell exhibits the highest read stability, as the ‘0’-storing storage node, which is directly accessed by the bitline during read operation, can recover from any upset. Furthermore, SARP12T consumes the least hold power. SARP12T also exhibits higher write ability and shorter write delay than most of the comparison cells. All these improvements in the proposed cell are obtained by exhibiting only a slightly longer read delay and consuming slightly higher read and write energy. [ABSTRACT FROM AUTHOR]

This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. In this paper, we propose a memory architecture named crossed-AND (C-AND), in which each storage cell consists of a single ferroelectric transistor. The write operation is performed using different write schemes and different absolute voltages, to account for the asymmetric switching voltages of the FeFET. It enables writing an entire wordline in two consecutive cycles and prevents current and power through the channel of the transistor. During the read operation, the current and power are mostly sensed at a single selected device in each column. The read scheme additionally enables reading an entire word without read errors, even along long bitlines. Our Simulations demonstrate that, in comparison to the previously proposed AND architecture, the C-AND architecture diminishes read errors, reduces write disturbs, enables the usage of longer bitlines, and saves up to 2.92X in memory cell area. [ABSTRACT FROM AUTHOR]

This paper presents a discrete-time low-noise amplifier for miniaturized sensor nodes. Such amplifier achieves a noise efficiency factor of 1.01 and a power efficiency factor of 1.63, improving the noise efficiency of an analog front-end. The proposed preamplifier employs discrete-time parametric amplification by modulating the capacitance of a MOS varactor. The sampling noise is minimized by adopting a high oversampling ratio of the input voltage, leading to an input-referred noise of 520 nVrms in a 1 kHz bandwidth. Also, the power consumption is reduced by using a 34-phase stepwise charging technique. The multiphase soft-charging technique is implemented using multiple time-interleaved cells and allows to significantly reduce the current consumption without introducing any significant penalty in terms of additional noise or area occupation. A two-stage parametric amplifier is introduced to provide higher gain, and suppress the noise contribution of the following amplifier chain. The proposed two-stage complementary preamplifier is followed by a third continuous-time stage, that employs a current-reuse inverter-based architecture. The contribution to the total noise efficiency factor of such amplifier is attenuated by the gain of the previous two-stage parametric preamplifier. As a result, the third stage provides gain programmability, while degrading the NEF of the entire chain by less than 10%. [ABSTRACT FROM AUTHOR]

This paper presents a monolithically integrated E-band amplifier multiplier chain (AMC) developed in 130 nm SiGe BiCMOS process. This E-band AMC is composed of a 25 GHz 1:1 power divider, two 25 GHz driver amplifiers (DA1,2), a 75 GHz passive frequency tripler, and a 75 GHz power amplifier (PA). By applying a bypass tuning capacitor based power enhancing technique in the single-ended DA and PA, the output power and power-added-efficiency (PAE) of the AMC have been effectively improved. Benefiting from the proposed passive tripler core with second harmonic suppression function, and the impedance matching network with frequency selection characteristics, the AMC presents better harmonic suppression performance compared with the conventional topology. The bias circuits with temperature compensation are applied to the DA and PA to ensure the performance of the AMC when the temperature changes. The AMC has a measured output power exceeding 0 dBm in the entire E-band frequency range with a peak output power of 10.9 dBm at 77 GHz, and exhibits a record PAE of 8.25 %. Within the 3 dB operating frequency range from 69 to 87 GHz, the rejection of fundamental and second harmonics are better than 33.5 dB. The AMC can work properly between −40°C and 125 °C with the proposed temperature compensation bias circuits. [ABSTRACT FROM AUTHOR]

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 $\text{G}\Omega $ and 700 $\text{G}\Omega $ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz. [ABSTRACT FROM AUTHOR]

In this paper we propose a novel approach called Multi-Folded (MF) MOS Current Mode Logic (MCML) which can be applied to a generic MCML gate (i.e., with a fan-in higher than two). The idea is implemented by alternating NMOS and PMOS differential pairs and properly introducing current mirrors between the adjacent levels of logic. The proposed approach allows a minimum power supply equal to the one of a MCML inverter and we show analytically the advantages in terms of speed and power consumption against the conventional implementation. The approach has been validated with post-layout simulations considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. In particular, OR/NOR gates with 3, 4, and 5 inputs implemented both with the conventional 2-inputs MCML gates implementation (Fin2) and the proposed MF MCML have been compared. Results show a reduction in the power consumption of the MF MCML equal to 3/4, 2/3 and 5/8 for the OR3, OR4 and OR5 logic functions respectively. Moreover, in terms of speed the Fin2 implementation has a delay at least 1.4 worst than the MF MCML, but is generally 1.7 worst than the proposed MF MCML gate. In this paper we have presented a novel approach which allows to implement MCML gates with a fan-in higher than 2 while keeping the minimum supply voltage as low as the one of a conventional MCML inverter. The proposed methodology, named Multi Folded MCML, born out by a generalization of the Folded MCML previously proposed by authors. The approach has been compared against the conventional Fin2 implementation (suited to implement arbitrarily logic function with a low power supply) both in terms of power consumption and propagation delay. The results have clearly demonstrated the advantages provided by the MF MCML. In particular, OR/NOR gates with 3-, 4-, and 5-inputs have been compared considering a commercial 28nm FD-SOI CMOS technology and a supply voltage as low as 0.6V. Post layout simulation results have shown that the MF gates outperform the conventional implementations in terms of propagation delay for all the considered logic functions. In particular, the propagation delay of the Fin2 implementation has been shown to be at least 1.4 times higher than the one of the MF MCML implementation and even 2 times higher for other logic functions. The power consumption of the MF gates has been shown to be 3/4, 2/3 and 5/8 than the one of the Fin2 implementations for the OR3, OR4 and OR5 logic functions respectively. Hence, the only drawback of the propose techniques seems due to a more complex design procedure. [ABSTRACT FROM AUTHOR]

The common mode (CM) current in differential circuits generates CM noise which radiates in the environment and causes electromagnetic interference (EMI) with electronic devices in proximity. This noise is generated due to imbalance in the charging and discharging paths of the driver circuit and asymmetric equalization. A systematic study of how asymmetric equalizer increase the CM noise is still lacking. Few active on-chip solutions are proposed for wireline transmitters up to 20-Gbps speed. However, these solution does not suppress CM noise by the equalizer and they could not support four-level pulse amplitude modulation (PAM-4) optical transmitters. This paper analyzes two potential sources of EMI-related CM noise, the common mode logic (CML) driver and feed forward equalization (FFE) circuit, and presents a novel on-chip active circuit technique for automatic CM noise cancellation in high-speed PAM-4 transmitter. This solution provides the benefits of small size and low cost by eliminating the need for discrete components to suppress EMI. The post-layout simulation demonstrates that the CM noise cancellation circuit (CMNC) efficiently mitigate the EMI by suppressing the CM noise up to 90% and consumes 5 mW, with core area of $17 \mu m \times 9 \mu m$. [ABSTRACT FROM AUTHOR]

The reduction of the nominal supply voltage of CMOS technologies with scaling comes with the decrease of the maximum tolerable voltage of the devices. This poses challenges in implementing circuit blocks that are compliant with standardized communication protocols or deal with off-chip signals in voltage domains larger than the nominal supply (e.g., 1.8 V, 3.3 V, 5 V). Design techniques such as cascoding, voltage shifting and adaptive biasing are effective at removing the need for customized voltage resistant input/output (I/O) devices since they prevent intolerable voltage drops. However, at the input of multiple-channel blocks, the design of switches of multiplexers results critical as the input and the output nodes can assume values beyond the signal range, causing harmful biasing configurations. This paper presents the architecture of a switch for input channel multiplexers able to handle signals up to twice the nominal supply voltage of the employed devices. Its effectiveness has been proved by implementing a 1.6V switch with the core MOS transistors of the 28nm CMOS technology with 0.96V nominal supply voltage. The comparison with a benchmark switch based on 1.8V I/O devices showed that both a larger area (slightly more than twice) and static current consumption ($40\mu \text{A}$) are required. [ABSTRACT FROM AUTHOR]

Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard non-rad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flip-flop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP’s 130nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from ($32.4\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$) to ($62.5\, \frac { {\mathrm { \text {M} \text {eV} }}\cdot {\mathrm { \text {c} \text {m} }}^{2}}{ {\mathrm { \text {m} \text {g} }}}$), depending on the variant. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junction (MTJ) with non-volatility, and near-zero leakage power features are believed to be the most prominent candidates for CMOS substitution. Logic-in-memory reduces the memory wall challenge and takes advantage of these features, but still has the challenge of writing to a magnetic device with regard to power consumption and device failure. Considering these challenges, we propose new designs in the approximate computing approach for magnetic device-based primitives. This paper proposes several power- and/or delay-efficient configurable Logic-in-Memory for Imprecise Tolerant Applications (LIMITA) based on spin transfer torque (STT) and STT-assisted voltage control magnetic anisotropy (VCMA) magnetic devices. Image processing is one of the most widely used imprecise tolerant applications with a high computational volume. Therefore, we map LIMITA with several approximation boundaries in Sobel, Sharpening, and Smoothing algorithms. To evaluate LIMITA at circuit and application levels, we did extensive simulations in HSPICE and MATLAB, respectively. Compared to the state-of-the-art works, the exact design of LIMITA improves the number of transistors in the logic tree up to 66% with 12% power overhead due to its configurability feature. In addition, in comparison with approximate primitives, LIMITA- $\text{F}_{\mathrm {i}}$ improves delay, power consumption, and the number of transistors by $4.5\times$ , $71.5\times$ , and $2\times$ respectively. [ABSTRACT FROM AUTHOR]

In this paper, we revisit Boole’s expansion theorem to propose a new synthesis method for implication logic circuits based on memristors. By rewriting the sum-of-products form of Boole’s expansion theorem in terms that are best suited for the implication logic, we develop a generalized rule to derive the sequence of operations needed to realize any logic function written in the classical AND-OR form. The proposed method leverages on multi-input operation, minimizing both the number of steps required to compute a given Boolean function and the number of memristors involved. Moreover, it allows using well-established methods of logic circuit optimization like binary decision diagrams, Karnaugh maps, and heuristic algorithms, that are already implemented in commercial CAD software. The proposed method allows a fair comparison between the performance of CMOS and implication logic implementations of the same logic function under the same degree of optimization, and is shown to outperform existing approaches. Possible device-circuit co-design strategies to optimize circuit performance are finally discussed. [ABSTRACT FROM AUTHOR]

Memristor crossbar arrays are used in a wide range of in-memory and neuromorphic computing applications. However, memristor devices suffer from non-idealities that result in the variability of conductive states, making programming them to a desired analog conductance value extremely difficult as the device ages. In theory, memristors can be a nonlinear programmable analog resistor with memory properties that can take infinite resistive states. In practice, such memristors are hard to make, and in a crossbar, it is confined to a limited set of stable conductance values. The number of conductance levels available for a node in the crossbar is defined as the crossbar’s resolution. This paper presents a technique to improve the resolution by building a super-resolution memristor crossbar with nodes having multiple memristors to generate $r$ -simplicial sequence of unique conductance values. The wider the range and number of conductance values, the higher the crossbar’s resolution. This is particularly useful in building analog neural network (ANN) layers, which are proven to be one of the go-to approaches for forming a neural network layer in implementing neuromorphic computations. [ABSTRACT FROM AUTHOR]

As technology scaling down, the sensitivity of SRAM cells to radiation-induced Single Event Upsets (SEUs) increases, and Single Event Multiple Node Upsets (SEMNUs) due to charge sharing has also become one of the major concerns in memory cell designs. In this paper, a high-reliability radiation hardened memory cell (RH-14T) is proposed to mitigate SEMNUs. SPICE simulations and 3D technology computer aided design mixed-mode simulations were performed to verify the high robustness of the RH-14T cell to SEUs. Compared with previous radiation hardened memory cells, the proposed RH-14T cell has similar read access time, smaller write access time, and the read access time and write access time are less sensitive to process variations. The Read Static Noise Margin (RSNM) and Write Margin (WM) of the RH-14T cell are larger than those of the unhardened conventional 6T SRAM cell. The improvement of reliability is often a trade-off with area, power consumption and performance. In order to achieve high reliability, the RH-14T cell employs more transistors, so it has 1.5 times the power consumption overhead of 6T and a larger area penalty. [ABSTRACT FROM AUTHOR]

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems. [ABSTRACT FROM AUTHOR]

In this paper, passive-less fully-digital operational transconductance amplifiers (DIGOTA) for energy- and area-constrained systems are modeled and analyzed from a design viewpoint. The digital behavior of DIGOTAs is modeled as an equivalent small-signal differential-mode circuit with zero bias current, and a common-mode feedback loop operating as a self-oscillating threshold sampler. Such continuous-time equivalent circuits are used to derive an explicit model of the main performance parameters that are generally adopted to characterize OTAs. This provides an insight into circuit operation and allows to derive practical guidelines to achieve a given design target. Among the others, an explicit model is derived for the DC gain, the frequency response, the gain-bandwidth product, the input-referred noise, and the input offset voltage. The models are validated via direct comparison with multi-die measurement results in CMOS 180 nm. From an application viewpoint, the voltage (power) reduction down to 0.25 V (sub-nW) uniquely enable direct harvesting (e.g., with solar cells), suppressing any intermediate DC-DC conversion stage. This further enhances the area efficiency advantage of DIGOTA stemming from its fully-digital nature, making it well suited for cost-sensitive and purely-harvested systems. [ABSTRACT FROM AUTHOR]

Silicon-based terahertz (THz) integrated circuits (ICs) have made rapid progress over the past decade. The demonstrated basic component performance, as well as the maturity of design tools and methodologies, have made it possible to build high-complexity THz integrated systems. Such implementations are undoubtedly highly attractive due to their low cost and high integration capability; however, their unique characteristics, both advantageous and disadvantageous, also call for research investigations into unconventional systematic architectures and novel THz applications. In this paper, we review the current status and future trend of silicon-based THz ICs, with the focus on state-of-the-art THz microsystems for emerging sensing and communication applications in the last few years, such as high-resolution imaging, high medium/long-term stability time keeping, high-speed wireline/wireless communications, and miniaturization of RF tags, as well as THz packaging technologies. [ABSTRACT FROM AUTHOR]

This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical sensing transistors. We simulated and fabricated the proposed DIBBSA architecture with various operational modes in 65-nm CMOS technology to analyze body biasing’s effectiveness in mitigating the offset. The standard deviation of offset (σOS) was measured over 5120 SAs in 10 ICs. The iso-gate area reduction in σOS for the proposed DIBBSA-FL and DIBBSA-PD modes resulted in 68.1% and 61.9% compared to conventional Current Latch SA (CLSA) and 24.1% and 18.1% compared to Voltage Latch SA (VLSA) at 0.4 V supply and 25 °C, respectively. Carried out measurements on 512 SAs in an IC show the minimum required differential input voltage across the temperature range of 0 °C to 75 °C at 0.4 V is achieved to be 48% lower compared to CLSA and 28% lower compared to VLSA by both the DIBBSA-FL and DIBBSA-PD modes. [ABSTRACT FROM AUTHOR]

This paper presents a charge-domain in-memory computing (IMC) macro for precision-scalable deep neural network accelerators. The proposed Dual-SRAM cell structure with coupling capacitors enables charge-domain multiply and accumulate (MAC) operation with variable-precision signed weights. Unlike prior charge-domain IMC macros that only support binary neural networks or digitally compute weighted sums for MAC operation with multi-bit weights, the proposed macro implements analog weighted sums for energy-efficient bit-scalable MAC operations with a novel series-coupled merging scheme. A test chip with a 16-kb SRAM macro is fabricated in 28-nm FDSOI process, and the measured macro throughput is 125.2-876.5 GOPS for weight bit-precision varying from 2 to 8. The macro also achieves energy efficiency ranging from 18.4 TOPS/W for 8–b weight to 119.2 TOPS/W for 2-b weight. [ABSTRACT FROM AUTHOR]

This paper presents an innovative Through-Load element aimed at characterization applications at mm-wave frequencies. The proposed structure can behave as a Through connection or as a 50-Ω load depending on a DC control voltage. Among other potential applications, this system can be used to implement a transfer switch or an attenuator. A demonstrator was fabricated and measured in the STM 55-nm BiCMOS technology. Over a wide bandwidth, from 55 GHz up to 170 GHz, experimental measurements demonstrate a maximum 1.6-dB of insertion loss when behaving as a Through connection and a minimum 14-dB of insertion loss when behaving as a 50-Ω load. In both cases, the return loss is better than 10 dB. The insertion loss at 90 GHz is 0.6 dB for the Through connection and 20 dB for the 50-Ω load connection. [ABSTRACT FROM AUTHOR]

First, this paper proposes a double-node-upset (DNU)-completely-tolerant (DNUCT) latch, featuring quadruple cross-coupled dual-interlocked-storage-cells (DICEs) with a C-element. Due to the existence of sufficient feedback loops, the latch can achieve complete DNU toleration. Second, this paper proposes an improved DNUCT latch (referred to as the TNUCT latch) by inserting a redundant level of C-elements at the output stage to intercept node-upset errors accumulated in the upstream DICEs so as to completely tolerate any possible triple-node-upset (TNU). Simulation results demonstrate the robustness of the proposed latches. These innovative latches are also cost-effective due to the use of high-speed transmission paths, clock gating, and fewer transistors. Compared with the typical TNU hardened latch (TNUHL) design that can completely tolerate any TNU, the proposed TNUCT latch reduces the delay-power-area product by approximate 98%. The proposed latches have less or equivalent sensitivity to process, voltage, and temperature variation effects compared with reference latches. [ABSTRACT FROM AUTHOR]

To achieve improved speed of operation, a higher integration density and lower power dissipation, transistors are being scaled aggressively. This trend has reduced the critical charge of sensitive nodes. As a result, SRAM cells used in the high radiation environment of aerospace have become highly vulnerable to soft errors. In this paper, we propose a soft-error-aware 14T (SEA14T) SRAM cell for aerospace applications. The performance of the proposed cell is assessed by comparing it with other radiation-hardened SRAM cells like QUCCE12T, WE-QUATRO, RHM12T, RHD12T, RSP14T and RHBD14T. The proposed cell can fully recover from a single-event upset, of any strength and polarity, induced at all the sensitive nodes. Simulation results also show that SEA14T can fully recover from a multi-node upset induced at the internal node-pair. The proposed cell exhibits 1.06 ×/1.08 ×/1.36 × shorter read delay than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.03 ×/1.09 ×/1.12 ×/1.15 ×/1.17 × shorter write delay than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. It also shows 1.33 ×/1.6 ×/2.4 × higher read stability than QUCCE12T/ WE-QUATRO/ RHBD14T and 1.13 ×/1.32 ×/1.37 ×/1.42 ×/1.5 × higher write ability than RHM12T/ WE-QUATRO/ QUCCE12T/ RSP14T/ RHD12T. Furthermore, the proposed cell consumes 2.31 ×/2.42 ×/2.55 ×/3.04 × lower hold power than RHD12T/ RSP14T/ WE-QUATRO/ QUCCE12T @ VDD = 1 V. All these improvements are achieved at the cost of a slightly larger area overhead. [ABSTRACT FROM AUTHOR]

In this paper, a broadband receiver front end for 0.1 to 40 GHz application, fabricated using 0.15-μm GaAs E-mode pHEMT process, is reported. The receiver front end consists of a broadband low-noise amplifier (LNA) and a broadband mixer. To achieve low noise and significant bandwidth extension, a three-stage LNA, cascading one stage cascode amplifier with feedback and bandwidth extension techniques, to two stage cascode Darlington amplifiers with feedback, is proposed. The bandwidth extension principles of LNA are analyzed theoretically and verified experimentally. Measurement results show that the proposed LNA exhibits an average gain of 23.7 dB with ± 1.5-dB variation, a typical noise figure of 3.8 dB, maximum OP1dB of 8.7 dBm in the frequency range from 0.1 to 40 GHz. A symmetric distributed drain mixer (SDDM) is proposed to provide broad bandwidth while ensuring an IP1dB of up to 5.8 dBm. The design procedure of SDDM is presented in detail. Experimental results indicate that the SDDM features a less than 7-dB conversion loss, an IP1dB of up to 5.8 dBm with zero dc dissipation and better than 15-dB isolation of LO-to-RF and IF-to-RF ports from 0.1 to 40 GHz. Finally, the LNA and SDDM are integrated as a 0.1 to 40-GHz receiver front end. Measurements illustrate that the receiver front end shows good matching with better than 10-dB return loss at RF and LO ports, and larger than 15-dB conversion gain in 0.1 to 40-GHz frequency range. The receiver occupies only 1.89-mm2 chip area including test pads. To the best of the authors’ knowledge, the designed receiver front end has the widest bandwidth among reported receivers fabricated by using GaAs process. [ABSTRACT FROM AUTHOR]

This paper proposes a technique to enhance the maximum achievable power gain (GMAX) of the two-port active network (2PAN) in the near-ƒMAX region. This technique is based on using the optimized passive-linear-lossy-reciprocal (PLLR) embedding to increase the unilateral power gain (U) of the 2PAN and accordingly the GMAX. Due to the possibility to increase U, it shows the potential to improve the conventional gain-boosting approach which relies on the passive-linear-lossless-reciprocal (PLLLR) embedding and keeps the U constant. The concept itself is demonstrated on pseudo-differential NMOS pair using lossy capacitive feedback as the PLLR. This structure can serve as a basis for further gain optimization by implementing additional PLLLR embedding on top of it. Finally, by using the mentioned technique, a 190GHz amplifier is implemented in 28nm bulk CMOS technology, achieving 14.3dB of gain with 1.5dBm of PSAT and 2.6% of maximum PAE. [ABSTRACT FROM AUTHOR]

In-memory computing provides unprecedented power and area efficiency for the execution of convolutional neural networks by using memory bitcells to perform dot-product (DP) operations in the analog domain. Yet, these operators suffer from analog non-idealities (ANIs) that degrade the inference accuracy. This paper proposes design guidelines inferred from a holistic simulation-based analysis of the impact of ANIs on the accuracy-efficiency trade-off that affects current-domain DP operators based on conventional 6T-SRAM bitcell arrays. We define a custom SNR metric aware of the DP operand distribution to quantify decision errors associated with various ANIs, over ranges of input/output resolution and hardware design parameters. We find out that non-linearity and local mismatch are the dominant ANIs limiting the design space, while IR drops turn out to be critical only when targeting high parallelism. We then quantify the accuracy-efficiency trade-off related to these dominant ANIs across the design space and propose optimal design choices. We notably identify that using larger operators can either improve or worsen the SNR depending on the target output resolution. Furthermore, we show that hardware calibration techniques which mitigate mismatch help to recover a fraction of the lost SNR, with greater effectiveness when scaling down the supply voltage. [ABSTRACT FROM AUTHOR]

In-SRAM Computation improves the throughput and energy-efficiency of data-intensive applications by utilizing parallelism and reducing the data transfers. However, when multiple wordlines are accessed simultaneously, a short-circuit path will likely incur dynamic read disturbance and generate extra direct current in 6T Compute SRAM (CSRAM). In order to mitigate this issue, existing works either degrade the access speed, use area-hungry bitcells, or incur architecture-level overheads. In this paper, we first perform a comprehensive circuit-level analysis of the dynamic read disturbance issues of 6T SRAM for the first time and find that such disturbance can be efficiently avoided by maintaining the bitline voltage at a high level. Second, we propose a novel energy-efficient, reconfigurable sense amplifier design that is able to achieve fast and reliable sensing when the bitline voltage level is high for the compute access. Third, we propose an adaptive wordline control scheme that keeps the bitline voltage at a high level to eliminate the dynamic read disturbance and the sneaky direct current pathway. Both the new sense amplifier and adaptive wordline control are also optimized to support the normal read access efficiently. We have validated our design in a 55nm CMOS technology. Experimental results show that our design not only reliably addresses the read disturbance and the extra direct current, but also operates 19% faster than the state-of-the-art design using an advanced 28nm FDSOI technology. [ABSTRACT FROM AUTHOR]

This paper presents a passive vector-modulated phase shifter (VMPS). The passive X-type attenuator consisting of digitally controlled transistor-array units is employed to perform the phase-invertible gain tuning, and thus enables phase shift in all four quadrants. The Wilkinson-like power combiner is utilized to sum up the quadrature signals and avoid impedance mismatches. Analysis proves that the proposed passive VMPS can provide consistent phase-shift performance for bidirectional operation. The proof-of-concept VMPS is implemented in 40-nm CMOS technology and occupies a core chip area of 0.15 mm2. Measured results prove that it can provide consistent bidirectional 6-bit phase-shift operation, with accurate phase tuning (i.e., RMS phase error <24°) and low gain error (i.e., ±0.6 dB) over the whole 70–90 GHz band. [ABSTRACT FROM AUTHOR]

This paper presents fully-integrated analog neural network classifier architecture for low resolution image classification that eliminates memory access. We design custom activation functions using single-stage common-source amplifiers, and apply a hardware-software co-design methodology to incorporate knowledge of the custom activation functions into the training phase to achieve high accuracy. Performing all computations entirely in the analog domain eliminates energy cost associated with memory access and data movement. We demonstrate our classifier on multinomial classification task of recognizing down-sampled handwritten digits from MNIST dataset. Fabricated in 65nm CMOS process, the measured energy consumption for down-sampled MNIST dataset is 173pJ/classification, which is $3\times $ better than state-of-the-art. The prototype IC achieves mean classification accuracy of 81.3% even after down-sampling the original MNIST images by 96% from $28\times 28$ pixels to $5\times 5$ pixels. [ABSTRACT FROM AUTHOR]

This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 – 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 – 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in current-frequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training. [ABSTRACT FROM AUTHOR]

This paper presents the first experimental demonstration of a ternary memristor-CMOS logic family. We systematically design, simulate and experimentally verify the primitive logic functions: the ternary AND, OR and NOT gates. These are then used to build combinational ternary NAND, NOR, XOR and XNOR gates, as well as data handling ternary MAX and MIN gates. Our simulations are performed using a 50-nm process which are verified with in-house fabricated indium-tin-oxide memristors, optimized for fast switching, high transconductance, and low current leakage. We obtain close to an order of magnitude improvement in data density over conventional CMOS logic, and a reduction of switching speed by a factor of 13 over prior state-of-the-art ternary memristor results. We anticipate extensions of this work can realize practical implementation where high data density is of critical importance. [ABSTRACT FROM AUTHOR]

Convolution is one of the key operations in signal processing and machine learning applications. In this paper, we propose a novel convolution computing paradigm based on the NOR Flash array (NFA) that is capable of executing the 2-D convolution computing in one clock cycle. In order to demonstrate the feasibility and efficiency of the proposed convolution computing paradigm, the feature extraction task on an image with the size of $20\times 20$ is executed using the NFA structure. We also prove the NOR Flash-driven convolution computing is capable of processing the image with a larger size. This paper presents a new approach to realize convolution computing with high speed and energy efficiency for the signal processing and convolution neural network. [ABSTRACT FROM AUTHOR]