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Exploring singular perturbation and stability region theory, the foundations for decomposing the stability analysis of power systems in time scales is developed and a general algorithm, for stability analysis of power systems, which has transient stability analysis and quasi-steady state analysis as particular cases, is proposed. This algorithm bridges the gap between short and mid-term stability analysis and clearly establishes the conditions to guarantee stability of the original electrical power system model in terms of stability of the fast and slow subsystems. Simple examples illustrate the application of the proposed algorithm and its ability in delineating the evolution of the power system dynamics and identifying unstable modes. [ABSTRACT FROM AUTHOR]

In today's process technologies, power supply noise may cause serious clock jitter and circuit malfunction. Noise occurs by the fast and simultaneous voltage switching. A primary contributor to the noise is the clock-tree and the underlying sequential circuits that switch simultaneously, thus causing high current peaks. This work proposes to spread the switching of the clock-tree drivers, while maintaining low skew at the sinks of the tree, where the clocked circuits are connected. Driver switching characterization has been used for fast computation of peak currents, delays and slopes, integrated in a two-phase algorithm. It first constructs the clock-tree in a top-down traversal, employing a mix of high threshold voltage (HVT) and weak low threshold voltage (LVT) clock-drivers. A bottom-up delay correction phase then takes place, aiming at clock skew minimization. The algorithm was implemented in 40 nanometers TSMC process technology, achieving 35% to 70% clock-tree peak current reduction, translated to similar reduction in power supply noise. The proposed method can easily be combined with other existing methods to further reduce the noise. [ABSTRACT FROM AUTHOR]

Aggressive reduction of timing margins, called timing speculation, is an effective way of reducing the supply voltage for a pipeline circuit and thereby its power consumption. However, probability of timing error increases with the voltage scaling and hence, the errors must be corrected with small cycle penalty. We introduce an improved Razor flip-flop which makes more effective use of its shadow latch, so that a pipeline stage can correct an error while continuing to receive data. This avoids the need for repeated clock gating when timing errors happen simultaneously at different stages, or when an error persists. The new flip-flop also facilitates time-borrowing. Our technique uses less energy than the state-of-the art technique, and the energy saving increases with pipeline length: with 10 stages, 4–9% smaller energy is used. [ABSTRACT FROM AUTHOR]

Frequency characteristics of the total feedback loop of a current-mode buck DC-DC converter in the discontinuous conduction mode (DCM) are examined by formulating an equivalent small-signal transfer function using a proposed block structure that does not suffer direct influence from the current feedback. Utilizing this transfer function, it is clarified that the type of the compensation slope in a current feedback loop affects the loop frequency characteristics in DCM, and in terms of stability, high voltage gain and large 0-dB frequency bandwidth, the quadratic compensation slope is more effective than the linear compensation slope. The validity of the proposed block structure and formulations and the effectiveness of applying a quadratic compensation slope instead of a linear compensation slope in DCM are verified by comparing calculation results, SPICE simulation results and evaluation results using circuit and measurement data from an MOS current-mode buck DC-DC converter IC that had been previously fabricated. More than 10-dB higher voltage gain, three times larger 0-dB frequency bandwidth, more than 10-degree larger phase margin and faster recovery time in load current change are realizable in DCM compared with the case using a linear compensation slope. [ABSTRACT FROM AUTHOR]

Increasing the accuracy of circuit delay estimation using Non Linear Delay Model (NLDM) in nanometer range CMOS technologies is highly challenging. To solve this issue, people have started using effective current source model (ECSM) and composite current source model (CCSM), which can both be derived from each other. For a standard cell, ECSM stores certain predefined threshold crossing points (TCPs) of the output voltage waveform with respect to several input transition time (TR) and load capacitance (Cl) values. In this work, we propose an analytical timing model relating all TCPs with Cl and TR values for inverter standard cell. We derive the relationship between the cell size and the model coefficients. We also derive the region of validity of the model in (TR, Cl) space and determine its relationship with cell size. The proposed model is in good agreement with HSPICE simulations with a maximum error of 2.5%. We use this model and the derived relationships with cell size to reduce the number of simulations in ECSM library characterization. Due to process, voltage and on-chip temperature (PVT) variation, re-characterization is done at several PVT corners. In addition, layout dependent effects also lead to an unexpected variation in cell performance. To reduce the characterization effort, we derive relationships of variation of our model coefficients and regions of validity with cell size in mechanical stress enabled CMOS technologies, considering cell layout parameters. We also derive relationships of our model's coefficients with on-chip supply voltage and temperature variations. We use these relationships in reducing number of HSPICE simulations in ECSM re-characterization significantly. [ABSTRACT FROM PUBLISHER]

It has been verified that wireless power transfer (WPT) system with multiple relay resonators (repeaters) inserted properly between the transmitter and the receiver can increase the transmission distance significantly. Based on the coupled resonator bandpass filter model, a flexible design method for wireless power transfer system with arbitrary number of repeaters is proposed in detail. The transmission efficiency and the transferred power of the proposed wireless power transfer system are derived under the design theory of filters. It is illuminated the reason that Butterworth type is preferred type for designing WPT with multi-repeater. Moreover, the relation between transmission distance and bandwidth is examined and a technique is further introduced to increase the transmission distance. An RS=50\ \Omega WPT system with three repeaters is tested and another RS=0\ \Omega WPT system with one repeater is simulated, and the effectiveness of the proposed method is confirmed as well. [ABSTRACT FROM PUBLISHER]

The self-calibrated knee voltage detector (SC-KVD) for electrical isolation primary side charger applications is proposed. The removal of the feedback network which is used in conventional designs and occupies at least 30 mm^2 can save PCB area up to around 11%. Besides, the SC-KVD can dynamically adjust the detection point to improve the accuracy to 99.65% compared to the prior arts. The test chip fabricated in 0.5 \mum 500 V UHV process can be powered on directly by the AC source owing to the 500 V ultra-high voltage device. Hence, the battery charger can be made more compact and portable than it was and the battery life can be prolonged and guaranteed. [ABSTRACT FROM AUTHOR]

The efficiency of power amplifiers (PAs) with a small output power (POUT) for short-range wireless sensor networks is limited by the loss in matching networks. To achieve high efficiency, a new design method which calculates the complicated design parameters in a class-F PA with a merged filter and matching networks is proposed. The design method provides a new quantitative conclusion that reducing both the power supply voltage (VDD) and the impedance transformation ratio increases the efficiency of a PA with a small POUT. Using this result, a dual-VDD scheme is realized to increase the efficiency of a transmitter (TX). At a POUT of -20 dBm, compared with the conventional single-VDD scheme, the drain efficiency (DE) of the PA and the global efficiency (GE) of the TX with the dual-VDD scheme are increased by factors of 2.1 and 1.5, respectively. A PA fabricated by a 40 nm CMOS process achieved a DE of 42% at a POUT of -17 dBm. The TX with the PA achieves the highest GE of 28% at a POUT of -20 dBm and the lowest energy of 36pJ/bit (=36\ \muW@1Mbps with on-off keying) among the published results for TXs. [ABSTRACT FROM AUTHOR]

Modeling and design aspects of on-chip photovoltaic energy conversion, voltage boosting and storage in bulk CMOS are investigated under the constraints of indoor illumination and small form factor. A power-supply architecture consisting of a photovoltaic converter, a clock generator, a charge-pump and a storage capacitor is considered. Maximization of the recharging rate of the capacitor at the low end of irradiance is adopted as the aim of design optimization. First, photodiodes available for conversion in bulk CMOS are comparatively evaluated, and potentially the most efficient ones are experimentally characterized for the typical range of indoor irradiance. Next, a generic model is developed and experimentally verified for a clock generator powered by a converter built with these photodiodes. This is followed by the modeling and experimental verification of a Dickson charge-pump whose single-device rectifier is free of body effect and near-ideal in forward characteristic. These models are based on the subthreshold operation of devices as necessitated by optimization under the limitations of bulk-CMOS stacking and indoor irradiance. Guidelines for design optimization are derived from these models. Experimental work is based on two test chips fabricated in 0.18-\mu\ m bulk CMOS with deep n-well option. [ABSTRACT FROM AUTHOR]

Physically Unclonable Functions (PUFs) are emerging as hardware security primitives. So-called strong PUFs provide a mechanism to authenticate chips which is inherently unique for every manufactured sample. To prevent cloning, modeling of the challenge-response pair (CRP) behavior should be infeasible. Machine learning (ML) algorithms are a well-known threat. Recently, repeatability imperfections of PUF responses have been identified as another threat. CMOS device noise renders a significant fraction of the CRPs unstable, hereby providing a side channel for modeling attacks. In previous work, 65 nm arbiter PUFs have been modeled as such with accuracies exceeding 97%. However, more PUF evaluations were required than for state-of-the-art ML approaches. In this work, we accelerate repeatability attacks by increasing the fraction of unstable CRPs. Response evaluation faults are triggered via environmental changes hereby. The attack speed, which is proportional to the fraction of unstable CRPs, increases with a factor 2.4 for both arbiter and ring oscillator (RO) sum PUFs. Data originates from a 65 nm silicon chip and hence not from simulations. [ABSTRACT FROM AUTHOR]

A modular compact model for memristors which describes a wide range of memristive devices is presented. Its modular structure enables the modeling of various device behaviors by adopting different functions inside the comprising blocks. Rooted from the theoretical analysis on ideal memristors, the window function of the model is uniquely based on the constitutive relationship between charge and flux. This not only solves the stability issue from previously reported models, but also reveals that an equivalent charge-flux constitutive relationship can always be obtained from a variety of memristive devices. Simulations on three types of memristive devices demonstrate that the model is able to reflect common memristive device properties such as limited memristance switching range, linear/nonlinear memristance switching rate, threshold voltages for SET/RESET, nonlinear I-V characteristics, and device parameters with variations. [ABSTRACT FROM AUTHOR]

Sufficient conditions are derived for the global asymptotic synchronization of a class of identical nonlinear oscillators coupled through a linear time-invariant network. In particular, we focus on systems where oscillators are connected to a common node through identical branch impedances. For such networks, it is shown that the synchronization condition is independent of the number of oscillators and the value of the load impedance connected to the common node. Theoretical findings are then leveraged to control a system of parallel single-phase voltage source inverters serving an impedance load in an islanded microgrid application. The ensuing paradigm: i) does not necessitate communication between inverters, ii) is independent of system load, and iii) facilitates a modular design approach because the synchronization condition is independent of the number of oscillators. We present both simulation and experimental case studies to validate the analytical results and demonstrate the proposed application. [ABSTRACT FROM PUBLISHER]

In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 \mum standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case. [ABSTRACT FROM PUBLISHER]

The recently proposed Frequency-Translational Noise-Cancelling receiver demonstrates exceptional out-of-band linearity, a low noise factor, and wideband operation. Fundamental to the receiver's performance is the use of two passive-mixer-based downconversion paths, which delays noise-cancelling until after baseband filtering. As a result, voltage gain at blocker frequencies can be avoided, but the benefits of noise cancelling (i.e., wideband operation and low noise) can be retained. Although a simplified LTI analysis is sufficient to understanding the basic noise properties of the system, such an analysis cannot yield accurate closed-form expressions because it neglects the many signal and noise folding terms introduced by the two passive mixers. In this work, a complete LTV analysis is presented, which accurately captures both the gain and noise performance of the noise-cancelling receiver. Simulation results verify the analysis. [ABSTRACT FROM AUTHOR]

A CMOS Capacitance-to-Digital Converter (CDC) for capacitive sensors array applications is presented. It consists of a 16:1 multiplexer, a capacitance-to-voltage front-end and a 16-bit voltage-to-pulses converter. The proposed capacitance-to-voltage front-end circuit extends the dynamic range by charging or discharging the measured capacitive sensors indirectly. For low power consumption and short conversion time, hardware reuse technique and multi-steps quantization method have been applied in voltage-to-digital pulse converter design. This 16-ch CDC's maximum absolute input capacitance is 350 pF under a non-uniform distributed sampling interval of 0.15–0.75 ms with 90 \muA current consumption under \pm0.9 V voltage supply. This prototype chip has been designed and fabricated in 0.18-\mum 1P6M CMOS process with active area of 640\,\times\,630 \mum^2 [ABSTRACT FROM AUTHOR]

A triple-mode step-up/step-down switched-capacitor DC-DC converter is proposed, and it can work with a wide input voltage range. There are three operational modes in the proposed converter: triple-step-up, double-step-up, and step-down modes. A built-in clock generator was designed to generate a constant switching frequency, independent of the input voltage. The proposed circuit was implemented by a 0.35-\mum CMOS mixed-signal 2P4M 3.3/5 V polycide process with a die area of 1.56\times 1.47\ mm^2. The output voltage is fixed at 3.3 V, while the input voltage range is 1.8–5 V. The maximal load current for a 1.8-V input voltage is 10 mA, while it increases to 30 mA when the input voltage is larger than 3 V. [ABSTRACT FROM PUBLISHER]

A fully integrated 256-Mcell multi-level cell (MLC) phase-change memory (PCM) chip in 90-nm CMOS technology is presented. The on-chip circuitry supports fast MLC operation at 4 bit/cell. A programmable digital controller is used to optimize closed-loop gain and timing of the iterative MLC programming scheme and two power-efficient 8-bit DACs support current-controlled as well as voltage-controlled write pulses. The read-out consists of a low-power auto-range frontend followed by a 6-bit cyclic ADC that converts the nonlinear PCM resistance in a range between 10 k\Omega and 10 M\Omega. A verilog-A model derived from a full 3-D simulation of the PCM cell was developed to simulate the complete chip. The chip was used to demonstrate operation at 2 bit/cell and programming below 10 \mus with Ge2Sb2Te5 (GST) based PCM cells at a raw bit error rate of \sim 2 \times 10^- 4. Two main roadblocks for MLC PCM are drift and endurance. The accuracy of the analog frontend in combination with the programmable controller enables drift mitigation at the system level and the exploration of new materials for MLC operation at 3+ bit/cell. [ABSTRACT FROM PUBLISHER]

A novel process and temperature compensation design for 2\,\times\,VDD output buffers is proposed, where the threshold voltages (Vth) of PMOSs and NMOSs varying with process and temperature deviation could be detected, respectively. A prototype 2\,\times\,VDD output buffer using the proposed compensation design is fabricated using a typical 0.18 \mum CMOS process. By adjusting output currents, the slew rate of output signals could be compensated over 117%. The maximum data rate with compensation is 120 MHz in contrast with 95 MHz without compensation, which is measured on silicon with an equivalent probe capacitive load of 10 pF. [ABSTRACT FROM PUBLISHER]

Frequency splitting phenomena are investigated systematically by circuit theory in a series-tuned contactless power transfer (CPT) system. First, in a symmetrical CPT system, the splitting equation is defined and the key frequency splitting characteristics are described by the trough and the ridge equations in a complete fashion. The even and the odd splitting frequencies are exactly two roots of the ridge equation; the splitting coupling is determined theoretically when the even and odd splitting frequencies merge together. Second, in an unsymmetrical CPT system, the idea of the trough and the ridge equation is exploited to find exactly the splitting coupling. Next, the relationship between frequency bifurcation and splitting is elucidated; and a zero-phase control method is suggested to track the splitting frequency when the coupling changes in the splitting region. Finally, the theoretical results are validated by a 10-W prototype with planar spiral coils. [ABSTRACT FROM PUBLISHER]

The use of pathological elements (i.e., nullators, norators, and the voltage mirror-current mirror pair) as universal active elements opens up the possibility to model the behavior of active devices with either differential features or input-output multiples, in order to be used in analysis tasks of linear(ized) analog circuits. This brief tries on the modeling this class of active devices, which is carried out by considering the impedance characteristics along with the behavior equation of each active device, the kind of signal to be processed and by applying the pathological element properties. In order to obtain a more realistic model, not only parasitic elements associated to the input-output terminals of each active device are considered, but the tracking errors of voltage and current differential followers modeled with grounded pathological elements and admittances are also included. Due to that the gain and tracking errors are finites and of limited bandwidth, a two-pole model is used for each of them in order to include their contributions on the symbolic expressions computed. Because the behavior of fully-differential amplifiers is modeled with grounded pathological elements, a standard nodal analysis can be performed. This imply that not only the size of the admittance matrix is smaller than those generated by applying modified nodal analysis (MNA) method, for instance, but also the number of nonzero elements and the generation of cancellation-terms are both reduced. As a result, the computational complexity during the solution of the system of equations is reduced when recursive determinant-expansion techniques are applied. Examples are described and compared with the MNA method, in order to show the usefulness of the proposed models to compute fully-symbolic small-signal characteristics of analog circuits containing fully-differential active devices and/or with input-output multiples. [ABSTRACT FROM AUTHOR]

The work here involves the development of a theory providing necessary and sufficient conditions for the property of essentiality, which was first introduced and defined by Barmish and Kettani. These conditions provide means to ascertain whether the individual unknown elements of a resistive network can be characterized as having the property of essentiality, which in turn is shown to have significant impact on the manner in which their uncertain parameter values influence overall network performance. While the work is immediately motivated by circuits and power network problems, it is anticipated to be generalizable to a range of linear system fault detection problem having an underlying network structure. In particular, this concept proves useful as a technique for robust fault detection and fault isolation. [ABSTRACT FROM AUTHOR]

A low noise transimpedance amplifier (TIA) is used in radiation detectors to transform the current pulse produced by a photo-sensitive device into an output voltage pulse with a specified amplitude and shape. We consider here the specifications of a PET (positron emission tomography) system. We review the traditional approach, feedback TIA, using an operational amplifier with feedback, and we investigate two alternative circuits: the common-gate TIA, and the regulated cascode TIA. We derive the transimpedance function (the poles of which determine the pulse shaping); we identify the transistor in each circuit that has the dominant noise source, and we obtain closed-form equations for the rms output noise voltage. [ABSTRACT FROM PUBLISHER]

An inherent shortcoming of rectifiers designed using standard CMOS devices is poor low input power performance. It is shown that this can be overcome through the use of intrinsic devices with close to zero-threshold voltage available in a 0.25\mum silicon-on-sapphire (SOS) CMOS process. A novel complementary bridge rectifier structure based on a combination of cross-connected and diode bridge rectifier topologies is introduced to avoid the excessive leakage current incurred through the use of intrinsic devices. A design strategy which maximizes efficiency and produces an input impedance which will interface well with the inductive coil type antennas used in biomedical implants is presented for this new rectifier type. The fabricated rectifier achieves a 1 \muW DC output power for an input power of -26.5 dBm at 100 MHz. A peak measured power conversion efficiency (PCE) of 67% is achieved at 100 MHz, but more importantly >30% PCE is attained for a wide output power range which reaches as low as -40 dBm. At the target 1 \muW output power a PCE of 44% was achieved. [ABSTRACT FROM PUBLISHER]

A 5 GHz double balanced mixer (DBM) is implemented in standard 90 nm CMOS low-power technology. A novel low-voltage self-bias current reuse technique is proposed in the RF transconductance stage to obtain better third-order intermodulation intercept point (IIP3 ) and conversion gain (CG) when considering the process variations. The DBM achieves a CG of 12 dB, a noise figure (NF) of 10.6 dB and port-to-port isolations of better than 50 dB. The input second-order (IIP 2) and IIP 3 are 48 dBm and 4 dBm, respectively. Two I/Q DBMs are then integrated with a differential low-noise amplifier (DLNA) and a poly-phase filter, to from a direct-conversion receiver (DCR). The DCR achieves a CG of 26 dB with an NF of 2.7 dB at 21 mW power consumption from a 1 V supply voltage. The port-to-port isolations are better than 50 dB. The IIP2 and the IIP3 of the DCR are 33 dBm and -12 dBm, respectively. [ABSTRACT FROM PUBLISHER]

An improved zero-voltage-switching (ZVS) dc-dc converter with a high voltage gain and a ripple-free input current is proposed. It consists of two converter cells - a boost cell and an asymmetrical pulse-width-modulation (APWM) full-bridge cell. The boost cell in the proposed converter has the capabilities of providing a ripple-free input current. The APWM full-bridge cell provides a high voltage gain. The output diodes are under zero-current-switching (ZCS) during turn-off. The proposed converter has high efficiency due to soft-switching operation in full-bridge switches. Steady-state analysis of the converter is presented to determine the circuit parameters. A laboratory prototype of the proposed converter is developed, and its experimental results are presented for validation. [ABSTRACT FROM AUTHOR]

Charge balance analysis and state transition analysis are presented in analyzing hysteretic voltage mode switching converters working in the steady state. It is shown that the ideal buck converter with a current-sink load can only work in discontinuous conduction mode (DCM) but not in continuous conduction mode (CCM), and the same converter with a resistive load can work in CCM, but the output voltage ripple is very large compared to the hysteresis window. Previously published CCM designs are functional because their operations actually rely on the small but nonzero equivalent series resistance (ESR) of the filtering capacitor. For the CCM buck converter with nonzero ESR, our proposed state transition analysis gives a much more accurate switching frequency than previous approaches. The hysteretic voltage mode boost and buck-boost converters are then analyzed, and shown to have no feasible operating region. Crucial simulation results are presented to confirm the analyses. [ABSTRACT FROM PUBLISHER]

We suggest an approach to use memristors (resistors with memory) in programmable analog circuits. Our idea consists in a circuit design in which low voltages are applied to memristors during their operation as analog circuit elements and high voltages are used to program the memristor's states. This way, as it was demonstrated in recent experiments, the state of memristors does not essentially change during analog mode operation. As an example of our approach, we have built several programmable analog circuits demonstrating memristor-based programming of threshold, gain and frequency. In these circuits the role of memristor is played by a memristor emulator developed by us. [ABSTRACT FROM PUBLISHER]

An analysis of the Class-E power amplifier is given using harmonic modeling that facilitates its characterization for a wide load-space regime expected in applications such as RF plasma generation for semiconductor manufacturing. Using a hybrid matrix- framework made up of the dominant harmonics of the circuit variables aided by the time-domain boundary conditions of the power switch voltage waveform, a quasi-linear algorithm is developed to accurately determine the voltage and the current levels expected on all components of the power amplifier for arbitrary loading and operating conditions. The application of the algorithm for design optimization is discussed, and its extension to phase-controlled Class-E power amplifier pairs is described. [ABSTRACT FROM AUTHOR]

A previous cut-insertion theorem for linear circuits and its application to a generalization of the elementary feedback theory are further extended. The new theorem is based on the splitting of an arbitrary node into two nodes and on the insertion between them and another arbitrary "reference" node, of a three-terminal circuit which keeps the network currents and voltages unchanged. The system analysis is in turn performed on the equivalent cut network by means of the techniques for two-port circuits, using generic variables, i.e., either voltages or currents. The new approach allows one to define a two-port circuit as an open loop around the split and reference nodes, as well to define a new feedback model specifically focused on it. Furthermore, it allows one to retrieve all the results of the previous general feedback theories, as well as several new ones. The obtained expressions of the overall transfer function include, as a particular case, the Blackman formula for the immittances, and relationships without the leakage term, which are useful for circuit synthesis and for dealing with spurious signals. New expressions are proposed for the evaluation of the output and input immittances. The virtual short-circuit method is derived and numerical and design examples are provided. The new approach retains the intuitive feedback vision of the elementary models. [ABSTRACT FROM AUTHOR]

The general performance of class AB switched currents (SI) is analyzed using the general MOS equations valid for all regions of operation. Using a figure-of-merit combining speed, dynamic range, and power consumption, the overall performance is shown to improve progressively as the SI memory transistors' operating region is moved from strong inversion to moderate and then weak inversion. The analysis is validated first by experiment using transistor arrays and then by simulation using 0.35-μm, 0.18-μm, and 90-nm CMOS process data. After discussing nonideal behavior of the weak inversion memory cell, the following two practical designs are described: a cascoded class AB memory at 1.25-V supply in the 3.3-V 0.35-μm process and a two-step sampling class AB memory at 0.6-V supply in the 1.8-V 0.18-μm process, and each demonstrates good performance. [ABSTRACT FROM AUTHOR]

A method for the design of continuous-time systems approximating prescribed impulse response is presented. The method is based on the least-squares error criterion. Using zero-pole-gain representation of the system, a constrained optimization problem is formed. The optimum is found by iterative procedure in which a second-order cone program is solved in each iteration. The method is applied in the design of continuous-time wavelet filters and high-voltage pulse-forming networks. It proved to be fast with low sensitivity to the iteration starting-point. Furthermore, it is suitable for the design of high-order systems. [ABSTRACT FROM AUTHOR]

Power consumption in match lines is the most critical issue for low-power ternary content-addressable memory (TCAM) designs. In the proposed match-line architecture, the match line in each TCAM word is partitioned into four segments and is selectively pre-charged to reduce the match-line power consumption. The partially charged match lines are evaluated to determine the final comparison result by sharing the charges deposited in various parts of the partitioned segments. This arrangement reduces the match-line power consumption by reducing effective capacitor loading and voltage swing at match lines. The segmented architecture also enhances operational speed by evaluating multiple segments in parallel and by overlapping the pre-charging and evaluation stages. 512 × 72 TCAM is designed using 0.18-µm CMOS technology. The extracted RC values are used to show the power reduction benefits. The sample design demonstrated that the match-line power consumption using a segmented match line was conservatively 44% of that produced by traditional parallel TCAM. The power savings by segmenting match lines can be up to 41% over a low-voltage swing technique due to the independent discharge capability in segmented match-line architecture. [ABSTRACT FROM AUTHOR]

We develop a method to configure a 3-D nonlinear nanoparticle-molecule network to performing ten out of twelve possible combinations of two 2-bit logic gates with shared inputs. The logic gates are based on a simple circuit with adjustable linear and fixed negative differential resistance (NDR) elements. A bistable latch for signal restoration is an integral part of this target circuit. The simulations show that conductive patterns can be formed by applying voltages on the input-output pins of the nanocell. They also show that one-link gaps (short highly resistive links) can be created within the conductive channels. Furthermore, we discuss methods for introducing NDR molecules in these gaps, a crucial element of the target circuit. The structures resulting from the simulations are put in an architectural context, in which complex functions can be realized from the individual nanocell logic gates. [ABSTRACT FROM AUTHOR]

Photovoltaic (PV) power has been successfully used for over five decades. Whether in dc or ac form, photovoltaic cells provide power for systems in many applications on earth and space. Its principles of operation are therefore well understood, and circuit equivalents have been developed that accurately model the nonlinear relationship between the current and voltage of a photovoltaic cell. With the improved efficiencies of power electronics converters, it is now possible to operate photovoltaic system about its maximum power point (MPP) in order to improve the overall system efficiency. Hitherto, this problem has been tackled using tracking (MPPT) algorithms that iteratively find the point of maximum power and respond to changes in solar irradiance accordingly. A mathematical manipulation that uses the mean value theorem is presented here that provides the analytic solution of a point in a close neighborhood of the MPP. It is thoroughly proved that this point is enclosed in a ball of small radius that also contains the MPP and therefore can practically be considered as the MPP. Since the solution is analytic, no iterative schemes are necessary, and only a periodic measurement is required to adjust to changes in solar irradiance. A circuit is implemented that shows the validity of the theory and the accuracy of the solution. [ABSTRACT FROM AUTHOR]

A 1-V current reference fabricated in a standard CMOS process is described. Temperature compensation is achieved from a bandgap reference core using a transimpedance amplifier in order to generate an intermediate voltage reference, VREF. This voltage applied to the gate of a carefully sized nMOS output transistor provides a reference drain current, IREF, nearly independent of temperature by mutual compensation of mobility and threshold voltage variations. The circuit topology allows for compensation of threshold voltage variation due to process parameters as well. The current reference has been fabricated in a standard 0.18-µm CMOS process. Results from nineteen samples measured over a temperature range of 0 °C to 100 °C, showed values of IREF of 144.3 µA ± 7% and VREF of 610.9 mV ± 2% due to the combined effect of temperature and process variations. [ABSTRACT FROM AUTHOR]

A new family of single-stage super Class-AB operational transconductance amplifiers (OTAs) suitable for low-voltage operation and low power consumption is presented. Three novel topologies are proposed featuring simplicity and compactness. They are based on the combination of adaptive biasing techniques for the differential input stage and nonlinear current mirrors for the active load that provide additional dynamic current boosting. The OTAs have been fabricated in a standard 0.5-mum CMOS process. Experimental results show a greatly improved slew rate by factors 30-60 and gain-bandwidth product by factors 11.5-17 when compared to a classical Class-A OTA. The circuits are operated at plusmn1-V supply voltage with only 10 muA of bias current [ABSTRACT FROM PUBLISHER]

As the clock frequency and physical address space of 64-bit microprocessors continue to grow, one major critical path is the access to the on-die cache memory that includes a tag comparator, a tag SRAM and a data SRAM. To improve the delay of the tag comparator, a diode-partitioned (DP) domino circuit is proposed. DP domino reduces the parasitic capacitance and enables a smaller keeper in high fan-in gates. The diode circuit is also improved by an enhanced diode that boosts up the gate voltage of the nMOS diode. Delay of a 40-bit tag comparator using the proposed scheme is 33% faster than an optimized complex domino circuit in 1.8-V 180-nm CMOS technology. [ABSTRACT FROM AUTHOR]

Design strategy and efficiency optimization of ultrahigh-frequency (UHF) micro-power rectifiers using diode-connected MOS transistors with very low threshold voltage is presented. The analysis takes into account the conduction angle, leakage current, and body effect in deriving the output voltage. Appropriate approximations allow analytical expressions for the output voltage, power consumption, and efficiency to be derived. A design procedure to maximize efficiency is presented. A superposition method is proposed to optimize the performance of multiple-output rectifiers. Constant-power scaling and area-efficient design are discussed. Using a 0.18-μm CMOS process with zero-threshold transistors, 900-MHz rectifiers with different conversion ratios were designed, and extensive HSPICE simulations show good agreement with the analysis. A 24-stage triple-output rectifier was designed and fabricated, and measurement results verified the validity of the analysis. [ABSTRACT FROM AUTHOR]

A 64-pixel linear array aimed at 3-D vision applications is implemented in a high-voltage 0.8 μm CMOS technology. The detection of the incident light signals is performed using photodiodes biased above breakdown voltage so that an extremely high sensitivity can be achieved exploiting the intrinsic multiplication effect of the avalanche phenomenon. Each 38 × 180-μm² pixel includes, besides the single photon avalanche diode, a dedicated read-out circuit for the arrival-time estimation of incident light pulses. To increase the distance measurement resolution a multiple pulse measurement is used, extracting the mean value of the light pulse arrival-time directly in each pixel; this innovative approach dramatically reduces the dead-time of the pixel read-out, allowing a high frame rate imaging to be achieved. The sensor array provides a range map from 2 m to 5 m with a precision better than ±0.75% without any external averaging operation. Moreover, with the same chip, we have explored for the first time the implementation of an indirect time-of-flight measurement by operating the proposed active pixel in the photon counting mode. [ABSTRACT FROM AUTHOR]

Differential flatness of buck, buck-boost, and boost converter models is shown. Its benefits if used for controlling the output voltage of these converters are revealed by comparing the flatness-based control with passivity-based and linear control. Two observers for the boost converter are suggested one of which requires only the measurement of the converters output voltage. Both observers can be used with minor changes for the buck-boost converter. Two flatness-based online trajectory planning algorithms are suggested. They exploit the parametrization of the trajectories in the energy. One of them is designed to achieve fast setpoint transitions during converter start-up or despite sudden load steps while simultaneously respecting the converters physical constraints. The other one is considered for applications in power factor correction. Different stabilization strategies are compared. The viability of the observers, the algorithm, and the stabilization strategies are verified by simulations of switched nonideal converter models. [ABSTRACT FROM AUTHOR]

Iterative decoders, including Turbo decoders, provide near-optimal error protection for various communication channels and storage media. CMOS analog implementations of these decoders offer dramatic savings in complexity and power consumption, compared to digital architectures. Conventional CMOS analog decoders must have supply voltage greater than 1 V. A new low-voltage architecture is proposed which reduces the required supply voltage by at least 0.4 V. It is shown that the low-voltage architecture can be used to implement the general sum-product algorithm. The low-voltage analog architecture is then useful for implementing Turbo and low-density parity check decoders. The low-voltage architecture introduces new requirements for signal normalization, which are discussed. Measured results for two fabricated low-voltage analog decoders are also presented. [ABSTRACT FROM AUTHOR]

A detailed analysis and optimized-oriented design of a family of three-level soft-switching converters is presented. The zero-voltage-switching (ZVS) of the outer switches and zero-cur- rent-switching (ZCS) of the inner switches is realized by employing a pulse-width-modulation (PWM) phase-shift control and a secondary-assisted passive snubber. The switching operation is discussed by comparing the results produced by the use of different passive snubbers (the author's original one and literature-available ones). The voltage on the rectifier diodes is clamped at a reasonable value, specific to each one of the six snubbers taken into consideration. The voltage stress on each transistor is reduced to half of the input voltage. Lower rated transistors and rectifier diodes can be used, thus reducing the conduction losses. Before turning on/off the inner switches, the snubber's capacitor voltage determines the fall of the primary current to zero, thus avoiding wasteful energy circulation and assuring ZCS. The snubber's energy is recuperated to the load. The outcome of these improvements is a high efficiency in energy processing. Soft-switching-oriented constraints on the converter parameters are expressed as implicit equations, whose graphical solution permits the optimized design of the parameters in order to ensure ZVZCS. A comparative analysis of the effective duty cycle and the boost effect of it, due to the use of the secondary snubber, is performed. The influence of the choices of the parameters values on the regulation capability is pointed out. Experimental results prove the expected high performances of the optimized converters. [ABSTRACT FROM AUTHOR]

The difficulty of realizing the operations of addition and subtraction of a voltage-mode signal renders two special active elements, namely, differential difference current conveyors (DDCCs) and fully differential current conveyors (FDCCIIs), both of which have the ability to perform the operations of addition and subtraction, to become very important for voltage-mode analog filter design. Note that, for the design of operational transconductance amplifier and capacitor (OTA-C) filters, the recently reported analytical synthesis methods (ASMs) have been shown to be very effective for achieving simultaneously the three criteria, namely, all capacitors being grounded, the use of the minimum number of active and passive components, and the use of single-ended input OTAs. However, none of the ASMs uses DDCCs and FDCCIIs in the design of voltage-mode filters. In this paper, a method of realizing DDCC and FDCCII-based all-pass filter structures with either equal capacitances or equal conductances through a new ASM is presented. Only n current conveyors (the least number of active components), n grounded capacitors, and n grounded resistors (the minimum number of passive components) are used for realizing an nth-order voltage-mode all-pass filter structure. Moreover, the new all-pass filter structure synthesized by the new ASM achieves very low individual as well as near-null group sensitivities just as in the case of the passive LC ladder filters, has very low power consumption, a low component spread for equal denominator conductance design, and a high input impedance which is attractive from the point of view of cascadability. Finally, H-Spice simulations, using 0.35-µm process and ± 1.65-V supply voltages, are included and validate theoretical predictions. [ABSTRACT FROM AUTHOR]