243 results
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2. A Three-Stage Charge Pump With Forward Body Biasing in 28 nm UTBB FD-SOI CMOS.
- Author
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Pinheiro, Carlos A., Olivera, Fabian, and Petraglia, Antonio
- Subjects
- *
ON-chip charge pumps , *SUPERCAPACITORS , *ENERGY harvesting , *STORAGE battery charging - Abstract
Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
3. A T-Type Switched-Capacitor Multilevel Inverter With Low Voltage Stress and Self-Balancing.
- Author
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Wang, Yaoqiang, Yuan, Yisen, Li, Gen, Ye, Yuanmao, Wang, Kewen, and Liang, Jun
- Subjects
- *
CIRCUIT complexity , *CAPACITORS , *SWITCHING circuits , *VOLTAGE - Abstract
This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
4. A Low-Profile Autonomous Interface Circuit for Piezoelectric Micro-Power Generators.
- Author
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Ciftci, Berkay, Chamanian, Salar, Koyuncuoglu, Aziz, Muhtaroglu, Ali, and Kulah, Haluk
- Subjects
- *
INTERFACE circuits , *OPEN-circuit voltage , *ENERGY harvesting , *MAXIMUM power point trackers , *PHOTOVOLTAIC power systems , *POWER electronics - Abstract
This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
5. A Series Stacked IGBT Switch Based on a Concentrated Clamp Mode Snubber for Pulsed Power Applications.
- Author
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Zarghani, Mostafa, Mohsenzade, Sadegh, and Kaboli, Shahriyar
- Subjects
- *
POWER semiconductor switches , *INSULATED gate bipolar transistors , *TRANSISTORS , *SHORT circuits , *ELECTROSTATIC discharges , *DRUG side effects , *POWER resources - Abstract
Clamp mode snubbers are very well suited for the series structure of the insulated-gate bipolar transistors (IGBTs) in pulsed power applications. They properly meet the necessities expected from them such as the fast operating of the series IGBTs since they have no effect on the gate side. In addition, they can provide safe voltage condition for the IGBTs in short circuit faults, which are very probable in pulsed applications. The clamp mode snubber can perform its voltage balancing task whenever the power capacity of the snubber can support the injected powers due to the voltage unbalancing factors. This paper initially introduces the main factors injecting power to the snubbers. Then, it will be illustrated that the exact injected power to each predetermined snubber cannot be determined due to the uncertainties about the effect of the voltage unbalancing factors. Although it is impossible to determine the exact value of the power injected to each snubber, the total injected powers to the snubbers can be calculated. Therefore, as an effective remedy, this paper proposes a concentrated snubber. Using the proposal, all the injected powers are conducted to a centralized circuit and can be easily managed. In addition, analytical expressions are provided for proper dimensioning of the proposed concentrated snubber elements. Furthermore, the performance of the proposed concentrated snubber is evaluated using simulations and experimental prototyping. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
6. Switched-Capacitor Boost-Buck Ladder Converters With Extended Voltage Range in Standard CMOS.
- Author
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Liu, Jingqi and Gregori, Stefano
- Subjects
- *
VOLTAGE-frequency converters , *CAPACITOR switching , *COMPLEMENTARY metal oxide semiconductors , *OVERVOLTAGE , *SWITCHING circuits , *CAPACITORS , *ELECTRIC capacity , *ELECTRIC potential - Abstract
This paper presents fully integrated switched-capacitor boost-buck power converters with conversion ratios 5, 7, and 1/5. Such converters operate over a voltage range extended beyond the device ratings due to a low-voltage-stress configuration, accumulation-mode NMOS capacitors, and a circuit technique for switch bootstrapping. After modeling the simple and the symmetrical ladder converters, we determined methods for assessing the device working voltages and for optimizing the sizes of capacitors and switches. The key performance parameters were compared and the losses due to non-linear parasitic capacitances were calculated. The characterization of the prototypes in a 1.8–3.3-V, 0.18- $\mu \text{m}$ CMOS process demonstrated a 15 V range, a 5.4 mW/mm2 output power density, and good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
7. A 0.6-V 10-bit 200-kS/s SAR ADC With Higher Side-Reset-and-Set Switching Scheme and Hybrid CAP-MOS DAC.
- Author
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Zhang, Hongshuai, Zhang, Hong, Sun, Quan, Li, Jijun, Liu, Xipeng, and Zhang, Ruizhi
- Subjects
- *
COMPLEMENTARY metal oxide semiconductors , *SUCCESSIVE approximation analog-to-digital converters , *ELECTRIC capacity - Abstract
This paper presents a low-power and area efficient 10-bit SAR ADC with higher side-reset-and-set (HSRS) switching scheme and hybrid capacitive-MOS (CAP-MOS) DAC. The HSRS switching scheme consumes zero switching energy for the two most-significant bits and skips unnecessary switching without using any auxiliary circuit. It is further verified in this paper that the HSRS switching scheme shows lower nonlinearity compared with the conventional CDAC structure with the same unit capacitor size and matching condition. This additional advantage permits using DAC topologies with lower total capacitance under given linearity requirement. A hybrid CAP-MOS DAC is adopted to reduce the total capacitance of the DAC, which consumes lower static current and chip area than the conventional hybrid capacitive-resistive DAC under the same settling requirement. The prototype 10-bit SAR ADC is implemented in a 0.18- $\mu \text{m}$ CMOS technology, showing an SNDR/SFDR of 56.43 dB/71 dB at 90-kHz input, under a 0.6-V power supply, while consuming $1.01~\mu \text{W}$ at 200 kS/s for a figure of merit of 9.32 fJ/conv.-step. The ADC occupies only a small active area of 0.0675 mm2. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
8. Slewing Mitigation Technique for Switched Capacitor Circuits.
- Author
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Kareppagoudr, Manjunath, Shakya, Jyotindra, Caceres, Emanuel, Kuo, Yu-Wen, and Temes, Gabor C.
- Subjects
- *
SWITCHED capacitor circuits , *CAPACITOR switching , *OPERATIONAL amplifiers , *SIGNAL-to-noise ratio , *SWITCHING circuits , *ELECTRONIC modulators - Abstract
Slewing in switched capacitor (SC) circuits reduces the available time for linear settling, and hence increases the nonlinear settling error. This transient demand in current can be supplied by making the bias currents larger in the operational transconductance amplifier (OTA). However, this increases the static power consumption significantly. In this paper a slewing mitigation technique is presented where just the right amount of charge is provided at the switching instant to the SC circuit so that OTA does not need to provide high peak current. This may eliminate slewing altogether, and allows using OTAs with less static current for the same settling accuracy. The operation of the proposed technique is illustrated by incorporating it in a second-order delta-sigma modulator (DSM). The modulator was designed and simulated in a 65nm CMOS process. Post-layout extracted simulations with optimized design show more than 12 dB improvement in signal to noise and distortion ratio (SNDR) for the same static power. Alternatively, compared to a DSM without such technique, the same performance can be achieved with 30% less power. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
9. A 12-bit SAR ADC With a DAC-Configurable Window Switching Scheme.
- Author
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Chung, Yung-Hui, Zeng, Qi-Feng, and Lin, Yi-Shen
- Subjects
- *
SUCCESSIVE approximation analog-to-digital converters , *DIGITAL-to-analog converters , *CAPACITOR switching , *ANALOG-to-digital converters , *SIGNAL-to-noise ratio , *DIGITIZATION - Abstract
This paper presents a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) that uses a digital-to-analog converter (DAC) configurable window switching technique. By reusing the capacitors in the DAC, the proposed window switching scheme yields window boundaries to determine whether the input is located within the window, and thus avoid unnecessary capacitor switching. The proposed window SAR ADC improves the conversion efficiency and ADC linearity. A qualitative analysis of prior window switching schemes is presented to elaborate for various applications. A low-input capacitance of 1 pF was adopted to relax the input and reference buffers. A prototype ADC was implemented in 180-nm CMOS occupying an active area of 0.1 mm2. At 20 MS/s, it consumes a total power of 1.22 mW from a 1.5-V supply. The measured peak signal-to-noise and distortion ratio and spurious-free dynamic range were 61.7 and 79 dB, respectively. At the Nyquist rate, the measured effective number of bits (ENOB) was 9.53, equivalent to a figure-of-merit (FOM) of 83 fJ/conversion-step. In low-power mode (100 kS/s), it consumed a total power of $1.5~\mu \text{W}$ from a 0.7-V supply. At the Nyquist rate, the measured ENOB was 9.82, equivalent to a FOM of 16.6 fJ/conversion step. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
10. Pulsewidth Modulation Control Algorithm for a Six-Phase PMSM: Reducing the Current in the Inverter Capacitor and Current Sensing With Resistors.
- Author
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Suzuki, Takashi, Hayashi, Yoshitaka, Kabune, Hideki, and Ito, Norihisa
- Subjects
- *
PULSE width modulation , *PERMANENT magnet motors , *ELECTRIC inverters , *SWITCHING circuits , *CAPACITORS - Abstract
Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
11. LCLC Converter With Optimal Capacitor Utilization for Hold-Up Mode Operation.
- Author
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Chen, Yang, Wang, Hongliang, Hu, Zhiyuan, Liu, Yan-Fei, Liu, Xiaodong, Afsharian, Jahangir, and Yang, Zhihua
- Subjects
- *
CASCADE converters , *HIGH voltages , *ELECTRIC inductors , *MAGNETIZATION , *SWITCHING circuits - Abstract
In data center and telecommunication power supplies, the front-end dc–dc stage is required to operate with a wide input voltage range to provide hold-up time when ac input fails. Conventional LLC converter serving as the dc–dc stage is not suitable for this requirement, as the normal operation efficiency (at 400 V input) will be penalized once the converter is designed to achieve high peak gain (wide input voltage range). This paper examined the operation of the LCLC converter and revealed that the LCLC converter could be essentially equivalent to a set of LLC converters with different magnetizing inductors that are automatically adjusted for different input voltages. In nominal 400 V input operation, the LCLC converter behaves like an LLC converter with large magnetizing inductor, thus the resonant current is small. In the hold-up period, when the input voltage reduces, the equivalent magnetizing inductor will reduce together with switching frequency reducing, thus the converter achieves high peak gain. In this paper, a new design methodology is also proposed to achieve optimal utilization of the two resonant capacitors for high power application. To verify the effectiveness of the LCLC converter for hold-up operation, comprehensive analysis has been conducted; a detailed step by step design example based on capacitor voltage stress is introduced; an experimental LCLC prototype optimized at 400 V, with input voltage range of 250–400 V and 12 V/500 W as output has been presented. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
12. Investigation of a New Modular Multilevel Converter With DC Fault Blocking Capability.
- Author
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Hu, Xing, Zhang, Jianzhong, Xu, Shuai, and Jiang, Yongjiang
- Subjects
- *
CASCADE converters , *POWER transmission , *LOW voltage systems , *ELECTRIC power transmission , *ELECTRIC circuits - Abstract
Modular multilevel converter (MMC) has been a promising candidate in high voltage direct current (HVdc) transmission systems. Due to the features of simple structure, low cost, and low power losses, half-bridge (HB) is usually adopted as the submodule circuit in the traditional MMC. However, an HB submodule circuit-based MMC does not have the capability of blocking dc short-circuit fault, which obstructs the development of low-cost HVdc systems with overhead lines. In order to solve this problem, an MMC with active clamped T-type submodule (ACTSM) to own dc fault blocking capability is proposed in this paper. Compared with other submodule circuits, the proposed ACTSM has many features, such as symmetrical blocking capability, low power losses, low voltage stress, and low amount of independent drive signals. The topology, operation principle, dc fault blocking capability, and distribution of power losses of the ACTSM are presented in this paper. The effectiveness of the ACTSM-based MMC is validated by both simulations and experiments. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
13. Modulated Model Predictive Control of Modular Multilevel Converters in VSC-HVDC Systems.
- Author
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Mahmoudi, Hamid, Aleenejad, Mohsen, and Ahmadi, Reza
- Subjects
- *
PREDICTIVE control systems , *CASCADE converters , *PREDICTION models , *ELECTRICAL engineering , *DIRECT currents - Abstract
This paper proposes a new modulated model predictive control method for the control of modular multilevel converters (MMCs) in voltage source converter-high voltage dc systems. The proposed method retains the advantages of the conventional finite control set-model predictive control methods by programing the nonlinear properties of the MMC into the design calculations while minimizing the ac line and circulating current ripples and steady-state error by generating modulated switching signals with a fixed switching frequency. In this paper, first, the predictive modeling of the MMC is provided. Next, the proposed control method is described. Then, the application of the proposed method to an MMC system is detailed. Finally, experimental results from an MMC system connected to a three-phase grid are provided to validate the theoretical outcomes. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
14. A Very High-Gain-Modular Three-Phase AC/DC Soft-Switched Converter Featuring High-Gain ZCS Output Rectifier Modules Without Using Step-Up Transformers for a DC Grid in Wind Systems.
- Author
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Abbasi, Mehdi and Lam, John
- Subjects
- *
ELECTRIC current converters , *AC DC transformers , *SWITCHING circuits , *ZERO voltage switching , *WIND energy conversion systems , *HIGH frequency transmission lines , *ELECTRIC current rectifiers , *ELECTRIC power conversion - Abstract
This paper presents a new modular ac/dc step-up soft-switched converter with unity turns ratio high-frequency transformers for medium-voltage (MV) dc grid in wind energy systems. In the proposed converter, the three-phase boost rectifier is combined with step-up resonant circuits and high-gain output rectifier modules (called voltage quadrupler modules) to form a modular step-up power conversion unit. As a result, the proposed converter is able to achieve very high voltage gain without using any medium-to-high frequency transformers with very large turns ratio, which greatly simplifies the insulation requirement and design of the high-frequency transformer. In addition, soft-switching operations are achieved in all the semiconductor devices to maintain high efficiency. The techniques to ensure voltage balancing across the dc-link capacitors and to achieve output short-circuit protection will be discussed in this paper. To realize high-frequency MV operation, silicon carbide (SiC) devices are utilized in the converter implementation on a 1.5 MW, 690 VAC/40 kV converter system to validate the performance of the proposed circuit. Experimental results on a 3.5 kW, 145 VAC/6.2 kV, 95.4% efficiency SiC-based laboratory-scale proof-of-concept prototype are then provided to highlight the merits of this work. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
15. Analysis of a New Single-Stage Soft-Switching Power-Factor-Correction LED Driver With Low DC-Bus Voltage.
- Author
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Khalilian, Hosein, Farzanehfard, Hosein, Adib, Ehsan, and Esteki, Morteza
- Subjects
- *
LIGHT emitting diodes , *ELECTRIC power factor correction , *SWITCHING circuits , *DIGITAL electronics , *ELECTRONIC circuits - Abstract
A new isolated single-stage soft-switching power-factor-correction (S4 PFC) driver for supplying light-emitting diodes (LEDs) is introduced in this paper. In the proposed LED driver, the switches voltage stress and also the dc-bus voltage is limited to the peak of the line voltage. Hence, low voltage rated
mosfet s and diodes can be used. The efficiency is improved because the switches are turnedon under zero current switching (ZCS) condition and turnedoff under zero voltage zero current switching (ZVZCS) condition. Also, no current feedback is required since the converter provides an output current independent of output voltage. In this paper, operating principle of the proposed LED driver is presented and design considerations are discussed. To verify the theoretical analysis, a laboratory prototype of the proposed converter for supplying a 50 W/70 V LED module from 220 Vrms/50 Hz ac mains is implemented, and the experimental results are presented. Since current feedback is not used, dimming property and operation for universal voltage range is not achievable. [ABSTRACT FROM PUBLISHER]- Published
- 2018
- Full Text
- View/download PDF
16. DTC of Three-Level NPC Inverter Fed Five-Phase Induction Motor Drive With Novel Neutral Point Voltage Balancing Scheme.
- Author
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Payami, Saifullah, Behera, Ranjan Kumar, and Iqbal, Atif
- Subjects
- *
ELECTRIC inverters , *INDUCTION motors , *VOLTAGE control , *TORQUE control , *CAPACITORS , *SWITCHING circuits - Abstract
In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
17. Rise-Time Improvement in Bipolar Pulse Solid-State Marx Modulators.
- Author
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Canacsinh, Hiren, Silva, J. Fernando, and Redondo, L. M.
- Subjects
- *
ELECTRONIC modulators , *CAPACITORS , *INSULATED gate bipolar transistors , *DIODES , *SWITCHING circuits - Abstract
This paper presents the effect of stray capacitances in bipolar (negative and/or positive) pulses generated by the two different topologies of the solid-state Marx modulators. According to the analysis, the stray capacitances influence the energy transfer from the Marx modulator capacitors to the load affecting the bipolar (negative and/or positive) pulse rise time. This paper deals with the structure design to reduce the influence of the stray capacitance and to improve the pulse rise time of these bipolar solid-state Marx modulators. A four-stage laboratory prototype of the two topologies has been assembled using 1200-V insulated gate bipolar transistors and diodes, operating with 1000-V dc input voltage and 1-kHz frequency, producing 4-kV bipolar pulses, with 5- \mu \texts pulse duration and 120-ns rise time, into a resistive load. [ABSTRACT FROM PUBLISHER]
- Published
- 2017
- Full Text
- View/download PDF
18. A Space Vector Pulse Width Modulation for Five-Level Nested Neutral Point Piloted Converter.
- Author
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Li, Junjie, Jiang, Jianguo, and Qiao, Shutong
- Subjects
- *
ELECTRIC current converters , *CASCADE converters , *PULSE width modulation , *PULSE modulation , *POWER capacitors - Abstract
This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
19. Compact design of high voltage switch for pulsed power applications.
- Author
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Appiah, G. N., Jang, S. R., Bae, J. S., Cho, C. G., Song, S. H., and Ryoo, H.J.
- Subjects
- *
ELECTRIC switchgear , *PULSED power switches , *ELECTRIC discharges , *SWITCHING circuits , *INSULATED gate bipolar transistors - Abstract
Generally, for pulsed power applications with low jitter and high repetition rates, the use of semiconductor switches have replaced the traditional gap switches and thyratron circuits due to the limited lifetime of the thyratron and gap switches under such operating conditions. However, the limited ratings of these semiconductor switches require series and/or parallel stacking in order to handle high voltages and current levels associated with the discharge energy. Described in this paper is the design of a high voltage switch that uses a simple and reliable gate driver circuit for pulsed power application. In this design, the switch module is made up of insulated-gate bipolar transistor (IGBTs) and their gate driver circuits compactly fitted onto a single module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier synchronization of the switches, the simultaneous transfer of both signal and power for current boost are also described in this paper. A 120 nF capacitor bank energy was discharged using a configuration of the developed high voltage switch and a developed 15 kV, 1.5 kJ/s peak power capacitor charger, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
20. A 10-Bit 200-kS/s 1.76- $\mu$ W SAR ADC With Hybrid CAP-MOS DAC for Energy-Limited Applications.
- Author
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Zhang, Hongshuai, Zhang, Hong, Song, Yan, and Zhang, Ruizhi
- Subjects
- *
SUCCESSIVE approximation analog-to-digital converters , *ELECTRIC potential , *STRUCTURE-activity relationships , *TRANSISTORS , *ENERGY consumption , *HYBRID power systems , *ANALOG-to-digital converters - Abstract
This paper presents a low-power and area efficient 10-bit successive approximation register (SAR) analog-to-digital (ADC) with a hybrid capacitive-MOS consisting of a 7-bit MSB capacitive DAC (CDAC) and a 3-bit LSB MOS DAC (MDAC), which consumes less power and much smaller chip area than a pure CDAC. Instead of using a string of eight MOS transistors to control one unit capacitor, the 3-bit LSB MDAC is realized by a MOS string with four native MOS transistors to control two unit capacitors, which allows higher voltage drop and more reliable operation for each unit MOS. The overall energy consumption of the proposed CAP-MOS DAC is reduced by 56.2% compared to a Vcm-based 10-bit pure CDAC with the same unit capacitance. Under the sampling rate of 200 kS/s, the prototype 10-bit SAR ADC implemented in a 0.18- ${\mu }\text{m}$ CMOS technology achieves a signal-to-noise-and-distortion ratio / spurious-free dynamic range of 56.91 /68.56 dB at 99-kHz input under a 0.6-V power-supply, while consumes $1.76~{\mu }\text{W}$ at 200 kS/s for a figure of merit of 15.38 fJ/step. The peak DNL and INL are +0.27/−0.21 LSB and +0.43/−0.45 LSB, respectively. The ADC occupies a small active area of 0.097 mm2. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
21. High-Performance Switched-Capacitor Boost–Buck Integrated Power Converters.
- Author
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Allasasmeh, Younis and Gregori, Stefano
- Subjects
- *
CAPACITOR switching , *CONVERTERS (Electronics) , *ENERGY conversion - Abstract
This paper presents the design of integrated boost and buck switched-capacitor power converters with high efficiency and fast start-up time. An analysis method is determined to evaluate the key performance parameters of integrated power converters, and techniques are proposed to improve the energy conversion efficiency and the dynamic response. Boost and buck structures are modeled and compared in static and transient conditions, including the losses due to parasitic elements. A switch bootstrapping technique prevents short-circuit losses, improves driving capability and start-up time, and enhances the overall efficiency. Moreover, the application of a charge-reuse technique reduces the dynamic power losses of the integrated structures. Prototypes of the integrated power converters were fabricated in a 180-nm CMOS process. Measurement results based on the proposed techniques are presented, demonstrating the improvements in steady-state and transient characteristics with a good correlation between measured and predicted results. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
22. A Dual-Output Switched Capacitor DC–DC Buck Converter Using Adaptive Time Multiplexing Technique in 65-nm CMOS.
- Author
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Kilani, Dima, Mohammad, Baker, Alhawari, Mohammad, Saleh, Hani, and Ismail, Mohammed
- Subjects
- *
COMPLEMENTARY metal oxide semiconductors , *CAPACITOR switching , *WEARABLE technology - Abstract
This paper presents an area- and power-efficient dual-output switched capacitor (DOSC) dc–dc buck converter for wearable biomedical devices. The DOSC converter has an input voltage range between 1.05 and 1.4 V and generates two simultaneous regulated output voltages of 1 and 0.55 V. The DOSC consists of two main blocks: a switched capacitor regulator and an adaptive time multiplexing (ATM) controller. The switched capacitor regulator generates a single regulated voltage using pulse frequency modulation based on a predetermined reference voltage. In addition, the ATM controller generates two simultaneous output voltages and eliminates the reverse current using pulse width modulation during the switching between the output voltages. Addressing the reverse current problem is important to reduce the output voltage droop and improve the performance. The proposed converter supports load currents of 10– $350~\mu \text{A}$ and 1– $10~\mu \text{A}$ at load voltages of 1 and 0.55 V, respectively. The DOSC circuit is fabricated in 65-nm CMOS, and it occupies an active area of 0.27 mm2. Measured results show that a peak efficiency of 78% is achieved at a load power of $300~\mu \text{W}$. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
23. Generalized Analysis of High-Order Switch-RC $N$ -Path Mixers/Filters Using the Adjoint Network.
- Author
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Pavan, Shanthi and Klumperink, Eric
- Subjects
- *
HARMONIC suppression filters , *CAPACITORS - Abstract
This paper presents a systematic method to analyze $N$ -path mixers and filters consisting of periodically switched $RC$ -networks of arbitrary order. It is assumed that each capacitor periodically exchanges charge with the rest of the network during the on-phase of the switching clock, then samples its charge, and holds it perfectly until the next on-phase. This assumption allows for using the adjoint network for simplified analysis of the harmonic transfer functions that describe the signal transfer and folding. Moreover, harmonic transfer cancellations due to the $N$ -path implementation with $N$ equal capacitors switched by $N$ non-overlapping clocks are systematically analyzed. The method is applied to a recently published $N$ -path filter-mixer combination and verified by simulations. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
24. Highly Efficient Single-Phase Buck–Boost Variable-Frequency AC–AC Converter With Inherent Commutation Capability.
- Author
-
Sharifi, Saeed, Monfared, Mohammad, Babaei, Mohammad, and Pourfaraj, Alireza
- Subjects
- *
SEMICONDUCTOR devices , *SEMICONDUCTOR switches , *WIND turbines , *HEATING , *SEMICONDUCTORS - Abstract
This paper introduces a novel single-phase buck–boost noninverting variable-frequency ac–ac converter that offers higher efficiency compared to the competitors. This converter utilizes a lower number of semiconductors. A simple and flexible switching strategy is also proposed, which generates the desired output waveform avoiding unnecessary high-frequency switching operation of semiconductor devices. A high reliable operation due to the elimination of the input source shoot-through risk, an inherent commutation capability that mitigates the voltage spikes across the semiconductors, a lower semiconductors rating requirement, an improved input current waveform quality, and a smaller required input filter inductor are the main advantages of the proposed converter. Thus, the proposed converter can be successfully applied to many industrial applications such as medium-frequency transformer isolation for traction and wind turbine converters, ac–dc high-voltage conversion based on Cockcroft–Walton circuit and induction heating systems. The theoretical achievements and claims are all confirmed through extensive experimental tests on a 200-W laboratory setup. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
25. Implementation of an Optimum Reduced Components Multicell Multilevel Inverter (MC-MLI) for Lower Standing Voltage.
- Author
-
Majumdar, Saikat, Mahato, Bidyut, and Jana, Kartick Chandra
- Subjects
- *
LOW voltage systems , *CIRCUIT complexity , *HIGH voltages , *IDEAL sources (Electric circuits) , *HARMONIC distortion (Physics) , *DC-AC converters - Abstract
Multilevel inverters (MLI) with reduced components are becoming popular to achieve higher voltage levels with lower cost and complexities of the circuit. Most of the reduced switch MLIs use a large number of isolated voltage sources that have a large total standing voltage (TSV) and higher losses. Moreover, many reduced component MLIs have been developed to reduce the number of switches only and have not utilized the dc-link voltages properly. Thus, an inverter needs to be designed in which the number of dc sources is also small and utilized fully. In this paper, a novel single-phase, multicell MLI configuration is presented that can generate a maximum number of output voltage levels using a minimum number of switches and dc sources. Two optimal configurations of the proposed MLI are proposed based on the minimum requirements of components with the optimum voltage stress of the highest rated switches. Moreover, the TSV of the proposed optimal MLI also becomes low. A generalized multicell optimum MLI is presented and the number of components, voltage stress of all the switches, and the TSV of the proposed as well as the other inverters also determined by the generalized expressions for comparison purpose. The prototype of a specimen 15-level inverter and the optimal 75-level inverter cell is further developed and implemented using DS 1103 in the laboratory to show the effectiveness of the proposed configuration. The experimental results corresponding to the different modulation indices are presented here for the verification of the simulation results. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
26. Pulsed Power Modulator With Active Pull-Down Using Diode Reverse Recovery Time.
- Author
-
Park, Su-Mi and Ryoo, Hong-Je
- Subjects
- *
PULSED power systems , *DIODES , *ION implantation , *ION sources , *PLASMA sources , *ELECTROPORATION , *HIGH-voltage direct current transmission - Abstract
This paper presents a pulsed power modulator with a new structure that utilizes the reverse recovery characteristics of diodes to achieve an effective pull-down circuit configuration. The proposed configuration for active pull-down applicable to negative pulsed power applications with a high-voltage direct switching method is implemented by adding a diode to the pulse discharging path of the modulator, instead of using a pull-down resistor. The diode is forward-biased while an output pulse voltage is applied to the load. When the pulse voltage applied to the load is removed, the residual energy in the load is quickly discharged through the reverse recovery path of the diode so that the pull-down function of the pulsed power supply system is efficiently performed. The operating principle of the proposed system is described, and each operating mode is analyzed in detail. In addition, the feasibility of the proposed system configuration is examined through various simulation results. Finally, it is proven that the proposed system can be used effectively in pulsed power application fields through a practical experiment in plasma source ion implantation applications. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
27. A Self-Adapting Synchronized-Switch Interface Circuit for Piezoelectric Energy Harvesters.
- Author
-
Chamanian, Salar, Muhtaroglu, Ali, and Kulah, Haluk
- Subjects
- *
INTERFACE circuits , *MAXIMUM power point trackers , *PIEZOELECTRIC transducers , *OPEN-circuit voltage , *EXTRACTION techniques - Abstract
This paper presents a self-adapting synchronized-switch harvesting (SA-SSH) interface circuit to extract energy from vibration-based piezoelectric energy harvesters (PEHs). The implemented circuit utilizes a novel switching technique to recycle optimum amount of harvested charge on piezoelectric capacitance to strengthen the damping force, and simultaneously achieve load-independent energy extraction with a single inductor. Charge recycling is realized by adjusting extraction time, and optimized through a maximum power point tracker based on charge-flipping dissipation. The circuit has been implemented using 180 nm HV CMOS technology with 0.9 × 0.6 mm2 active area. Self-adapting SSH circuit has been validated with both macro-scaled and MEMS PEHs with different inductor values. The interface circuit provides maximum energy extraction for the full storage voltage range of 1.8–3.7 V. The implementation harnesses have 500% more power compared to an ideal full-bridge rectifier, and output 3.4 μW for 2.24 V peak-to-peak open-circuit piezoelectric voltage from MEMS PEH excited at its resonant frequency. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
28. Nonisolated Multiport Converters Based on Integration of PWM Converter and Phase-Shift-Switched Capacitor Converter.
- Author
-
Sato, Yusuke, Uno, Masatoshi, and Nagata, Hikaru
- Subjects
- *
CASCADE converters , *PULSE width modulation transformers , *PULSE width modulation inverters , *ZERO voltage switching , *CAPACITOR switching , *CAPACITORS , *BATTERY storage plants , *PULSE width modulation - Abstract
Photovoltaic (PV) systems having rechargeable batteries are prone to be complex and costly because multiple converters are necessary to individually regulate a load, PV panel, and battery. This paper proposes novel nonisolated multiport converters (MPCs) integrating a bidirectional pulsewidth modulation (PWM) converter and phase-shift-switched capacitor converter (PS-SCC) for standalone PV systems. A PWM converter and PS-SCC are integrated by reducing the total switch count, realizing the simplified system and circuit. In the proposed MPCs, two control freedoms of duty cycle and phase shift angle are manipulated to individually regulate the load, PV panel, and/or battery. The detailed operation analysis was performed to mathematically derive gain characteristics and zero voltage switching operation boundaries. For the battery discharging mode, in which the PV panel is not available and the MPC behaves as a single-input–single-output converter with two control freedoms available, the optimized control scheme achieving the lowest rms current is also proposed to maximize power conversion efficiencies. Various kinds of experimental verification tests using a 200-W prototype were performed to verify the theoretical analysis and to demonstrate the performance of the proposed MPC. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
29. A New Triple-Switch-Triple-Mode High Step-Up Converter With Wide Range of Duty Cycle for DC Microgrid Applications.
- Author
-
Bhaskar, Mahajan Sagar, Alammari, Rashid, Meraj, Mohammad, Padmanaban, Sanjeevikumar, and Iqbal, Atif
- Subjects
- *
CAPACITOR switching , *HIGH voltages , *SEMICONDUCTOR devices , *DUTY , *PHOTOVOLTAIC cells , *FUEL cells - Abstract
DC microgrid is gaining attraction and a recent trend in distribution power generation system due to penetration of renewables (especially photovoltaic or fuel cell). In this paper, a new triple-switch-triple-mode high step-up converter (TSTM-HS converter) is presented for dc microgrid applications. In the proposed converter, voltage lift technique is employed and range of duty cycle is extended by incorporating an additional switch in converter circuitry. By doing this, high voltage conversion ratio is achieved without using a transformer, coupled inductor, and multiple stages of switched capacitors. Moreover, the TSTM-HS converter operated in three modes with two types of the duty cycles to achieve low to high voltage conversion without using high duty cycle for each switch. The effects of difference in the inductance values on the regulation and operating behavior of the TSTM-HS converter are discussed. The continuous conduction mode and discontinuous conduction mode characteristics of the TSTM-HS converter are discussed in detail with steady-state analysis and boundary condition. The comparison is provided to highlight the benefits of the TSTM-HS converter. The selection of semiconductor devices and the design of reactive components are discussed for the TSTM-HS converter. The experimental results of the proposed converter are provided which validate the theoretical approach, performance, and feasibility of converter. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
30. Reduced Switch Cascaded Multilevel Inverter With New Selective Harmonic Elimination Control for Standalone Renewable Energy System.
- Author
-
Panda, Kaibalya Prasad, Lee, Sze Sing, and Panda, Gayadhar
- Subjects
- *
ELECTRIC inverters , *ELECTRON tube grids , *LINE drivers (Integrated circuits) , *MATHEMATICAL optimization , *SWITCHING circuits , *TOPOLOGY , *HARMONIC analysis (Mathematics) - Abstract
Recently multilevel inverters (MLIs) have received wide attention from industry and academia, as they are changing into a viable technology for diverse applications. To produce high-quality output using less switch count, development of novel reduced switch MLI (RS MLI) topologies has been a focus of current research theme. This paper presents design and control of a switched-diode dual source single switch MLI (SDDS MLI). The generalized SDDS MLI is first designed using an asymmetric basic unit. Proposed SDDS MLI requires less switch count and driver circuit count compared with the few recently developed RS MLI topologies. To improve the voltage quality by eliminating targeted low-order harmonics, a modified version of fish swarm optimization algorithm is examined for computing optimum switching angles required to control the SDDS MLI. Moreover, suitability and superiority of the derived algorithm are established by comparing with traditional selective harmonic elimination techniques. The developed topology is investigated through several MATLAB simulations as well as experimental tests in the laboratory applying the modified control approach. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
31. Highly Efficient Bridgeless Dual-Mode Resonant Single Power-Conversion AC–DC Converter.
- Author
-
Kim, Sooa, Kwon, Bong-Hwan, and Kim, Minsung
- Subjects
- *
ZERO current switching , *ELECTRIC current rectifiers , *AC DC transformers , *SWITCHING circuits , *VOLTAGE control , *DIODES , *RESISTOR-inductor-capacitor circuits - Abstract
This paper presents a bridgeless dual-mode single power-conversion ac–dc converter that can achieve a high conversion efficiency. By adopting a bidirectional switch, we remove a full-bridge diode rectifier from the grid side of the proposed converter, and thereby, reduce the number of components and the primary-side conduction loss. To adapt the converter to 1-kW power applications with a bidirectional switch, we used a series-resonant circuit in the output voltage doubler on the secondary side. The series-resonant circuit also provides zero-current switching turn-off at the output diode, and thereby, reduces the reverse-recovery loss. To attain medium–high power capability with an appropriate transformer, the proposed converter operates in both discontinuous conduction mode and continuous conduction mode. The operation principle of the converter is presented and analyzed. By using the dual-mode control algorithm, the proposed converter achieves a high power factor of 0.994 and maximum efficiency of 97.3 $\%$. Experimental results for a prototype 1-kW ac–dc converter verify these characteristics. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
32. Design of Trigger Circuit for High-Power Gas Switch Based on Flyback Circuit.
- Author
-
Kim, Shin, Bae, Jung-Soo, Kim, Hyoung-Suk, Yu, Chan-Hun, Lee, Byung-Joon, Ahn, Suk-Ho, and Jang, Sung-Roc
- Subjects
- *
ENERGY storage , *THYRISTORS , *GASES , *SWITCHING circuits , *LOGIC circuits , *POWER resources , *ELECTRIC transformers , *PULSE generators - Abstract
This paper proposes a flyback-circuit-based design of a trigger circuit for a high-power gas switch. By incorporating a flyback circuit in a high-power gas switch, it is possible to generate a high step-up ratio and high-voltage pulse by using a transformer. Furthermore, simple trigger circuit having the minimum possible number of components (transformer and switch) can be realized. When an inductor is used as an energy storage element, energy is stored as a current source, and thus, the element can operate reliably when low impedance exists between the trigger node of the switch after triggering. According to the fundamental operating principle of a flyback circuit, the proposed trigger circuit is designed considering the maximum trigger voltage and energy required for a high-power gas switch. To verify the proposed design procedure and feasibility of the trigger circuit, a compact trigger circuit (7.5 kV, 1.3 mJ/pulse) is simulated using the PSpice program and implemented. Based on this compact circuit, a trigger circuit (20 kV, 100 mJ/pulse) for a triggered vacuum switch (TVS) is developed, and the tests with an actual TVS (3.3 kJ) are carried out. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
33. Voltage-Source Parallel Resonant Class E Inverter.
- Author
-
Shigeno, Akinobu and Koizumi, Hirotaka
- Subjects
- *
ZERO voltage switching , *WIRELESS power transmission , *ELECTRIC inverters , *SWITCHING circuits , *CAPACITORS , *RESONANT inverters - Abstract
This paper proposes a voltage-source parallel resonant Class E inverter. The proposed circuit has a shunt capacitor including parasitic capacitance of a switching device and achieves zero-voltage switching and zero-voltage derivative switching at turning-on like a classical Class E inverter. Therefore, high power conversion efficiency is achieved under high operating frequency. Unlike the other Class E inverters, the proposed circuit has no choke inductor or dc blocking capacitor. Moreover, it has a parallel resonant tank unlike the classical Class E inverter. Thus, a circuit protection is not required in a wireless power transfer system. Circuit analysis, circuit simulations, and circuit experiments were carried out. The experimental circuit performed the desired operation and the power conversion efficiency was 93.2% with the output power 4.76 W at the operating frequency 1 MHz. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
34. Using Short-Circuit Programs to Simulate Basic Capacitor Switching Transients.
- Author
-
Tian, Yu, Xu, Wilsun, and Yong, Jing
- Subjects
- *
CAPACITOR switching , *ELECTRIC transients , *ELECTROMAGNETIC devices , *SHORT-circuit currents , *OVERVOLTAGE - Abstract
Switching of shunt capacitors can cause transient overvoltage. The voltages are traditionally evaluated with electromagnetic transients (EMT) simulation programs. It is a very time-consuming process mainly due to the need to convert a power-flow (or short-circuit) case to the EMT case. This paper proposes an idea to conduct capacitor switching studies directly inside commercial power-flow/short-circuit tools such as PSS/E, thus avoiding the data-conversion process. The idea is to conduct switching studies in the frequency domain. The frequency response of the study network is determined using the short-circuit solution engine of the host commercial software. This paper presents the theory, unique issues, and implementation details of the idea. The effectiveness of the proposed method is verified by comparing the results with those of the EMT simulations. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
35. Decoding and Synthesizing Transformerless PWM Converters.
- Author
-
Wu, Tsai-Fu
- Subjects
- *
PULSE width modulation , *CONVERTERS (Electronics) , *ELECTRIC inductors , *ELECTRIC inverters , *ZETA potential , *SWITCHING circuits - Abstract
Pulse-width-modulated (PWM) converters have been widely applied for power processing, and they are typically the stems of other types of converters, such as quasi-resonant, Z-source, and switched-inductor hybrid converters. Development of PWM converters has been spanning over a century, starting from the buck converter. The well-known PWM converters include buck, boost, buck–boost, Ćuk, single ended primary inductive converter (SEPIC), zeta, Z-source, quasi-Z source, etc. Many attempts have been proposed to develop these converters based mostly on canonical cell concepts and by introducing extra LC filters to the cells. This paper presents an enhancement to the layer and graft schemes by introducing the ideas of dc voltage/current offsetting, capacitor/inductor component splitting, diode grafting, and inverse operation of PWM converters. The PWM converters, which can be operated in continuous conduction mode (CCM) or discontinuous conduction mode (DCM), therefore can be synthesized systematically according to decoded transfer gains. Decoding and synthesizing PWM converters uniquely bridge transfer gains to converter topologies and provide readers a comprehensive understanding of PWM-converter evolution from the original converter, the buck converter. Additionally, in this paper, the Ćuk, SEPIC, and zeta converters all with the same transfer gain of $D/(1 - D)$ are proved to be equivalent to the buck–boost converter with an extra LC filter. For further illustrating the proposed approaches, various types of Z-source converters, switched-capacitor/switched-inductor hybrid converters, and a single-stage interleaved converter are reviewed, and new PWM converters are developed. [ABSTRACT FROM AUTHOR]
- Published
- 2016
- Full Text
- View/download PDF
36. An Efficient Self-Powered Piezoelectric Energy Harvesting CMOS Interface Circuit Based on Synchronous Charge Extraction Technique.
- Author
-
Shi, Ge, Xia, Yinshui, Wang, Xiudeng, Qian, Libo, Ye, Yidie, and Li, Qing
- Subjects
- *
ENERGY harvesting , *PIEZOELECTRIC device design & construction , *INTEGRATED circuits , *ELECTROMAGNETIC waves , *WIRELESS sensor networks , *EQUIPMENT & supplies - Abstract
An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
37. Design and Analysis of Energy-Efficient Single-Pulse Piezoelectric Energy Harvester and Power Management IC for Battery-Free Wireless Remote Switch Applications.
- Author
-
Lee, Minbok, Yang, Joonseok, Park, Myeong-Jae, Jung, Sung-Youb, and Kim, Jaeha
- Subjects
- *
ENERGY harvesting , *PIEZOELECTRIC devices , *WIRELESS communications , *EQUIPMENT & supplies - Abstract
This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
38. A 0.55-V, 28-ppm/°C, 83-nW CMOS Sub-BGR With UltraLow Power Curvature Compensation.
- Author
-
Liu, Lianxi, Mu, Junchao, and Zhu, Zhangming
- Subjects
- *
CMOS memory circuits , *THRESHOLD voltage , *CAPACITORS - Abstract
This paper proposes an ultralow power, high precision sub bandgap voltage reference (sub-BGR) for low-voltage self-powered devices. A novel ultralow power curvature compensation circuit is proposed to improve the temperature coefficient over a wide temperature range. A switch capacitor voltage divider with improved leakage current reduction switches is used to obtain a high accuracy and a low power. To minimize the clock feedthrough and charge injection in the switches, a clock scaling down circuit is proposed, that effectively improves the line sensitivity (LS) of the sub-BGR. The proposed sub-BGR is implemented in a 0.18- \mu \textm standard CMOS process with a total area of 0.061 mm2. After measuring 30 chips, the average power consumption is 83 nW at 0.55 V of supply at 27 °C. In the supply voltage range of 0.55 to 1 V, the LS is 0.059%/V, and the error is ±0.75% ( $3\sigma $ ) after trimming. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
39. An 11-Bit 250-nW 10-kS/s SAR ADC With Doubled Input Range for Biomedical Applications.
- Author
-
Sadollahi, Mahmoud, Hamashita, Koichi, Sobue, Kazuki, and Temes, Gabor C.
- Subjects
- *
SUCCESSIVE approximation analog-to-digital converters , *BIOMEDICAL materials , *SWITCHING circuits - Abstract
This paper presents a low-power, area-efficient 11-b single-ended successive-approximation-register (SAR) analog-to-digital converter (ADC) targeted for biomedical applications. The design features an energy-efficient switching technique with an error cancelling capacitor network. The input range is twice the reference voltage. The ADC’s loading of the previous stage is reduced by using a single-ended structure, and by eliminating the largest capacitor in the array. The common mode voltage of the input signal can be used as reference voltage. All building blocks were designed in subthreshold for power efficiency, with an asynchronous self-controlled SAR logic. The ADC was fabricated in 0.18 – \mu \textm CMOS 2P4M process. The measured peak SNDR was 60.5 dB, the SFDR was 72 dB, the DNL +0.6/−0.37 LSB, and the INL +0.94/−0.89 LSB. The total power consumption was 250 nW from 0.75-V supply voltage. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
40. A Single-Phase Three-Level Flying-Capacitor PFC Rectifier Without Electrolytic Capacitors.
- Author
-
Qi, Wenlong, Li, Sinan, Tan, Siew-Chong, and Hui, S. Y.
- Subjects
- *
ELECTROLYTIC capacitors , *ELECTRONIC circuits , *CORRECTION factors , *ELECTRIC inductance , *SWITCHING circuits , *MAGNETICS - Abstract
A component-minimized and low-voltage-stress single-phase power factor correction rectifier without electrolytic capacitor is proposed in this paper. Component minimization is achieved by embedding an active pulsating-power-buffering (PPB) function within each switching period, such that typical add-on power electronic circuits for PPB are no longer needed. Additionally, with a three-level flying-capacitor configuration, the voltage stresses of switching devices can be reduced more than 50% as compared to existing solutions that are based on embedded PPB. The relationship between the inductance requirement and the patterns of the modulation carriers, and how it can be utilized to minimize the magnetics of the rectifier, is also discussed. A 110 W hardware prototype is designed and tested to demonstrate the feasibilities of the proposed rectifier. An input power factor of more than 0.97, peak efficiency of 95.1%, and an output voltage ripple of less than 4.3% across a wide load range have been experimentally obtained. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
41. Optimal Design Method of Interleaved Boost PFC for Improving Efficiency from Switching Frequency, Boost Inductor, and Output Voltage.
- Author
-
Xu, Hengshan, Chen, Diyi, Xue, Fei, and Li, Xutao
- Subjects
- *
MAGNETIC flux density , *ELECTRIC power factor , *DC-to-DC converters , *ELECTRIC potential , *SWITCHING circuits , *AC DC transformers , *CORRECTION factors , *ELECTRONIC equipment - Abstract
Many research works have been conducted on increasing the efficiency of interleaved boost converters (IBCs) applied for power factor correction (PFC) by using high-performance power electronic devices and soft switching circuits, which are not helpful in reducing the hardware cost and systematic complexity. In this paper, three intrinsic parameters affecting the efficiency of IBC PFC are found and analyzed, including the switching frequency value, boost inductor value, and output voltage value. Based on the findings, considering the limitations of current ripples, power factor, maximum magnetic flux density, and volume of a boost inductor, an optimization design method for high-efficiency IBC PFC is proposed. A 3.3-kW IBC PFC prototype is developed based on Si devices. The experimental result verifies that the proposed method can improve the efficiency of IBC PFC with low-cost low-performance devices in the full-load range. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
42. Optimization of Self-Breakdown and Triggering Characteristics on Multigap Gas Switch by Mounting Resistors and Capacitors in Parallel With Switch Gaps.
- Author
-
Jiang, Hongyu, Sun, Fengju, Cong, Peitian, Wang, Zhiguo, Jiang, Xiaofeng, Yin, Jiahui, Huang, Tao, Luo, Weixi, Zhang, Tianyang, and Zhai, Rongxiao
- Subjects
- *
CAPACITOR switching , *ELECTRIC resistors , *ELECTRIC breakdown , *GASES , *STANDARD deviations , *RANDOM access memory , *SWITCHING circuits , *ELECTRIC potential - Abstract
The multigap gas switch has been widely used in liner transformer drivers (LTDs), but there is still room for improvement on its self-breakdown and triggering characteristics. In this paper, based on the circuit model of the six-gap gas switch, the gap voltage distribution during the charging and triggering process is analyzed, and the optimization on self-breakdown and triggering characteristics by mounting resistors and capacitors in parallel with switch gaps are theoretically and experimentally investigated. The results indicate that compared with the original switch, when the self-breakdown voltage is about ±90 kV, the standard deviation is reduced from 7.5 to less than 3 kV; for a charging voltage of ±80 kV and by operating at 60% working coefficient, when the negative trigger voltage is 75 kV, the jitter of the switch is reduced from 6.1 to 1.4 ns. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
43. A Single Switch Quadratic Boost High Step Up DC–DC Converter.
- Author
-
Wang, Yijie, Qiu, Yuping, Bian, Qing, Guan, Yueshi, and Xu, Dianguo
- Subjects
- *
CONVERTERS (Electronics) , *ZERO current switching , *SWITCHING circuits , *DIODES , *MATHEMATICAL analysis - Abstract
In this paper, a high step up converter consisting of an integrated quadratic-boost converter and a voltage doubler is proposed. The integration of the quadratic-boost converter makes the system easier to lift up its voltage gain through slightly increasing the duty ratio of the single switch. The voltage doubler further increases the voltage gain of the system as the turn ratio rises. The voltage stresses on the switch and the diodes are decreased for such cascaded topology. Different operation modes are analyzed and mathematical analysis of the converter is presented in detail. The leakage inductance contributes to realizing zero current switching of the diodes in the second boost stage and the doubler and the energy can be recycled to the load. A 38-W prototype is built to work as a vehicle LED driver. Experiments are conducted to verify the advantages of the proposed converter and the efficiency is 90% at the nominal operating point. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
44. Minimum Active Switch Requirements for Single-Phase PFC Rectifiers Without Electrolytic Capacitors.
- Author
-
Li, Sinan, Qi, Wenlong, Wu, Jiayang, Tan, Siew-Chong, and Hui, Shu-Yuen
- Subjects
- *
ELECTRIC current rectifiers , *ELECTROLYTIC capacitors , *SEMICONDUCTOR switches , *ENERGY storage , *SWITCHING circuits , *TECHNICAL specifications - Abstract
Active pulsating power buffering (PPB) function can effectively reduce the twice-line frequency energy storage requirement in a single-phase rectifier. Existing single-phase solutions with active PPB must utilize more than two active switches in their circuits. Compared with conventional single-active-switch solutions without active PPB (e.g., a boost power-factor-correction (PFC) rectifier), the cost of additional semiconductor switches and gate drive circuitry in an active PPB-based rectifier may not be justified for low-power applications. This paper presents a family of single-switch single-phase rectifier with active PPB. Taking advantage of the on-time and off-time of a single switch, the proposed rectifiers are formulated by merging two converters that are duty and frequency controlled. The steady-state characteristics of these converters are analyzed. A step-by-step design procedure is provided, and an active control method for limiting the maximum switching frequency for wide-load-range operation is presented. A 100-W prototype is built for the demonstration of the proposed single-switch rectifier concept. It is envisaged that this concept, when combined with other circuit formulation techniques, e.g., partial power processing, dc-voltage feedback, may lead to new derivatives of single-switch rectifiers with more advanced features. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
45. A Modified SEPIC-Based High Step-Up DC–DC Converter With Quasi-Resonant Operation for Renewable Energy Applications.
- Author
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Hasanpour, Sara, Baghramian, Alfred, and Mojallali, Hamed
- Subjects
- *
SWITCHING circuits , *DC-to-DC converters , *RENEWABLE energy sources , *CONVERTERS (Electronics) , *LEAKAGE inductance , *STEADY-state responses , *EQUATIONS - Abstract
In this paper, a new modified single-switch single-ended primary inductor converter (MS2-SEPIC)-based high step-up dc–dc converter is presented. The proposed topology uses the coupled-inductor (CL) technique and a voltage tripler rectifier, which results in a high voltage gain for the converter. Here, the switching loss has been reduced significantly owing to the quasi-resonance operation of the circuit created by the leakage inductance of the CL along with circuit capacitors. The operational principles and steady-state analysis are discussed. Experimental results based on a 100 W laboratory prototype verify the validity of theoretical analysis. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
46. Experimental Design of Fixed Switching Frequency Model Predictive Control for Sensorless Five-Level Packed U-Cell Inverter.
- Author
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Sebaaly, Fadia, Vahedi, Hani, Kanaan, Hadi Y., and Al-Haddad, Kamal
- Subjects
- *
PREDICTIVE control systems , *SWITCHING circuits , *FREQUENCY changers , *ELECTRIC inverters , *VOLTAGE control , *MATHEMATICAL optimization - Abstract
In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
47. Family of Multiport Switched-Capacitor Multilevel Inverters for High-Frequency AC Power Distribution.
- Author
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Raman, S. Raghu, Fong, Yat Chi, Ye, Yuanmao, and Eric Cheng, Ka Wai
- Subjects
- *
CAPACITOR switching , *HARMONIC distortion (Physics) , *ENERGY crops , *IDEAL sources (Electric circuits) , *FAMILIES , *CAPACITORS , *ELECTRIC vehicles - Abstract
This paper proposes a family of multiport switched-capacitor multilevel inverter (SCMLI) topologies for high-frequency ac power distribution. It employs asymmetric dc voltage sources with a common ground that makes it ideal to be employed in renewable energy farms and modern electric vehicles. The proposed family of step-up SCMLI attains higher number of output voltage steps with optimum component count in comparison to several existing topologies. The problem of capacitor voltage balancing is solved as the capacitors are inherently charged to a finite voltage every half cycle. In-depth study on two staircase modulation strategies, namely, selective harmonic elimination and minimum total harmonic distortion (THD) scheme is presented with study on the variation of switching angles and THD with modulation indices under both schemes. Working principle and analysis are presented for the proposed family of topologies. Simulation outcomes are validated with experimental results under both the aforementioned modulation schemes with equal and unequal output voltage waveform steps. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
48. A Multicell Cascaded High-Frequency Link Inverter With Soft Switching and Isolation.
- Author
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Moosavi, Morteza and Toliyat, Hamid A.
- Subjects
- *
HIGH frequency transformers , *ELECTRIC inverters , *SWITCHING circuits , *VOLTAGE-frequency converters , *ELECTRIC windings , *CLAMPS (Engineering) - Abstract
Soft-switching inverters can achieve high efficiencies and low switchdv/dtanddi/dt, but often impose additional stress on the switches due to their resonant behavior. Multicell converters, on the other hand, can process high voltages by arranging the switches to share the stress. This paper proposes a buck–boost multicell soft-switching inverter with inherent cell voltage balancing. Both the current and voltage stresses are shared by the cells. Soft-switching conditions are achieved for all switching transitions without any need for auxiliary circuitry or clamps. A multiple-winding transformer transfers energy between the terminals and provides galvanic isolation. An analytical study and experimental results on a 1200-W prototype verify the operation of the inverter. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
49. A Dual-Input High Step-Up DC/DC Converter With ZVT Auxiliary Circuit.
- Author
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Zhu, Binxin, Zeng, Qingdian, Chen, Yao, Zhao, Yuhui, and Liu, Song
- Subjects
- *
CASCADE converters , *ZERO voltage switching , *PHOTOVOLTAIC power systems - Abstract
A dual-input high step-up DC/DC converter with zero voltage turn-off (ZVT) auxiliary circuit is presented in this paper. The cost of whole photovoltaic (PV) power could be decreased significantly by the proposed converter because it allows two PV panels to be connected at the same time. ZVT auxiliary circuit provides soft switching in a wide range of load variations with six passive components. Turn-off switching losses could be decreased and the efficiency of the whole converter could be improved. In , the operation principle and performance characteristics of the proposed converter have been analyzed and an 800 W experimental prototype has been built to validate the analytical results in. In , a dual-input maximum power point tracking (DMPPT) control algorithm has been designed for the proposed converter. Experimental results show that two PV panels can achieve the maximum power output state separately by the proposed DMPPT control algorithm. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
50. An Adaptable Interface Circuit With Multistage Energy Extraction for Low-Power Piezoelectric Energy Harvesting MEMS.
- Author
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Chamanian, Salar, Ulusan, Hasan, Koyuncuoglu, Aziz, Muhtaroglu, Ali, and Kulah, Haluk
- Subjects
- *
INTERFACES (Physical sciences) , *PIEZOELECTRICITY , *MICROELECTROMECHANICAL systems , *VIBRATION (Mechanics) , *OPEN-circuit voltage - Abstract
This paper presents a self-powered interface circuit to extract energy from ambient vibrations for powering up microelectronic devices. The circuit interfaces a piezoelectric energy harvesting micro electro-mechanical systems (MEMS) device to scavenge acoustic energy. Synchronous electric charge extraction (SECE) technique is deployed through the implementation of a novel multistage energy extraction (MSEE) circuit in 180 nm HV CMOS technology to harvest and store energy. The circuit is optimized to operate with minimum power losses when input power is limited, and adapts well to operating conditions with higher input power. The highly accurate peak detector was validated for a wide piezoelectric frequency range from 20 Hz to 4 kHz. A charging efficiency of about 84% has been achieved for 4.75 V open-circuit piezoelectric voltage excited at 390 Hz input vibration under nominal input power range of 30–80 μW. Power optimizations enable the circuit to maintain a conversion efficiency of 47% at input power level as low as 3.12 μW. MSEE provides up to 15% efficiency improvement compared to traditional SECE, and maintains power efficiency as high as possible for a wide input power range. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
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