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In this paper, a simple yet effective network pruning framework is proposed to simultaneously address the problems of pruning indicator, pruning ratio, and efficiency constraint. This paper argues that the pruning decision should depend on the convolutional weights, and thus proposes novel weight-dependent gates (W-Gates) to learn the information from filter weights and obtain binary gates to prune or keep the filters automatically. To prune the network under efficiency constraints, a switchable Efficiency Module is constructed to predict the hardware latency or FLOPs of candidate pruned networks. Combined with the proposed Efficiency Module, W-Gates can perform filter pruning in an efficiency-aware manner and achieve a compact network with a better accuracy-efficiency trade-off. We have demonstrated the effectiveness of the proposed method on ResNet34, ResNet50, and MobileNet V2, respectively achieving up to 1.33/1.28/1.1 higher Top-1 accuracy with lower hardware latency on ImageNet. Compared with state-of-the-art methods, W-Gates also achieves superior performance. [ABSTRACT FROM AUTHOR]

In recent years, very high frequency (VHF) converter has attracted much attention. However, with rich parasitic parameters and complex resonance links, there are some great difficulties to the modeling of such systems. Taking the on-off controlled VHF resonant boost converter as an example, this paper presents an accurate modeling and analysis method that considers multiple parasitic parameters. First, the closed-loop VHF converter system is divided into a main network and a parasitic oscillation network. Then, based on the operation analysis, an equivalent circuit model characterized by a time-varying input voltage source and two variable duty-cycle controlled switches is proposed. It worth noting that both the time-varying input and the controlled switches take into account the influences of the parameters. Furthermore, the periodic approximate analytical solution of the output voltage in the on stage is obtained by using the equivalent small parameter method to the proposed circuit model. And then combining the solution of the parasitic oscillation network and on-off state switching conditions, the steady-state waveform of output voltage can be obtained quickly. Finally, a prototype with operating frequency of 21.44 MHz is built to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Emerging device-based digital processing-in-memory (PIM) architectures have been actively studied due to their energy and area efficiency derived from analog to digital converter (ADC)-less PIM hardware. However, digital PIM architectures generally need large extra memories to copy parameters, and they also suffer from low computation per memory-cycle efficiencies. In this paper, we present a novel spin-orbit torque magnetic random access memory (SOT-MRAM) based digital PIM architecture to alleviate the extra memory size burden and computation cycle issues. First, we propose the spintronics-assisted logic-in-memory (SLIM) cells to support efficient digital logic operations inside memories, where the voltage-controlled magnetic anisotropy (VCMA) is exploited to enhance the computation per memory-cycle efficiencies. In addition, crossed input source PIM (CRISP) architecture is proposed to extend the merits of SLIM cells by eliminating the extra memories for parameter copying while significantly improving the degree of parallel processing. An intra-memory pipelining scheme is also considered to further increase the throughput of CRISP. The proposed CRISP architecture has been implemented using 28 nm CMOS process, and it presents 1.10 TOPS/W and 0.95 TOPS/mm2, showing considerable improvements of energy efficiency and throughput per area, compared to the state-of-the-art digital PIM architecture. Finally, to evaluate the impact of computation errors induced from the SOT devices and circuits in CRISP architecture, classification accuracy simulations have been performed while applying computation errors. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

The emergence of applications which require high-voltage switches has created a tendency to use semiconductor device series stacks. These series stacks permit operation at blocking voltages above semiconductor elements’ nominal voltage. Insulated-gate bipolar transistors (IGBT) are currently utilized for controllability and switching speed, when these topologies are employed. The main challenge therewith is guaranteeing voltage balance between IGBTs, both when blocked and when switching transistors. Most of the methods which have been proposed to mitigate static and dynamic voltage unbalances increase transistor losses. The series stack loss-less high voltage switch (LHVS) which mitigates voltage unbalances, thus reducing switching losses, is presented in this paper. LHVS consists of a circuit, which ensures soft IGBT switching, an energy recovery circuit, and a gate delay compensation circuit. Additionally, the insulation voltage level is guaranteed to be equal between control circuit and high-voltage side of each IGBT. The operating principle of the LHVS is detailed in this paper, as is experimental validation which has been performed for three series stack modules. Static unbalances are reduced to 1%, while the differences between collector–emitter voltage curves in switching “on” do not surpass 8 ns, and switching losses are reduced by 41%, as compared to the hard-switching topology. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel insulated gate bipolar transistor (IGBT) behavioral model on the field programmable gate array (FPGA), which is suitable for the real-time simulation of fast transients in power electronics circuits. In this model, the static and dynamic behaviors of the IGBT switch are described and modeled separately. The static IGBT model is represented by the saturation region of output characteristic and is a part of the circuit network model. The dynamic IGBT model is combined with the static one to describe the fast switching transient behaviors by using the IGBT equivalent circuit model. The presented dynamic model in this paper does not involve any iterative solving algorithm and can be designed with highly pipelined structures on FPGA. Therefore, the IGBT switching transient waveforms can be generated precisely with a 5 ns resolution. The proposed model is tested with two cases—a four-phase floating interleaved boost converter and a three-phase five-level modular multilevel converter. The effectiveness and accuracy of the model are validated by comparing the real-time simulation results with offline simulation software. [ABSTRACT FROM AUTHOR]

The higher voltage blocking capability and faster switching speed of silicon-carbide (SiC) mosfets have the potential to replace Si insulated gate bipolar transistors (IGBTs) in medium-/low-voltage and high-power applications. In this paper, a state-of-the-art commercially available 325 A, 1700 V SiC mosfet module has been fully characterized under various load currents, bus voltages, and gate resistors to reveal their switching capability. Meanwhile, Si IGBT modules with similar power ratings are also tested under the same conditions. From the test results, several interesting points have been obtained: different to the Si IGBT module, the over-shoot current of the SiC mosfet module increases linearly with the increase of the load current and it has been explained by a model of the over-shoot current proposed in this paper; the induced negative gate voltage due to the complementary device turn-off (crosstalk effect) is more harmful to the SiC mosfet module than the induced positive gate voltage during turn-on when the gate off-voltage is –6 V; the maximum dv/dt and di/dt (electromagnetic interference) during switching transients of the SiC mosfet module are close to those of the Si IGBT module when the gate resistance is larger than 8 Ω but the switching loss of the SiC mosfet module is much smaller; the switching losses of the Si IGBT module are greater than those of the SiC mosfet module even when the gate resistance of the former is reduced to zero. An accurate power loss model, which is suitable for a three-phase two-level converter based on SiC mosfet modules considering the power loss of the parasitic capacitance, has been presented and verified in this paper. From the model, a 96.2% efficiency can be achieved at the switching frequency of 80 kHz and the power of 100 kW. [ABSTRACT FROM AUTHOR]

The hybrid switch concept of paralleling a higher-current main Si IGBT and a lower-current auxiliary SiC mosfet offers an improved cost/performance tradeoff in power converters. Currently, the gate control strategy of these two internal devices emphasizes on minimizing the total power loss, and is referred to as the efficiency control mode in this paper. However, there is a serious risk of overheating and reliability degradation of the SiC mosfet if solely relying on this control strategy. In this paper, we propose a new method of gate control optimization, referred to as the thermal balance control mode, to keep the junction temperature of both devices within the specified temperature range, and to minimize the total power loss simultaneously. We first investigate the dependency of the hybrid switch switching losses on the gate control pattern both theoretically and experimentally. We then extensively study control optimization in these two distinct control modes in a dc–dc boost converter. It is found that the thermal balance control mode can achieve almost the same total power loss as the efficiency control mode, but much lower and more balanced junction temperatures of the two internal devices. Experimental results demonstrate that the Si/SiC hybrid switch in an optimal thermal balance control mode can achieve a 163% higher power handling capability in the 20-kHz boost converter or four times higher switching frequency in the 4-kW boost converter than a single IGBT solution with hard switching condition, and yet a considerably lower component cost than a single SiC mosfet solution in the boost converter. [ABSTRACT FROM AUTHOR]

Gallium-nitride-field-effect transistors (GaN-FETs) are promising switching devices with fast switching capability. However, they commonly have low gate threshold voltage, suffering from susceptibility to the false triggering. Particularly, the oscillatory false triggering, i.e., a self-sustaining repetitive false triggering, can occur after a fast switching, which is a severe obstacle for industrial applications. The purpose of this paper is to elucidate the design instruction for preventing this phenomenon. The oscillatory false triggering is known to be caused by the parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance and the parasitic inductance of the wiring. This paper analyzed the nonoscillatory condition of this oscillator. The result revealed an appropriate ratio between the gate-drain capacitance and the common-source inductance is a key to prevent the oscillatory false triggering. Experiment successfully verified this analysis result, supporting the effectiveness of the appropriate design of this ratio for preventing the oscillatory false triggering. [ABSTRACT FROM AUTHOR]

Superjunction MOSFETs in cascode configuration with low-voltage silicon MOSFETs are evaluated in this paper. The proposed structure combines the good switching performance provided by the cascode configuration with the benefits of the silicon technology such as its robustness, maturity, and low cost. This paper aims to explain and to demonstrate the reduction of switching losses of superjunction MOSFETs in cascode configuration with respect to their standalone counterparts (directly driven). A detailed simulation analysis of power loss contributions is carried out under hard-switching operation. Moreover, experimental evidence is provided using a boost converter (100–400 V) operating in continuous conduction mode for different switching frequencies (100–400 kHz) and output power levels (180–500 W). [ABSTRACT FROM AUTHOR]

Wide bandgap (WBG) devices offer the advantages of high frequency, high efficiency, and high power density to power converters due to their excellent performance. However, their low parasitic capacitance and fast switching speed also make them more susceptible to switching oscillations. The switching oscillations can cause voltage and current overshoots, shoot-through, electromagnetic interference, additional power loss, and even device damage, which can seriously affect the performance of power converters and systems. However, a comprehensive and in-depth overview is lacking on this topic. This article reviews the types, the causes and negative effects, the effects of parasitic parameters and suppression methods of these switching oscillations, which is helpful for practical engineering. First, the switching oscillations are divided into different types, and their causes and negative effects are reviewed. Then, the effects of different parasitic parameters on the switching oscillations are overviewed. It is found that due to the different physical structures of silicon carbide metal-oxide-semiconductor field-effect transistors, enhancement-mode gallium nitride high-electron mobility transistors (eGaN HEMTs), and cascode GaN HEMTs, the effects are also different. Finally, the main methods of suppressing the switching oscillations are summarized, and the advantages and disadvantages of these methods are presented. Furthermore, future research works on this topic and the conclusion of this paper are drawn, which will help readers deepen their understanding of the switching oscillations of WBG devices, and inspire readers to better use WBG devices for high-frequency and high-efficient power conversion. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) devices enable more compact and efficient design of applications such as traction inverters and rectifiers. With miniaturization of power electronics, the volume and weight of heatsink or cold plate occupies a significant portion. So, thermal design, especially power loss evaluation, is crucial to the whole system. Analytical switching model based on datasheet parameters is usually adopted to evaluate devices’ switching loss due to its convenience. However, when applied on SiC metal-oxide-semiconductor field-effect-transistors (mosfets), turn-on waveforms of conventional analytical switching model show obvious discrepancy from experiments at both current rising and voltage falling stages. The transfer and capacitance characteristics from datasheet are responsible for that. Due to short channel effect and drain-induced barrier lowering, transfer characteristic during turn on period varies with different drain-to-source voltage vds. Cgd during actual turn on period is also different from that on the datasheet. So, considering the actual turn on process, dynamic transfer characteristic and Qgd are proposed and measured in this paper. After these modifications, switching-on waveforms of the analytical switching loss model match the experiments very well, and error of the estimated loss is less than 5%. [ABSTRACT FROM AUTHOR]

This paper presents the tradeoff study of heat sink and output filter volume of a GaN HEMT based single-phase inverter. The selected topology is three-level active neutral point clamped (ANPC) inverter, and the main aim is to explore the benefits of the GaN HEMTs at 600 V blocking class on the system level efficiency, and power density under the wide range of operating conditions. The paper starts by introducing the inverter topology, selected pulse width modulation scheme and followed by the device features, static, and dynamic characterization and continues with presenting and discussing the results of extensive experimental and analytical characterization. After this, the impact of GaN HEMTs on inverter volume is discussed in terms of heat sink and output filter volume analysis under different switching frequency and heat sink temperature conditions. The calculation of heat sink volume and single stage LC output filter volume are presented with respect to experimental results of the single phase prototype. The findings from static, dynamic characterization, and single phase prototype results clearly show that GaN HEMT has excellent switching performance under wide load current and heat sink temperature conditions. The high performance of the inverter leads to reduction of the combined total volume, including output filter and heat sink volume. [ABSTRACT FROM AUTHOR]

The nine-switch converter is a multiport converter having two three-phase terminals and a dc-link, just like a 12-switch back-to-back (BTB) converter, but with 25% reduction of active switch count. However, the reduction from 12-switch to 9-switch may not always be an efficient choice considering losses in the switches. Only the load–source combination for the ac–ac common frequency mode and the source–source combination for the ac–dc different frequency (ac–dc DF) mode have been reported, so far, to yield relatively lower loss for the nine-switch converter. This paper shows that the nine-switch converter can have relatively lower loss even with a load–source combination, instead of only source–source combination in its ac–dc DF mode—when the upper terminal is connected to a dc load and the lower terminal is connected to an ac source. Mathematical proof is presented with derivation of the particular operating parameters for which the nine-switch converter will have comparatively lower losses. The analysis is validated with simulation and experimental results of a 1-kW system. Finally, the benchmark of the application criteria of the nine-switch converter for having lower conduction loss than the BTB converter is updated in this paper. [ABSTRACT FROM AUTHOR]

SiC mosfet has low on-state resistance and can work on high switching frequency, high voltage, and some other tough conditions with less temperature drift, which could provide the significant improvement of power density in power converters. However, for the bridge circuit in an actual converter, high dv/dt during fast switching transient of one mosfet will amplify the negative influence of parasitic components and produce the significant negative voltage spikes on the complementary mosfet, which will threaten its safe operation. This paper proposes a new gate driver circuit for SiC mosfet to attenuate the negative voltage spikes in a bridge circuit. The proposed gate driver adopts a simple voltage dividing circuit to generate a negative gate-source voltage as traditional and a passive triggered transistor with a series-connected capacitor to suppress the negative voltage spikes, which could satisfy the stringent requirements of fast switching SiC mosfets under the high dc voltage condition with low cost and less complexity. An analysis is presented in this paper based on the simulation and experimental results with the performance comparison evaluated. [ABSTRACT FROM AUTHOR]

This paper presents a novel single source fed isolated gate driver circuit based on the dual-forward converter topology. The two forward converters are paralleled at the secondary side to achieve 0%–100 $\%$ duty cycle range together with galvanic isolation. The gate driver switching frequency is independent of the main pulse-width modulation frequency (PWM). As a result, the gate driver switching devices and magnetics are designed for high frequencies independent of the main PWM frequency. At high frequencies, problems of resonance due to parasitics become significant. This paper discusses this problem and proposes a novel solution to mitigate it. In addition, this paper also presents a novel solution and circuit to produce negative gate pulse for miller clamp. The proposed circuit can be used for any application, irrespective of switching frequency, thus making it a wide band generalized gate driver. The circuit is analyzed and verified experimentally. [ABSTRACT FROM PUBLISHER]

High-voltage high-power pulse switches are built with semiconductor devices, preferably thyristor, due to the superior performance that they offer. Triggering methods classify the thyristor as electrically triggered thyristor (ETT) and light triggered thyristor (LTT). Due to the specialized gate constructions and many build-in protections, the cost of LTT is much higher than ETT. The operating modes in applications, such as crowbar, do not require all these build-in protections. In this paper, the operation of a crowbar is analyzed, and the build-in protections of LTT are reviewed. This paper proposes three experiments for the design selection of thyristor, between ETT and LTT, for crowbar applications. The experiments cover the electrical performance as well as electromagnetic emissions in a 10-kV, 1-kA crowbar built with both ETT as well as LTT, which can be used to benchmark the performance of the crowbar circuit. From the three experiments, the performance of ETT-based crowbar is found to be comparable with LTT-based crowbar. Based on the experiments carried out with the proposed benchmarking approaches, this paper shows that ETT-based crowbar is a cost-effective solution for crowbar applications. [ABSTRACT FROM PUBLISHER]

Pulsed magnetic field generation is a critical aspect of all nuclear magnetic resonance (NMR) experiments. In this paper, a novel design for a low field, low frequency (less than 5 MHz), pulsed magnetic field generation circuit suited for unilateral NMR applications is presented. A pulsed sinusoidal current is generated at an inductive load connected to an FET-based switch. The inductive load resonates at a frequency of approximately 2 MHz, which is also the precession frequency of ^1H protons in an external magnetic flux density of 500 G. The designed circuit can be tuned to operate at resonant frequencies of other chemical species as well. In this paper, the design parameters and operation of the prototype pulsed field generator will be discussed. [ABSTRACT FROM AUTHOR]

Recent progress of widebandgap semiconductor switching devices enabled extremely high-frequency operation of power converters owing to their ultrafast switching capability. Fast switching may cause large switching noise at the common source inductance, which may increase the switching loss and lead to false triggering. Therefore, measurement of the common source inductance is often intensely required in practical design of fast switching power converters. However, measurement of the common source inductance is difficult, because 1) the wiring path hidden beneath the molded package significantly contributes to this inductance, 2) the mutual inductance between the gating circuit and the power circuit also contributes to this inductance, and 3) this inductance cannot be defined as the stray inductance of a loop wiring path. These difficulties are addressed in this paper by proposing a novel measurement method of the common source inductance. The proposed method is applicable to already-mounted power circuits. In addition, the proposed method offers a straightforward measurement procedure with common instruments, such as a signal generator, an oscilloscope, and voltage and current probes. Along with the measurement principle, this paper also presents an experiment to evaluate the proposed method. [ABSTRACT FROM PUBLISHER]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

Generally, for pulsed power applications with low jitter and high repetition rates, the use of semiconductor switches have replaced the traditional gap switches and thyratron circuits due to the limited lifetime of the thyratron and gap switches under such operating conditions. However, the limited ratings of these semiconductor switches require series and/or parallel stacking in order to handle high voltages and current levels associated with the discharge energy. Described in this paper is the design of a high voltage switch that uses a simple and reliable gate driver circuit for pulsed power application. In this design, the switch module is made up of insulated-gate bipolar transistor (IGBTs) and their gate driver circuits compactly fitted onto a single module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier synchronization of the switches, the simultaneous transfer of both signal and power for current boost are also described in this paper. A 120 nF capacitor bank energy was discharged using a configuration of the developed high voltage switch and a developed 15 kV, 1.5 kJ/s peak power capacitor charger, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging. [ABSTRACT FROM AUTHOR]

This paper introduces a new type of switched-mode gate driver, which is capable of operating at high frequencies. This topology satisfies requirements of small passive storage components, low-voltage stress, and high design flexibility. Most popular gate-drive circuits require at least two transistors. The proposed circuit has only a single transistor and is suitable for operation at switching frequencies on the order of several megahertz. The output voltage of the gate driver is a quasi-rectangular waveform shaped by a resonant network to produce the desired gate–source voltage waveform. A detailed steady-state operation of the proposed gate driver is discussed. The power-loss analysis and design procedure are presented. Experimental results are given to verify the presented analytical approach. A laboratory prototype of the gate driver is designed, built, and tested at a switching frequency of 20 MHz. [ABSTRACT FROM AUTHOR]

Applying series configuration of the insulated gate bipolar transistors (IGBTs) to the pulsed power supplies offers unique features such as compactness and long life time. In the high-voltage pulsed power supplies, a large number of the IGBTs are required to be serially connected. Hence, the safe operating condition provision for the series IGBTs is an important and crucial issue. The effect of the voltage unbalancing factors becomes remarkable when the number of switches in the series structure increases. There are passive and active methods to balance the voltage of the series IGBTs. In both of these methods, an amount of power must be dissipated to remove the effect of the voltage unbalancing factors. Consequently, the power loss is considerable when a large number of series devices are necessary. This paper proposes an effective power recovery system that recovers the power associated with the series stacking of the IGBTs. Using this proposal, the efficiency of the resulted series switch enhances considerably. The power recovery system can be implemented easily for any number of series IGBTs. It consists of a simple dc–dc converter and several interconnection diodes for power recovery procedure. Proper performance of the proposed structure is evaluated by the aid of simulations and experiments. [ABSTRACT FROM AUTHOR]

In this paper, a new high-frequency resonant boost converter is presented. Zero-voltage switching (ZVS) for the switches and zero-current switching (ZCS) for the rectifying diode are attained. The provided ZVS conditions reduce switching losses considerably, and ZCS conditions for the diode decrease voltage oscillations. Both switches are grounded which simplifies the gate-drive circuit and enhances the converter potential for high-frequency operation. All passive elements are high-frequency resonant type and thereby the converter power density is enhanced. The resonant inductor placed in front of the converter can operate in continuous conduction mode and smoothens the converter input current. Experimental results from a 160 W/500 kHz laboratory discrete prototype with an almost high-voltage conversion ratio of 100 to 300 V confirm the integrity of the proposed converter operation. [ABSTRACT FROM AUTHOR]

Low-voltage enhancement-mode gallium nitride high electron mobility transistors (eGaN HEMTs) are a kind of promising devices to realize high-efficiency and high-power-density conversion because of their fast switching speed, low conduction, and switching losses. Since the reverse conduction loss of eGaN HEMTs accounts for a large part of switching losses, it is of great importance to improve the traditional switching analytical model to predict the reverse conduction loss. In this paper, a complete and accurate switching analytical model of low-voltage eGaN HEMTs is presented, which considers the effects of low-parasitic inductances, nonlinear junction capacitances and nonlinear transconductances. The turn-on and turn-off switching processes are described in detail, and the resulting equations are solved by using mathematical software such as MATLAB to predict the switching waveforms during the switching periods. And an accurate loss calculation method based on the proposed model is proposed including the reverse conduction loss. The accuracy of the proposed model is validated by comparing the predicted switching waveforms and the efficiency of a synchronous buck converter with the experimental results, respectively. Moreover, the proposed model is compared with the traditional model, which proves the advantages of the proposed model. In the end, according to the proposed complete model, the effect of the top switch (TS) gate resistance, the TS drain-source capacitance, power loop inductance, current ripple, the bottom switch (BS) gate resistance, the BS drain-source capacitance, and dead time on the loss breakdown of the synchronous buck converter is explored and some qualitative suggestions are given to improve the conversion efficiency based on these analyzing results. [ABSTRACT FROM AUTHOR]

Securing the intellectual property (IP) from counterfeiting is an important goal toward trustworthy computing. Camouflaging of logic gates is a well-known technique to prevent an adversary from de-layering the chip and stealing IP. In this paper, we propose threshold voltage modulation to realize 2-input static camouflaged logic that can hide six functionalities. We extend the concept of threshold-voltage defined logic to propose multi-input camouflaged gates capable of hiding six 3-input Boolean functions (NAND, NOR, AOI, OAI, XOR, and XNOR). We also propose interconnect camouflaging technique which hides the original connectivity of nets using a novel threshold-voltage defined pass transistor mux. Since threshold voltages are asserted during fabrication and are difficult to identify during optical reverse engineering (RE)-based techniques, the adversary will be forced to launch a brute-force search. We present a thorough analysis of RE effort and overheads associated with the proposed camouflaging techniques. The proposed methodology is demonstrated using fabricated test-chip in 65 nm technology. [ABSTRACT FROM AUTHOR]

In photovoltaic applications, many previous research works have focused on pulsewidth modulation (PWM) resonant converters in order to achieve a high efficiency with a wide input voltage range. Conventional approaches utilized symmetric boosting modulation at the secondary side rectifier to obtain a symmetric operation, and they utilized two boosting modes in a switching period. Among various rectifier structures, the voltage doubler structure has a strong advantage due to a small number of components. However, it suffers from serious hard switching losses in the secondary side rectifier. In this paper, a new converter with a novel asymmetrical modulation is proposed and verified. The strong point of the proposed converter is that it eliminates hard switching turn-on losses from the rectifier, while maintaining the minimized number of components. Although the proposed converter adopts an asymmetric modulation, the offset current on the transformer becomes zero inherently. Furthermore, a “forced half resonance” operation of the proposed converter keeps rms current stresses at the same level as conventional converter although it has a higher peak current. Accordingly, the proposed converter achieves a superior efficiency with the minimum number of components at 35–25 V input and 380 V/300 W output specification. [ABSTRACT FROM AUTHOR]

Nanosecond pulse discharge plasma has many prospects in industrial applications, and high-voltage repetitive nanosecond pulse generators with compact design and light weight have become one of the key issues limiting its development in some applications. This paper presents a high voltage series-connected silicon carbide (SiC) metal-oxide -semiconductor field effect transistor (MOSFETs) module which can be served as the main switch in a repetitive high-voltage nanosecond pulse generator. This kind of series-connected MOSFETs module with only single external gate driver requiring very few components is very suitable for compact assembly. By analyzing the working principle, three topologies of series-connected MOSFETs module are proposed. The switching behaviors of the three different topologies with four SiC MOSFETs series-connected are compared experimentally. The variation of switching characteristics of series-connection SiC MOSFETs module with different numbers of devices are investigated. The layout is also optimized to shorten pulse front time and improve output pulse quality. Furthermore, a 10 kV SiC MOSFETs module with a turn-on transition time ∼10 ns is developed. The double pulse test result demonstrates excellent switching performances. Finally, a compact and high-voltage pulse generator composed of three 10 kV SiC MOSFETs module is tailored, with a typical rise time ∼40 ns and peak voltage of ∼30 kV. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) power electronic devices feature the advantages of fast switching speed, low conduction loss, and reliable operation in high temperature environment, etc. Due to the differences of parasitic parameters and threshold voltage between SiC mosfets and Si mosfets, crosstalk problem is easy to be triggered when SiC mosfets are applied to bridge topologies. In this paper, the crosstalk effect with different parasitic parameters of SiC mosfets is firstly analyzed, and then an improved active crosstalk suppression method for high-speed SiC mosfets is proposed. By using the proposed method, when the crosstalk occurs, the crosstalk voltage will be decreased by reducing the equivalent gate resistance and increasing the equivalent gate-source capacitance in an active way. Consequently, the crosstalk problem can be suppressed without affecting the switching speed. To verify the effectiveness of the proposed method, a prototype of a buck–boost converter is built and the proposed modified gate driver is applied to the half-bridge topology. Comparative experimental study is conducted and the crosstalk voltage is analyzed. The experimental results verify that effective crosstalk suppression is achieved. [ABSTRACT FROM AUTHOR]

This paper addresses the design of a solid-state bipolar pulsed-power modulator based on a series of stacked power cells that realize a simple and robust structure. Each cell is charged in parallel by an LCC resonant converter independently of the discharging loop. A passive cell-balancing design is implemented. The power cell using insulated gate bipolar transistors (IGBTs) can operate in bypass mode without an additional component, and the circuit operation was analyzed. A simple gate driving method, which provides synchronized gate signals without an extra power source of each gate driver using two control loops and isolation transformers, is implemented for the proposed bipolar pulsed-power modulator based on stacked cells. Moreover, an unexpected gate turn-on problem was solved by an additional off signal. To validate the proposed structure and the gate driving scheme, a three-cell, 1.2-kV, 110-A, 1.5- to 4- $\mu \text{s}$ , 3-kHz laboratory experimental prototype test was conducted. The results proved the reliability of the proposed solid-state bipolar pulsed-power modulator. [ABSTRACT FROM AUTHOR]

This paper proposes a flyback-circuit-based design of a trigger circuit for a high-power gas switch. By incorporating a flyback circuit in a high-power gas switch, it is possible to generate a high step-up ratio and high-voltage pulse by using a transformer. Furthermore, simple trigger circuit having the minimum possible number of components (transformer and switch) can be realized. When an inductor is used as an energy storage element, energy is stored as a current source, and thus, the element can operate reliably when low impedance exists between the trigger node of the switch after triggering. According to the fundamental operating principle of a flyback circuit, the proposed trigger circuit is designed considering the maximum trigger voltage and energy required for a high-power gas switch. To verify the proposed design procedure and feasibility of the trigger circuit, a compact trigger circuit (7.5 kV, 1.3 mJ/pulse) is simulated using the PSpice program and implemented. Based on this compact circuit, a trigger circuit (20 kV, 100 mJ/pulse) for a triggered vacuum switch (TVS) is developed, and the tests with an actual TVS (3.3 kJ) are carried out. [ABSTRACT FROM AUTHOR]

The dynamic on-resistance in gallium nitride (GaN) devices is problematic as it can impair the converter's efficiency due to the increased conduction loss. In this paper, the hard-switching transient's effect on the dynamic on-resistance is, for the first time, evaluated experimentally on a commercial high-voltage GaN high electron mobility transistor. A new ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ measurement circuit with fast sensing speed is designed, and an accurate measurement of ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ can be realized experimentally within 49.6 ns after the device's current reaches to the load current. A double-pulse-test setup is designed to comprehensively evaluate the switching transient's effect on ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ under different operating conditions. From the experimental results, it is found that the turn-on and turn-off gate resistance have a significant impact on the dynamic on-resistance whereas the cross-talk effect on ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ is negligible. Specifically, at 400 V/25 A, more than 27% (28.2%) increase in ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ is observed when the external turn-on (turn-off) gate resistance increases from 0 to 20 Ω. Detailed discussion and quantitative analysis are provided to explain the experimental results. In terms of the turn-on process, it is concluded that the ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ variation is mainly caused by the different numbers of generated hot electrons. For the turn-off transient, it is confirmed the variation of drain current at different dv/dt slew rate leads to the ${R_{{\rm{dyn}} - {\rm{ds}},{\rm{on}}}}$ difference. [ABSTRACT FROM AUTHOR]

A gate driving for power devices is a key technology to further improve switching characteristics. With the help of digital gate driver IC, the switching behavior of power devices can be enhanced even under high-speed switching. In this paper, an evaluation platform for determining the optimal switching pattern of an active gate drive control is proposed for an inverter circuit. A high speed optimization system is built up to search for an advantageous switching pattern that reduces total switching loss of two power devices in an inverter circuit and constrains surge voltage simultaneously. The proposed online optimization demonstrates its feasibility for the full-bridge inverter circuit, which is rated at 500 V with digital active gate drive control. Experimental results show that the proposed optimization system is able to obtain optimal switching pattern from $64^{60}$ possible combinations of switching patterns within 15 min, which is 6 times faster than the previous study. Optimizations can also conducted under different load current conditions. Eventually, the obtained optimal pattern yields up to 42% reduction in the total switching loss when it constrains surge voltage to minimum compared with the conventional driving pattern. [ABSTRACT FROM AUTHOR]

Parasitic ringing is commonly observed during the high-speed switching of wide band-gap (WBG) devices. Additional loss contributed by parasitic ringing becomes a concern especially for high switching frequency applications. This paper investigates the effects of parasitic ringing on the switching loss of WBG devices in a phase-leg configuration. An analytical switching loss model considering parasitics in power devices and application circuit is derived. Two switching commutation modes, gate drive dominated mode and power loop dominated mode, are investigated, respectively, and the switching loss induced by damping ringing is identified. It is found that this portion of the loss is at most the energy stored in parasitics, which always exists regardless of the switching speed and parasitic ringing. Therefore, with the given WBG device in the specific application circuit, damping more severe parasitic ringing during faster switching transient would not introduce higher switching loss. Additionally, the extra switching loss induced by resonance among parasitics and crosstalk is investigated. It is observed that severe resonance and its resultant over-voltage during the turn-on transient worsen the crosstalk, causing large shoot-through current and excessive switching loss. The theoretical analysis has been verified by the double pulse test with a 1200-V/50-A SiC-based phase-leg power module. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) has shown substantial promise in the fabrication of high-power devices, and SiC Schottky diodes and field-effect transistors (FETs) have been considered as potential candidates for outerspace and sensors applications. Due to the multipolar structure, SiC gate turn-off thyristor (GTO) device is relatively sensitive to the irradiation-induced point defects. However, how SiC GTO devices perform under neutron irradiation still needs to be clarified. In this paper, the effects of neutron irradiation on the static and dynamic switch characteristics of high-voltage 4H-SiC GTOs are investigated for the first time. For the static electrical properties, it is found that the forward current significantly decreases with the increasing neutron irradiation fluence. While the cathode leakage current in the blocking characteristics shows an insignificant change up to a neutron fluence of ${1.0} \times {10}^{{13}}$ n/cm2. For the switching characteristics, both the pulse peak current and di/dt show substantial reduction as the neutron fluence increases while the delay time increases after irradiation. The degraded performance of the static and dynamic characteristics of SiC GTO devices was then analyzed and attributed to the weakened conductivity modulation and reduced carrier injection efficiency into the drift layer. These two aspects originate from the significantly reduced carrier lifetime and deteriorated forward characteristics of anode-gate diodes, respectively. [ABSTRACT FROM AUTHOR]

Featuring higher switching speed and lower losses, the silicon carbide mosfets (SiC mosfets) are widely used in higher power density and higher efficiency power electronic applications as a new solution. However, the increase of the switching speed induces oscillations, overshoots, electromagnetic interference (EMI), and even additional losses. In this paper, a novel active gate driver (AGD) for high-power SiC mosfets is presented to fully utilize its potential of high-speed characteristic under different operation temperatures and load currents. The principle of the AGD is based on drive voltage decrement during the voltage and current slopes since high dV/dt and dI/dt are the source of the overshoots, oscillations, and EMI problems. In addition, the optimal drive voltage switching delay time has been analyzed and calculated considering a tradeoff between switching losses and switching stresses. Compared to conventional gate driver with fixed drive voltage, the proposed AGD has the capability of suppressing the overshoots, oscillations, and reducing losses without compromising the EMI. Finally, the switching performance of the AGD was experimentally verified on 1.2 kV/300 A and 1.7 kV/300 A SiC mosfets in double pulse test under different operation temperatures and load currents. In addition, an EMI discussion and cost analysis were realized for AGD. [ABSTRACT FROM AUTHOR]

The Computational Random Access Memory (CRAM) is a platform that makes a small modification to a standard spintronics-based memory array to organically enable logic operations within the array. CRAM provides a true in-memory computational platform that can perform computations within the memory array, as against other methods that send computational tasks to a separate processor module or a near-memory module at the periphery of the memory array. This paper describes how the CRAM structure can be built and utilized, accounting for considerations at the device, gate, and functional levels. Techniques for constructing fundamental gates are first overviewed, accounting for electrical and noise margin considerations. Next, these logic operations are composed to schedule operations in the array that implement basic arithmetic operations such as addition and multiplication. These methods are then demonstrated on 2D convolution with multibit data, and a binary neural inference engine. The performance of the CRAM is analyzed on near-term and longer-term spintronic device technologies. Significant improvements in energy and execution time for the CRAM-based implementation over a near-memory processing system are demonstrated, and can be attributed to the ability of CRAM to overcome the memory access bottleneck, and to provide high levels of parallelism to the computation. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

This paper proposes unified non-inverting and inverting ac–ac converter (UNI-AC) using pulse width modulation (PWM) for the utility voltage compensation. It offers four effective switching states to regulate the output voltage in bipolar manner, facilitating versatile modes of operation with different number of switching states being modulated. Each mode of the proposed UNI-AC is able to compensate both the grid voltage sag and swell problems due to its bipolar voltage gain. The operational principle and comparison for all these modes are investigated in details. Also, the UNI-AC is reversible and compatible with full range of power factor. Other technical merits offered by the proposed approach include the compact hardware installation, reduced switch voltage stress (also low dv/dt) and decreased control complexity. Detailed analysis and experimental verification are presented in this paper. [ABSTRACT FROM AUTHOR]

Test vector omission allows the length of a functional test sequence to be reduced without reducing its fault coverage. When a circuit is embedded in a design, the omission of test vectors from a functional test sequence for the circuit may result in a sequence that does not satisfy the functional constraints imposed by the design. This paper addresses this issue by developing a procedure that restores omitted test vectors in order to satisfy functional constraints. For the discussion in this paper, functional constraints are captured by the switching activity of the sequence before any test vectors are omitted from it. This is referred to as its functional switching activity profile. Experimental results demonstrate that the length of a sequence can be reduced even after restoration of omitted test vectors based on its functional switching activity profile. [ABSTRACT FROM AUTHOR]

The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in synchronous dc–dc buck converters. This paper presents a converter using a gate drive with a negative biased gate voltage on the low-side FET to improve the dV/dt robustness. The resulting much larger voltage drop during the dead time conduction is a concern as it can quickly overcharge the bootstrap capacitor voltage. This paper demonstrates that with a negative biased gate voltage, the rise in the bootstrap capacitor voltage is predominantly caused by the change in effective dead time conduction due to a variation in output load. A spice model to estimate the change is presented and verified. This paper also found that a change in the bootstrap capacitor voltage must be prevented as it leads to a significant change in turn-on dynamics, resulting in higher dV/dt stress with an increase in output load. To prevent a change in bootstrap capacitor voltage, different techniques such as Zener diode clamping and an external free-wheeling Schottky diode are tested and discussed. Finally, a modification of a standard bootstrap circuit using a series inductor is proposed and tested. It has been found to be the most effective method in preventing a variation in the bootstrap capacitor voltage and should be included when using a negative gate drive in a GaN dc–dc buck converter. [ABSTRACT FROM AUTHOR]

This paper evaluates the temperature-dependent static and switching characteristics of SiC Trench mosfets in a low-inductance multiple-chip power module. First, a phase-leg power module package design with integrated decoupling capacitance is proposed and fabricated based on the P-cell/N-cell concept, and the module design including the substrate layout and packaging material selection are discussed. With the fabricated power module, the temperature-dependent static and switching characteristics of the SiC Trench mosfets are comprehensively investigated, and the key performance differences from the traditional SiC planar mosfets are discussed. Specifically, compared to the SiC mosfets with planar structure, the SiC Trench mosfets are observed to have a different temperature coefficient in term of the turn-off switching loss. Detailed analysis is provided as well to explain the experimental results. [ABSTRACT FROM AUTHOR]

Series–parallel forward dc–dc converter system is a good option in high-voltage high-power applications. A switch fault, in this converter, should be detected as soon as possible, to avoid further damage and save maintenance cost. In this paper, a new switch fault diagnosis method, which treats output inductor voltages as diagnostic criteria, is proposed for this system. With the proposed method, expensive sensors are needless, since diagnostic signal can be easily acquired by adding a small auxiliary winding into inductor magnetic core. Based on the feature of diagnostic signals in such a system, a low-cost diagnostic circuit is designed. The failed module caused by open-circuit fault or short-circuit fault could be detected within one switching period, allowing for an immediate fault-tolerant action. This method also shows generality for different connections and buck-type isolated topologies. Besides, it works reliably under input-voltage variation and load step, and no misdiagnosis will occur during normal dynamic process. Finally, experimental result verifies the effectiveness of this method. The proposed scheme has a good potential to be applied in real applications for its simplicity and robustness. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

The improved three switch-active clamp forward (3S-ACF) converter is proposed in this paper. The proposed converter has minimized the switching loss on all switches of the conventional 3S-ACF converter by simply changing the gate control method without any additional components. Moreover, the modified gate control enables peak and average currents on the clamp diode to be reduced. Though, all switches of the proposed converter have low-voltage stress similarly to those of the conventional 3S-ACF converter. Consequently, the proposed converter can achieve a high efficiency without any additional components. To confirm the operation, features, and validity of the proposed converter, a 180–288 Vdc input and 12 V/550 W output laboratory prototype is built and tested. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]