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This paper presents an optimization framework for sequential reconfiguration using an assortment of switching devices and repair process in distribution system restoration. Compared to existing studies, this paper considers types, capabilities and operational limits of different switching devices, making it applicable in practice. We develop a novel multi-phase method to find the optimal sequential operation of various switching devices and repair faulted areas. We consider circuit breakers, reclosers, sectionalizers, load breaker switches, and fuses. The switching operation problem is decomposed into two mixed-integer linear programming (MILP) subproblems. The first subproblem determines the optimal network topology and estimates the number of steps to reach that topology, while the second subproblem generates a sequence of switching operations to coordinate the switches. For repairing the faults, we design an MILP model that dispatches repair crews to clear faults and replace melted fuses. After clearing a fault, we update the topology of the network by generating a new sequence of switching operations, and the process continues until all faults are cleared. To improve the computational efficiency, a network reduction algorithm is developed to group line sections, such that only switchable sections are present in the reduced network. The proposed method is validated on the IEEE 123-bus and 8500-bus systems. [ABSTRACT FROM AUTHOR]

Piezoelectrically actuated fast mechanical switches provide a low-loss conduction path in hybrid circuit breakers for protecting medium-voltage direct-current systems. As the desired actuation speed approaches the driving limit of a piezoelectric actuator, excessive vibration starts to dominate its underdamped travel curves, resulting in insulation failures and delayed switching in the fast mechanical switch. To improve the underdamped travel curves into critically damped travel curves, several switching motion control schemes with active damping filters are proposed in this paper. The switching motion controllers are based on an electromechanical model of a fast mechanical switch with experimentally identified parameters. According to hardware implementation tests, the proposed closed-loop control schemes optimized the switch travel curves with a 56% reduction in the undershoot and a 75% reduction in the settling time. Equipped with the critically damped travel curves, the piezoelectrically actuated fast mechanical switch is better suited for sequential submodule operations to reduce the interruption time, the peak current and the fault energy to be absorbed in hybrid circuit breakers. [ABSTRACT FROM AUTHOR]

Different from typical circuit breakers, breakers used to switch AC filters in convertor stations have to operate frequently according to the real-time operation mode and daily load changes. Therefore, the performance of filter breakers decreases very quickly, which leads to frequent accidents. Both preinsertion resistors and controlled switching devices can suppress switching transients. In this paper, a comparative analysis of whether a controlled switching device and preinsertion resistor should be adopted is carried out using PSCAD. The transient is calculated as the combined result of the switching angle and preinsertion resistor value, and the optimal configurations are proposed. After determining the resistor value and whether a controlled switching device should be included, the reference voltage of the arrester should be reevaluated. [ABSTRACT FROM AUTHOR]

Condition assessment of Medium Voltage switchgears requires effective, but inexpensive solutions to become a common practice. On the other hand, failure of a switchgear component can cause cascade effects and outage of other apparatus, in addition to significant economic losses due, e.g., to lack of energy availability. A major diagnostic property to evaluate switchgear health and reliability is partial discharges, being a direct cause of failure of organic insulation systems. A new approach to automatic, self-assessment of switchgear reliability based on partial discharge, PD, acquisition and processing, as well as a new type of PD sensor solution are presented in this paper. The sensor is based on the capacitive divider existing in most bushings to indicate the presence or absence of voltage. The innovative automatic software is able to provide automatic noise and PD separation, noise rejection and type of PD-source identification. The embedded bushing sensor has been tested on switchgears in the presence of defective components as cable terminations and bushings. Results show that the sensor, coupled with the automatic software, is able to provide good sensitivity compared to other sensors, and good capability to locate the cabinet and identify the type of source generating partial discharges. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

The emergence of applications which require high-voltage switches has created a tendency to use semiconductor device series stacks. These series stacks permit operation at blocking voltages above semiconductor elements’ nominal voltage. Insulated-gate bipolar transistors (IGBT) are currently utilized for controllability and switching speed, when these topologies are employed. The main challenge therewith is guaranteeing voltage balance between IGBTs, both when blocked and when switching transistors. Most of the methods which have been proposed to mitigate static and dynamic voltage unbalances increase transistor losses. The series stack loss-less high voltage switch (LHVS) which mitigates voltage unbalances, thus reducing switching losses, is presented in this paper. LHVS consists of a circuit, which ensures soft IGBT switching, an energy recovery circuit, and a gate delay compensation circuit. Additionally, the insulation voltage level is guaranteed to be equal between control circuit and high-voltage side of each IGBT. The operating principle of the LHVS is detailed in this paper, as is experimental validation which has been performed for three series stack modules. Static unbalances are reduced to 1%, while the differences between collector–emitter voltage curves in switching “on” do not surpass 8 ns, and switching losses are reduced by 41%, as compared to the hard-switching topology. [ABSTRACT FROM AUTHOR]

Clamp mode snubbers are very well suited for the series structure of the insulated-gate bipolar transistors (IGBTs) in pulsed power applications. They properly meet the necessities expected from them such as the fast operating of the series IGBTs since they have no effect on the gate side. In addition, they can provide safe voltage condition for the IGBTs in short circuit faults, which are very probable in pulsed applications. The clamp mode snubber can perform its voltage balancing task whenever the power capacity of the snubber can support the injected powers due to the voltage unbalancing factors. This paper initially introduces the main factors injecting power to the snubbers. Then, it will be illustrated that the exact injected power to each predetermined snubber cannot be determined due to the uncertainties about the effect of the voltage unbalancing factors. Although it is impossible to determine the exact value of the power injected to each snubber, the total injected powers to the snubbers can be calculated. Therefore, as an effective remedy, this paper proposes a concentrated snubber. Using the proposal, all the injected powers are conducted to a centralized circuit and can be easily managed. In addition, analytical expressions are provided for proper dimensioning of the proposed concentrated snubber elements. Furthermore, the performance of the proposed concentrated snubber is evaluated using simulations and experimental prototyping. [ABSTRACT FROM AUTHOR]

The quantum phase-slip junctions (QPSJs) resulting from quantum fluctuation of superconducting order parameter in 1-D superconducting nanowires are explained as exact duals to Josephson junctions (JJs). An overdamped QPSJ can generate a current pulse to emulate a spiking event in biological neurons. We have demonstrated spiking neuron circuits and synaptic circuits using QPSJs in our previous work through simulations in WRspice. The neuron circuit can fire a current pulse as soon as the capacitor voltage is above a threshold, which is similar to an integrate-and-fire neuron (IFN). The synaptic circuit, either based on magnetic JJs and QPSJs or only using QPSJs, functions as an adjustable weighted connection between neurons. To overcome existing problems, such as fan-out limitations, and further explore the possible applications of QPSJs in superconducting neuromorphic computing, we propose new neuromorphic circuits based on QPSJs and JJs in this paper. The neuron, synapse and fan-out circuits operate through the transfer of quantized charge or fluxons, providing circuit operations that emulate brain functions. Since the fabrication of reproducible QPSJ elements remains at a preliminary stage, the demonstration of our circuits design has been primarily done in WRspice simulation with a QPSJ SPICE model. [ABSTRACT FROM AUTHOR]

The distributed propulsion aircraft with HTS electrical system is a novel concept for future airliners, which can reduce by more than 70% fuel burn and NOx emissions. The circuit breakers ensure the security of this novel aircraft by isolating electrical faults timely. Solid-state circuit breakers (SSCBs) are preferred due to their fast response and high performance in the cryogenic circumstance. However, the high conduction loss of SSCBs impedes their further application. A mechanical switch using liquid nitrogen (LN2) as an arc extinguishing medium shows excellent DC current interruption performance. The LN2 switch is characterized with extremely low contact resistance, and the proper use may reduce the conduction loss of power switches significantly. Nevertheless, the effect of metal type arc chutes on the arcing process in the LN2 is still not clear. Thus the objective of this paper is to understand the effect of metal type arc chutes on the current interruption performance of LN2. Silicon iron arc chutes are employed. Neodymium (NdFeB) magnets are used to stretch the arc into the arc chutes. The maximum interrupting current is 1 kV/ 2 kA when only magnets are applied. Further applying the arc chutes leads to a significant drop in the arc voltage and interruption performance. Since the high relative permeability of silicon iron weakens the magnetic field acting on the arc, metal type arc chutes are not recommended. 1 kV / 10 kA fault current is successfully cleared by the combination of resistance type superconducting fault current limiter (R-SFCL) and LN2 switch with magnets, during which the R-SFCL responds to the fault within 420 μs, compensating the long clear time of the LN2 switch. [ABSTRACT FROM AUTHOR]

Motors and inverters are increasingly being used in vehicles. As more vehicle components are being adopted, requirement for safety and installation space are increasing. Growing attention is being paid to the use of six-phase permanent magnet synchronous motors (PMSMs) and their parallel control by two inverters, because of their reduced size and enhanced safety. This paper proposes a pulsewidth modulation (PWM) control algorithm for a six-phase PMSM. In low-voltage vehicle components such as electric power steering, the current is usually acquired with resistors placed under the low-side switching devices. In the proposed control algorithm, the neutral voltage of the two inverters is shifted to either a lower or higher voltage within a certain range to allow for the signal conditioning time delay after the switching device turns on or off, and the time taken for the phase current to rise or settle. The paper proposes a novel PWM control algorithm that ensures that the on-time of the low-side switching devices satisfies the restriction on current sensing with resistors and reduces the current in the capacitor at the same time. The work contributes to reducing the current in a practical configuration involving low-voltage vehicle components. [ABSTRACT FROM AUTHOR]

This paper has introduced two important indexes, turn-off surge voltage (TSV) on power switch and peak positive pole potential (PPPP) of storage batteries, which can be used to evaluate switching transient process of high-voltage energy storage system. Research on them is of great significance to power switch choice and high-voltage isolation design in engineering applications. Power switch response process at the turning off moment and transient process in freewheel stage have been analyzed by the established small-signal model of single power switch; then, a power switch test platform for hybrid energy storage system was built to verify it. Taking pulsed-power supply charging device with a novel inductor of low resistance and high inductance as a research object, this paper has analyzed dynamic process of the TSV and the PPPP at the turning off moment through establishing state space model of the whole system. Comparison shows that the numerical curves match the simulated curves well. Finally, the exactness of the employed model has been further verified in two pulse capacitor charging experiments. [ABSTRACT FROM AUTHOR]

In data center and telecommunication power supplies, the front-end dc–dc stage is required to operate with a wide input voltage range to provide hold-up time when ac input fails. Conventional LLC converter serving as the dc–dc stage is not suitable for this requirement, as the normal operation efficiency (at 400 V input) will be penalized once the converter is designed to achieve high peak gain (wide input voltage range). This paper examined the operation of the LCLC converter and revealed that the LCLC converter could be essentially equivalent to a set of LLC converters with different magnetizing inductors that are automatically adjusted for different input voltages. In nominal 400 V input operation, the LCLC converter behaves like an LLC converter with large magnetizing inductor, thus the resonant current is small. In the hold-up period, when the input voltage reduces, the equivalent magnetizing inductor will reduce together with switching frequency reducing, thus the converter achieves high peak gain. In this paper, a new design methodology is also proposed to achieve optimal utilization of the two resonant capacitors for high power application. To verify the effectiveness of the LCLC converter for hold-up operation, comprehensive analysis has been conducted; a detailed step by step design example based on capacitor voltage stress is introduced; an experimental LCLC prototype optimized at 400 V, with input voltage range of 250–400 V and 12 V/500 W as output has been presented. [ABSTRACT FROM AUTHOR]

Modular multilevel converter (MMC) has been a promising candidate in high voltage direct current (HVdc) transmission systems. Due to the features of simple structure, low cost, and low power losses, half-bridge (HB) is usually adopted as the submodule circuit in the traditional MMC. However, an HB submodule circuit-based MMC does not have the capability of blocking dc short-circuit fault, which obstructs the development of low-cost HVdc systems with overhead lines. In order to solve this problem, an MMC with active clamped T-type submodule (ACTSM) to own dc fault blocking capability is proposed in this paper. Compared with other submodule circuits, the proposed ACTSM has many features, such as symmetrical blocking capability, low power losses, low voltage stress, and low amount of independent drive signals. The topology, operation principle, dc fault blocking capability, and distribution of power losses of the ACTSM are presented in this paper. The effectiveness of the ACTSM-based MMC is validated by both simulations and experiments. [ABSTRACT FROM AUTHOR]

Gallium-nitride-field-effect transistors (GaN-FETs) are promising switching devices with fast switching capability. However, they commonly have low gate threshold voltage, suffering from susceptibility to the false triggering. Particularly, the oscillatory false triggering, i.e., a self-sustaining repetitive false triggering, can occur after a fast switching, which is a severe obstacle for industrial applications. The purpose of this paper is to elucidate the design instruction for preventing this phenomenon. The oscillatory false triggering is known to be caused by the parasitic oscillator circuit formed of a GaN-FET, its parasitic capacitance and the parasitic inductance of the wiring. This paper analyzed the nonoscillatory condition of this oscillator. The result revealed an appropriate ratio between the gate-drain capacitance and the common-source inductance is a key to prevent the oscillatory false triggering. Experiment successfully verified this analysis result, supporting the effectiveness of the appropriate design of this ratio for preventing the oscillatory false triggering. [ABSTRACT FROM AUTHOR]

Soft-switching techniques of transformerless photovoltaic grid-connected inverters (TLIs) can significantly reduce switching losses, as well as soften switching processes. Conventional dc–ac soft-switching configurations proposed by Dr. Deepakraj M. Divan are invalid in TLIs because of the leakage current problem. In order to develop soft-switching techniques in TLIs, this paper proposes a new soft-switching configuration and a procedure to guide the invention of soft-switching TLIs. First, this paper proposes two basic resonance tanks related to dc bus polarities, and then, uses these basic tanks to elevate four popular full-bridge-type TLIs according to the proposed guideline. As a result, four soft-switching TLIs are gained. Second, this paper picks obtained soft-switching highly efficient and reliable inverter concept (HERIC) as example to analyze its soft-switching operation principle and performance. As a consequence, all active switches of the gained soft-switching HERIC circuit are switched under both of zero-current turn-on and turn-off conditions; the reverse recovery problem of freewheeling diodes is alleviated owing to the zero-current turn-off of diodes; meanwhile, the common-mode voltage at the switching frequency scale is still constant. Finally, some experimental results from a 3-kW universal prototype at 50-kHz switching frequency are provided to verify the effectiveness of the main contributions of this paper. [ABSTRACT FROM AUTHOR]

The paper deals with some new results on the averaging theory approach for the analysis of feedback controlled pulsewidth modulation power electronic converters. It develops some considerations regarding the averaging approximation of time-variant differential systems proving an analytical relationship between the accuracy with which the solution of the averaged model converges to the solution of the original time-variant model (i.e., the switched model) and the switching frequency of the converters. This relation is valid both for stable and unstable systems. Moreover, this paper confirms, as corollary, that under suitable conditions (verified during the standard operations of the power electronic converters) the averaged model uniformly converges to the switched model. [ABSTRACT FROM AUTHOR]

This paper proposes a new modulated model predictive control method for the control of modular multilevel converters (MMCs) in voltage source converter-high voltage dc systems. The proposed method retains the advantages of the conventional finite control set-model predictive control methods by programing the nonlinear properties of the MMC into the design calculations while minimizing the ac line and circulating current ripples and steady-state error by generating modulated switching signals with a fixed switching frequency. In this paper, first, the predictive modeling of the MMC is provided. Next, the proposed control method is described. Then, the application of the proposed method to an MMC system is detailed. Finally, experimental results from an MMC system connected to a three-phase grid are provided to validate the theoretical outcomes. [ABSTRACT FROM AUTHOR]

This paper presents a unified framework for the modeling, analysis, and design of load-independent Class E and Class EF inverters and rectifiers. These circuits are able to maintain zero-voltage switching and, hence, high efficiency for a wide load range without requiring tuning or use of a feedback loop, and to simultaneously achieve a constant amplitude ac voltage or current in inversion and a constant dc output voltage or current in rectification. As switching frequencies are gradually stepping into the megahertz (MHz) region with the use of wide-bandgap (WBG) devices such as GaN and SiC, switching loss, implementing fast control loops, and current sensing become a challenge, which load-independent operation is able to address, thus allowing exploitation of the high-frequency capability of WBG devices. The traditional Class E and EF topologies are first presented, and the conditions for load-independent operation are derived mathematically; then, a thorough analytical characterization of the circuit performance is carried out in terms of voltage and current stresses and the power-output capability. From this, design contours and tables are presented to enable the rapid implementation of these converters given particular power and load requirements. Three different design examples are used to showcase the capability of these converters in typical MHz power conversion applications using the design equations and methods presented in this paper. The design examples are chosen toward enabling efficient and high-power-density MHz converters for wireless power transfer (WPT) applications and dc/dc conversion. Specifically, a 150-W 13.56-MHz Class EF inverter for WPT, a 150-W 10-MHz miniature Class E boost converter, and a lightweight wirelessly powered drone using a 20-W 13.56-MHz Class E synchronous rectifier have been designed and are presented here. [ABSTRACT FROM AUTHOR]

Superjunction MOSFETs in cascode configuration with low-voltage silicon MOSFETs are evaluated in this paper. The proposed structure combines the good switching performance provided by the cascode configuration with the benefits of the silicon technology such as its robustness, maturity, and low cost. This paper aims to explain and to demonstrate the reduction of switching losses of superjunction MOSFETs in cascode configuration with respect to their standalone counterparts (directly driven). A detailed simulation analysis of power loss contributions is carried out under hard-switching operation. Moreover, experimental evidence is provided using a boost converter (100–400 V) operating in continuous conduction mode for different switching frequencies (100–400 kHz) and output power levels (180–500 W). [ABSTRACT FROM AUTHOR]

This paper presents a new modular ac/dc step-up soft-switched converter with unity turns ratio high-frequency transformers for medium-voltage (MV) dc grid in wind energy systems. In the proposed converter, the three-phase boost rectifier is combined with step-up resonant circuits and high-gain output rectifier modules (called voltage quadrupler modules) to form a modular step-up power conversion unit. As a result, the proposed converter is able to achieve very high voltage gain without using any medium-to-high frequency transformers with very large turns ratio, which greatly simplifies the insulation requirement and design of the high-frequency transformer. In addition, soft-switching operations are achieved in all the semiconductor devices to maintain high efficiency. The techniques to ensure voltage balancing across the dc-link capacitors and to achieve output short-circuit protection will be discussed in this paper. To realize high-frequency MV operation, silicon carbide (SiC) devices are utilized in the converter implementation on a 1.5 MW, 690 VAC/40 kV converter system to validate the performance of the proposed circuit. Experimental results on a 3.5 kW, 145 VAC/6.2 kV, 95.4% efficiency SiC-based laboratory-scale proof-of-concept prototype are then provided to highlight the merits of this work. [ABSTRACT FROM AUTHOR]

The neutral-point voltage-balancing control is a critical issue of a neutral-point-clamped converter. The conventional control strategy is to inject the specific zero-sequence voltage to regulate the redundant vector, but it is unacceptable to the three-phase four-wire system. This paper provides a neutral-point voltage-balancing control by the dipolar modulation, and the control freedom of the zero-sequence voltage is flexible. Therefore, the proposed method is suitable for both three-phase three-wire and three-phase four-wire systems. Besides, the proposed method improves the control dynamic in a reactive power system. The proposed neutral-point voltage-balancing control is verified by the mathematical analysis and experimental results. The control dynamic, power loss estimation, and the output current performance are analyzed in this paper. [ABSTRACT FROM PUBLISHER]

A new isolated single-stage soft-switching power-factor-correction (S4 PFC) driver for supplying light-emitting diodes (LEDs) is introduced in this paper. In the proposed LED driver, the switches voltage stress and also the dc-bus voltage is limited to the peak of the line voltage. Hence, low voltage rated mosfets and diodes can be used. The efficiency is improved because the switches are turned on under zero current switching (ZCS) condition and turned off under zero voltage zero current switching (ZVZCS) condition. Also, no current feedback is required since the converter provides an output current independent of output voltage. In this paper, operating principle of the proposed LED driver is presented and design considerations are discussed. To verify the theoretical analysis, a laboratory prototype of the proposed converter for supplying a 50 W/70 V LED module from 220 Vrms/50 Hz ac mains is implemented, and the experimental results are presented. Since current feedback is not used, dimming property and operation for universal voltage range is not achievable. [ABSTRACT FROM PUBLISHER]

In applications that demand single-input dual-output (SIDO) or dual-input single-output (DISO) dc–dc converters, employing two separate single-input single-output (SISO) converters is a solution. However, the number of components is doubled, resulting in high overall cost. In order to reduce costs, this paper proposes a novel topology synthesis methodology, with which a variety of SIDO and DISO dc–dc converters with reduced components can be derived. The principle of topology synthesis states that integrated SIDO and DISO dc–dc converters can be easily developed from conventional SISO converters by replacing a diode with a basic cell inclusive of additional input/output port. The principle is effective for many SISO dc–dc converters, and as an example, topology synthesis based on buck, boost, buck–boost, Cuk, sepic, and zeta SISO converters is performed in this paper. In order to achieve better understanding of the proposed converters, the integrated SIDO Cuk converter is specifically analyzed and experimentally verified. In comparison with the conventional scheme of two separate SISO Cuk converters, good cross regulation is retained while the number of diodes, inductors, and capacitors is reduced in the proposed SIDO Cuk converter. In addition, zero-voltage-switching operation of one switch is achieved, contributing to lower switching losses. Finally, a prototype circuit with 48-V input and 156 V/1 A, 24 V/4 A outputs is built to validate the theoretical analysis. [ABSTRACT FROM PUBLISHER]

The modeling and control of a buck–boost and stacked dual half-bridge (DHB) integrated bidirectional dc–dc converter have been studied in this paper. This converter features high-voltage transfer ratio, high efficiency, and the minimum number of switches. In this paper, an extended, continuous, full-order, state-space averaging modeling method is proposed. Compared with existing methods, the proposed method exhibits higher coincidence with the switching circuit simulation, in steady and especially dynamic states. Due to its high dynamic accuracy and low complexity, the proposed modeling method provides a better theoretical analysis and a fast simulation tool for transient process and control design of converters with dual-active-bridge units, especially with DHB units. By using this method, the high-frequency transformer series inductance current is directly divided into a sampled dc component and a fluctuant component. Only the sampled dc one is included into state variables, but both components are considered into state equations. Besides, this method regards the entire converter as a linear superposition of its subsections, which provides a stepwise modeling based on linearization of subsections. Moreover, a decoupled proportional-integral control method is proposed to enhance the stability and dynamic response of the converter. This control method is analyzed by the proposed models, which can be regarded as an application of the proposed modeling method. Simulation and experiments have validated both the proposed modeling and the decoupled control strategy. [ABSTRACT FROM PUBLISHER]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric. [ABSTRACT FROM PUBLISHER]

This paper focuses on the design, performance modeling, and evaluation of probabilistic logic using superparamagnetic nanomagnets for which there exists a strong interplay between deterministic dynamics and intrinsic thermal noise. The switching element in the spin domain is chosen as the giant spin-Hall effect (GSHE) device that operates based on the dipolar coupling phenomenon in a two-magnet system to achieve low-energy ( $\approx ~1.3$ fJ/b) and low-power ( $\approx ~0.5~\mu $ W) switching characteristics. The use of spin currents on the order of a few tens of mA/ $\mu $ m2 in the subcritical regime to operate the GSHE device yields nondeterministic switching behavior with probability of correctness less than 100%. Therefore, the proposed technique allows us to trade off circuit accuracy for tremendous reduction in energy and power dissipation. In this paper, we identify the required dimensions and material parameters of the read–write units to ensure robust magnetic dipolar coupling for reliable operation of the GSHE switch. Then, through Monte Carlo simulations, we evaluate the probabilistic switching behavior of the GSHE switch as a function of the input spin current amplitude and pulsewidth for various orientations of the magnetization vectors. The delay of the GSHE switch is quantified using a probability distribution function owing to the randomness imparted to the dynamics by intrinsic thermal noise of the nanomagnets. The relationship between the probability of correctness and the energy dissipation of the GSHE switch is quantified. The results are extended to evaluate the performance and circuit error rate of complex logic gates, such as NAND and NOR, constructed using the GSHE switch. It is shown that unlike the probabilistic CMOS (PCMOS) logic, the circuit error rate in the GSHE logic becomes a function of the input vector combination and the prior state of the switch. These nuances are captured in the compact model of the circuit error rate of multiple-input GSHE logic developed in this paper. The performance of the probabilistic GSHE logic is compared with that of PCMOS logic at the 14 nm technology node. Since the noise generation process in PCMOS logic has a limited bandwidth of tens of megahertz and consumes tens of microwatt power, the peripheral circuitry becomes prohibitive. By utilizing the inherent thermal stochasticity, nanomagnets provide a clear advantage to implement probabilistic computing platform targeted toward error-tolerant applications such as those from the image processing and machine learning domains. [ABSTRACT FROM AUTHOR]

This paper presents the effect of stray capacitances in bipolar (negative and/or positive) pulses generated by the two different topologies of the solid-state Marx modulators. According to the analysis, the stray capacitances influence the energy transfer from the Marx modulator capacitors to the load affecting the bipolar (negative and/or positive) pulse rise time. This paper deals with the structure design to reduce the influence of the stray capacitance and to improve the pulse rise time of these bipolar solid-state Marx modulators. A four-stage laboratory prototype of the two topologies has been assembled using 1200-V insulated gate bipolar transistors and diodes, operating with 1000-V dc input voltage and 1-kHz frequency, producing 4-kV bipolar pulses, with 5- \mu \texts pulse duration and 120-ns rise time, into a resistive load. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel five-level nested neutral point piloted (NNPP) converter and analyzes the operating principle of five-level NNPP converter. This paper presents a novel space vector pulse width modulation (SVPWM) algorithm based on gh coordinate for five-level NNPP converter. First, the common-mode voltage is reduced by choosing the appropriate redundant switching states. After that, the floating-capacitor voltage balance control strategy is presented. The appropriate switch combinations of each phase are determined by the control requirements of floating-capacitor voltages respectively and the hardware mapping method of the switching states is presented. Furthermore, the neutral-point voltage balance control strategy is presented. In order to balance the dc-link capacitor voltages, the seven-segment switching sequence is selected according to the control requirements of dc-link capacitor voltages and the neutral-point voltage regulatory factor is introduced to regulate the durations of the redundant switching states in a switching cycle. Finally, the validity of the novel SVPWM algorithm with decoupling control strategies of floating-capacitor voltages and dc-link capacitor voltages is verified by the experimental results of five-level NNPP converter under steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

Generally, for pulsed power applications with low jitter and high repetition rates, the use of semiconductor switches have replaced the traditional gap switches and thyratron circuits due to the limited lifetime of the thyratron and gap switches under such operating conditions. However, the limited ratings of these semiconductor switches require series and/or parallel stacking in order to handle high voltages and current levels associated with the discharge energy. Described in this paper is the design of a high voltage switch that uses a simple and reliable gate driver circuit for pulsed power application. In this design, the switch module is made up of insulated-gate bipolar transistor (IGBTs) and their gate driver circuits compactly fitted onto a single module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier synchronization of the switches, the simultaneous transfer of both signal and power for current boost are also described in this paper. A 120 nF capacitor bank energy was discharged using a configuration of the developed high voltage switch and a developed 15 kV, 1.5 kJ/s peak power capacitor charger, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging. [ABSTRACT FROM AUTHOR]

This paper studies the fault detection problem for a class of discrete-time switched linear systems under dwell-time (DT) constraints, using the parity space-based approach. The DT-dependent Lyapunov function is employed to investigate the asymptotic stability with less conservatism and to solve the constant ${l}_{2}$ -gain performance analysis problem, and its advantage is verified compared to the time-independent Lyapunov function approach. The corresponding switching residual generation is made to carry out the desired fault detection in the framework of parity space-based model. Then, by means of solving a generalized eigenvalue–eigenvector problem, the parity space matrices design is implemented. A quantitative relationship is established between the optimization performance and the choice of the parity space order. Two numerical examples are utilized to demonstrate effectiveness of the developed fault detection approach, including an application to switched RLC circuits. [ABSTRACT FROM AUTHOR]