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Piecewise affine (PWA) systems are attractive models that can represent various hybrid systems with local affine subsystems and polyhedral regions due to their universal approximation properties. The identification problem of PWA systems amounts to estimating the number of subsystems, parameters of each subsystem, and the corresponding polyhedral partitions via state-input vectors. In this paper, we propose a novel approach to address the online identification problem of continuous-time PWA systems in state-space form. Specifically, an online active mode recognition algorithm and a generalized integral concurrent learning identifier are presented to acquire the number of subsystems, the switching sequence, and the parameter of each subsystem. In addition, we develop the optimization problem for the polyhedral partition estimation, which is solved by using the estimated switching sequence and subsystem parameters. The effectiveness of the proposed identification approach is demonstrated via simulation results. [ABSTRACT FROM AUTHOR]

The Ring-AllReduce framework is currently the most popular solution to deploy industry-level distributed machine learning tasks. However, only about half of the maximum bandwidth can be achieved in the optimal condition. In recent years, several in-network aggregation frameworks have been proposed to overcome the drawback, but limited hardware information have been disclosed. In this paper, we propose a scalable fully-pipelined architecture that handles tasks like forwarding, aggregation and retransmission with no bandwidth loss. The architecture is implemented on a Xilinx Ultrascale FPGA that connects to 8 working servers with 10 Gb/s network adapters, and it is able to scale to more complicated scenarios involving more workers. Compared with Ring-AllReduce, using AllReduce-Switch improves the efficient bandwidth of AllReduce communication with a ratio of $1.75\times $. In image training tasks, the proposed hardware architecture helps to achieve up to $1.67\times $ speedup to the training process. For computing-intensive models, the speedup from communication may be partially hidden by computing. In particular, for ResNet-50, AllReduce-Switch improves the training process with MPI and NCCL by $1.30\times $ and $1.04\times $ respectively. [ABSTRACT FROM AUTHOR]

Large-scale millimeter-wave (mm-Wave) integrated phased array is the key technology to enable broadband 5G and satellite communications. This paper details the design considerations, challenges and trade-offs of mm-Wave integrated phased arrays based on bulk CMOS and multi-layer hybrid PCB technologies. Both technologies attain high yield and low cost for mass production. Important beamforming building blocks are addressed and compared in detail. Demonstrators of integrated phased arrays are presented from circuit to board levels. The 1024- and 4096-element integrated phased arrays achieve the EIRP of 72.5 and 84.0 dBm respectively. Finally, relevant phased-array transceivers and antennas from the recent literature are discussed. [ABSTRACT FROM AUTHOR]

This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling. [ABSTRACT FROM AUTHOR]

In this paper, the issue of open-switch faults of voltage source inverter (VSI) is studied, an adaptive fast voltage-based real-time open-switch fault location method is proposed. Firstly, for each switching period, the voltage deviation is calculated by the expected voltage and estimated actual voltage, they are obtained via the mixed logical dynamic model (MLDM) and measured currents, respectively. Then, the voltage deviation of each phase is employed as a fault variable. By this way, avoiding the use of additional hardware, and embedding easily in system. Furthermore, considering the impact of sampling error, parameter error, dead time, delay time, and transition time, the adaptive threshold is designed. Finally, simulations and experiments are executed to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Aiming at a class of switched uncertain nonlinear strict-feedback systems under the action of average dwell time switching signal, this paper proposes a novel adaptive neural network output feedback tracking control based on the consideration of the full state constraints. The controller is proposed based on neural networks. One of the key characteristics of the system discussed is that the state variables cannot be measured and the system states need to be kept within the constraint ranges. For the sake of estimating the unmeasured states, the observer is constructed. In order to ensure all states which are within the time-varying boundary, the tangent barrier Lyapunov function (BLF-Tan) is selected in the design process. The boundedness of the closed-loop signals with average dwell time is guaranteed by the designed controllers and all the states limit in their constrained sets. It has been proved that the output tracking error converge to a small neighborhood of zero. In addition, the significance of the presented control strategy is verified and tested by a simulation example. [ABSTRACT FROM AUTHOR]

This paper studies stability for a class of switched descriptor systems with state bumpless transfer performance and input bumpless transfer performance. Since the state jump is inevitable for switched descriptor systems when a switching occurs, to restrain the amplitude of the state jump induced by switchings, for the first time, the state bumpless transfer performance of switched descriptor systems is defined. Moreover, when switching occurs, to avoid the abrupt and large control input signals change damaging the system, we are the first to introduce the input bumpless transfer control scheme for switched descriptor systems. Furthermore, by using multiple Lyapunov functions, a sufficient condition is put forward to make sure the state bumpless transfer performance, input bumpless transfer performance and asymptotical stability for the closed-loop systems. Meanwhile, the switching rule and the state feedback controller are co-designed. In the end, a multiple inputs numerical example and an application on the DC motor model are used to exhibit the merit and validity of the presented control scheme. [ABSTRACT FROM AUTHOR]

In this paper, hybrid dynamical systems theory is applied to the analysis and control of switched converters with Pulse-Width Modulated (PWM) inputs. The system is described by a state-space model with continuous flows and discrete jumps, without averaged equations. The modulation effects are captured in full without using time-dependent signals, by enlarging the state vector to include the PWM waveform generation process. Furthermore, the sample-and-hold mechanism associated with the sampling frequency is also taken into account with this approach. A control law is proposed based on a Lyapunov function candidate. Furthermore, convergence sets and the steady state jitter, inherent to PWM-based controllers, are analyzed estimating limit sets for the augmented state. Consequently, output chattering can be bounded. By using hybrid dynamical system theory, the control designer gains a deeper understanding of the effect of modulation in the closed-loop dynamics, avoiding the problems associated with the use averaged models. Experimental results validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper addresses the problem of simultaneous fault detection and control (SFDC) for Markov jump systems (MJSs) over sensor networks. In order to save the bandwidth of the network, round-Robin protocol is adopted for the communication between the sensors and fault detection filter. First, to fully utilize the data of sensor networks, a new distributed system is developed especially for SFDC, and a residual system, which integrates the MJSs with the distributed SFDC system, is also established. Then, by constructing a mode-dependent Lyapunov functional, the conditions for distributed SFDC are derived, which can make the residual system asymptotically mean-square stable and meanwhile satisfy the prescribed H∞ performance requirements. Finally, comparison analyses are made by examples to illustrate the effectiveness and superiority of the proposed new design approach. [ABSTRACT FROM AUTHOR]

Data transfer across DRAM channels accounts for nearly a quarter of the total energy consumption of DDR4 DRAMs. Modern applications with high bandwidth requirements further increase channel energy consumption. However, channel energy consumption is dependent on data being transferred. Pseudo Open Drain (POD) asymmetric termination, used in current DDR4 systems, consumes energy only when 1’s are being transmitted over the channels. Many modern applications, including AI/ML ones are resilient to errors in data, and can work well with approximate data. This resilience can vary widely across and within applications, which provides a number of ways for exploiting these characteristics to save data transfer energy across the DRAM channel. However, all DRAM data encoding schemes have been targeted towards applications that require exact data and are not approximation resilient. In this paper, we propose Zero Aware Configurable Data Encoding by Skipping Transfer (ZAC-DEST), a data encoding scheme to reduce the energy consumption of DRAM channels, specifically targeted towards approximate computing and error resilient applications. ZAC-DEST exploits the similarity between recent data transfers across channels and information about error resilience behaviour of applications to reduce on-die termination and switching energy by reducing the number of 1’s transmitted over the channels. ZAC-DEST also provides a number of knobs for trading off application’s accuracy for energy savings, and vice versa, and can be applied to both training and inference. We apply ZAC-DEST to five machine learning applications. On average, across all applications and configurations, we observed a reduction of 40% in termination energy and 37% in switching energy as compared to the state of the art data encoding technique BD-Coder with an average output quality loss of 10%. We show that if both training and testing are done assuming the presence of ZAC-DEST, the output quality of the applications can be improved upto 9 × as compared to when ZAC-DEST is only applied during testing leading to energy savings during training and inference with increased output quality. [ABSTRACT FROM AUTHOR]

This paper presents the theory of a novel memcomputing paradigm based upon a memristive version of standard Cellular Nonlinear Networks. The insertion of a nonvolatile memristor in the circuit of each cell endows the dynamic array with the capability to store and retrieve data into and from the resistance switching memories, obviating the current need for extra memory blocks. Choosing the parameters of each cell circuit so that the memristors may undergo solely sharp transitions between two states, each processing element may be approximately described at any time as one of two first-order systems. Under this assumption, the classical Dynamic Route Map may be employed to synthesise and analyse the data storage and retrieval genes. A new system-theoretic methodology, called Second-Order Dynamic Route Map, is also introduced for the first time in this paper. This technique allows to study the operating principles of arrays with second-order processing elements, as is the case, in the proposed network, if the set up of cell circuit parameters induces analogue memristive dynamics. This paper shows how the novel tool may be adopted to investigate the operating mechanisms of a cellular array with second-order cells, which compute the element-wise logical OR between two binary images. [ABSTRACT FROM AUTHOR]

This paper deals with the problem of observer-based fault estimation (FE) for discrete-time nonlinear systems via a weighted switching approach. A pair of variable weights is introduced in an efficient but straight-forward way, and thus, the space spanned by the prescribed normalized fuzzy weighting function can be divided into a set of non-overlapping subspaces. A new fuzzy switching FE observer is proposed by designing exclusive FE observer gain matrices for each non-overlapping subspaces, and thus, less conservative off-line designed conditions for the proposed fuzzy switching FE observer are obtained than the previous results by adequately taking advantage of the characteristic information of each non-overlapping subspaces. More importantly, the process of on-line deciding the current subspace’s index at each sampled point is very straightway and some previous time-consuming online operation is avoided, i.e., it can be said that the on-line computational burden also is alleviated in this paper. Finally, the proposed theoretical result is applied to a tunnel diode circuit and the advantages over existing literature are validated by means of objective comparisons. [ABSTRACT FROM AUTHOR]

This paper addresses the finite-time event-triggered control problem for nonlinear semi-Markovian switching cyber-physical systems (S-MSCPSs) under false data injection (FDI) attacks. Compared with the traditional time-triggered mechanism, the proposed event-triggered scheme (ETS) can effectively avoid network resource waste. Considering the network-induced delay in the modeling, a closed-loop system model with time delay is established in the unified framework. By the use of a mode-dependent piecewise Lyapunov-Krasovskii functional (LKF), stochastic finite-time stability (SFTS) criteria are established for the resultant closed-loop system. Then, some solvability conditions are established for the desired finite-time controller in light of a linear matrix inequality framework. Finally, an application example of vertical take-off and landing helicopter model (VTOLHM) is provided to demonstrate the effectiveness of the theoretical findings. [ABSTRACT FROM AUTHOR]

Since the power consumption of data centers keeps increasing, a 48-V rack power distribution system replaces the conventional 12-V power bus to reduce the power delivery IR losses. Meanwhile, the 48 V needs conversion into 1 V or lower at the point-of-load for microprocessors. A 48V-to-12V DC-DC converter can serve as a first stage between the huge gap of 48V-to-1V, in a two-stage voltage regulator module (VRM). Thus, this paper presents a 3-phase resonant switched-capacitor (3Φ-ReSC) converter as the first stage of the VRM. Different from the reported solutions, 3-phase resonant operation reduces the current stress across each small-size GaN switch, and thus improves the power conversion efficiency. In addition, we also present the theoretical analysis and design procedures for the 3Φ-ReSC converter. We demonstrated the proposed 3Φ-ReSC converter with a 98% peak power efficiency at an output current of about 1 A, with a maximum output current of 10 A. [ABSTRACT FROM AUTHOR]

This paper presents a wide input range active rectifier using a bipolar-CMOS-DMOS (BCD) process with a high voltage conversion ratio (VCR) and high power conversion efficiency (PCE). The proposed rectifier ensures safe and robust operation under large input voltage variations, which can be caused by changes in the magnetic coupling or loading conditions. It supports an input voltage range 3–12 V with the adaptive delay-compensated active operation of the power switches. An active signal clamper and voltage-time hybrid gate control circuit with two compensation loops was proposed for the optimal gate transition of low-side NMOS switches. For high-side PMOS switches, a fully integrated low-power-consuming high-side driver is proposed to replace the conventional high-side gate driving structure. The proposed active rectifier was fabricated through a TSMC 0.18 μm BCD process. The measurement results show that the proposed rectifier achieves stable and well-delay-compensated active operation, resulting in a high VCR and PCE with a wide output power range from 4.5 to 288 mW. Peak VCR and PCE of 96.8% and 93.7%, respectively, were achieved. [ABSTRACT FROM AUTHOR]

A cascaded mode-switching sub-sampling PLL with quadrature dual-mode voltage waveform-shaping oscillator is proposed in this paper. The dual-mode voltage waveform-shaping oscillator is introduced to extend the tuning range and improve phase noise performance at mm-wave frequency, simultaneously. Meanwhile, the dual-mode quadrature topology is investigated to reduce the phase noise and quadrature phase error, compared to conventional quadrature oscillator. Then, the proposed oscillator is applied in a cascaded PLL with divider-less mode-switching sub-sampling loop, which can obtain the merits of high frequency-resolution, low loop noise, and wide frequency locking range. Both the dual-mode voltage waveform-shaping oscillator and the cascaded PLL are verified and fabricated in a 28-nm CMOS process. The FoM and FoMT of the oscillator at 10 MHz offset are −188.2 dBc/Hz and −200.7 dBc/Hz respectively. The proposed PLL prototype exhibits a frequency range from 22.8 to 33.9 GHz with a typical power consumption of 41.7 mW. The phase noise across the frequency band is from −104.1 to −108.2 dBc/Hz at 1 MHz offset. The jitter FoMj is −236.2 dB. [ABSTRACT FROM AUTHOR]

Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered and effectively modeled for the parasitics of the busbar, which is not accurate enough to evaluate the current imbalance for the busbar connected with SiC devices. This paper proposes accurate modeling of the effective parasitic parameter of laminated busbars with paralleled SiC MOSFETs. The model incorporates not only the self-inductance and resistance but also the complex mutual coupling effect of all the current paths. Moreover, a switching period is divided into two durations for accurate effective parasitic models, in which the busbar can have different effective models regarding one physical structure. Furthermore, for easy evaluation of the current balance, a single effective model, namely equivalent model, is derived for a physical structure by replacing the complex mutual network. A specific laminated busbar for EV inverter is analyzed to prove the above theory, which is validated by simulation and experiment separately. [ABSTRACT FROM AUTHOR]

Emerging computation-in-memory (CIM) paradigm offers processing and storage of data at the same physical location, thus alleviating critical memory-processor communication bottlenecks suffered by conventional von-Neumann architecture. Storage of data in a CIM architecture is analog in nature and therefore computation is performed in analog domain i.e. inputs and outputs are analog values. Since the outside computing environment is digital, analog-to-digital converters (ADC) are utilized to perform the output data conversion. However, ADC designs are bulky, power-hungry circuits that are prone to design variations and therefore, play an important role in determining the computing efficiency of CIM architectures. In this paper, we present a scalable and reliable integrate and fire circuit ADC (SRIF-ADC) design for CIM architectures, suitable for stringent power and area constraints. We devise a technique to stabilize the node receiving analog inputs that allows more rows to be activated at the same time, thereby increasing the operand size of input vectors. This allows better scalability in terms of higher parallelism of operations. We employ a self-timed variation-aware design approach and design measures to drastically reduce read disturb of memristor devices that address reliability issues related to the ADC design. In addition, we present a compact, built-in sample-and-hold circuit to replace the large-sized capacitance and built-in weighting technique to alleviate the need for post-processing. For multiply-and-accumulate (MAC) operation, our simulation results show that we can improve the computational parallelism by 3X as well as ADC conversion speed and energy efficiency are improved by 2X and 11.6X, respectively, compared to the state-of-the-art design. [ABSTRACT FROM AUTHOR]

To avoid the bumps of the control signal in the switching instants, this paper proposes a bumpless transfer control method which guarantees the continuous of control signal while keeping the asymptotic stability of the closed-loop system. Firstly, the presented bumpless transfer control method possesses a simple structure and meanwhile not have to redesign sub-controllers, which is easy to implement. Furthermore, the method is appropriate for either stable subsystems or unstable subsystems, and be suitable for either state feedback control or dynamic output feedback control. Moreover, we give the sufficient conditions of asymptotic stability for switched linear systems under bumpless transfer control for four cases. For the original switched system with stable subsystems under state or dynamic output feedback control, the stability conditions under mode-dependent average dwell time switching are derived. For the original switched system with unstable subsystems under state or dynamic output feedback control, which is stabilized by some certain switching laws, the stability conditions under the original switching law are given. Finally, a hardware-in-the-loop simulation of an aero-engine control system is employed to verify the effectiveness and superiority of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a novel T-type multilevel inverter (MLI) based on the switched-capacitor technique. The proposed inverter not only achieves that the maximum voltage stress of the switches is less than the input voltage but also has a voltage boost capability, which makes it suitable in high voltage applications. It is worth mentioning that the proposed inverter features two topology extension schemes which help it achieve a higher output level and voltage gain. With the merit of low voltage stress and reduced power devices, a seven-level inverter can be achieved using only two capacitors. Moreover, capacitor voltage self-balancing capability can simplify the complexity of the circuit and control. The topology, operating principle, modulation strategy and analysis of the capacitor of the inverter are presented. The superiorities of the proposed inverter are investigated by comparing with recently proposed hybrid MLIs and switched-capacitor MLIs. Finally, a seven-level prototype is constructed to validate the correctness of the theoretical analysis and the feasibility and effectiveness of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a 32-channel analog filterbank for front-end signal processing in sound classification systems. It employs a passive N-path switched capacitor topology to achieve high power efficiency and reconfigurability. The circuit’s unwanted harmonic mixing products are absorbed by the machine learning model during training. To enable a systematic pre-silicon study of this effect, we develop a computationally efficient circuit model that can process large machine learning datasets on practical time scales. Measured results using a 130 nm CMOS prototype IC indicate competitive classification accuracy on datasets for baby cry detection (93.7% AUC) and voice commands (92.4% average precision), while lowering the feature extraction energy compared to digital realizations by approximately $2\times $ and $10\times $ , respectively. The 1.44 mm2 chip consumes 800 nW, which corresponds to the lowest normalized power per simultaneously sampled channel in recent literature. [ABSTRACT FROM AUTHOR]

This paper proposes a novel artificial neural network (ANN) based control method for a dc/dc buck converter. The ANN is trained to implement optimal control based on approximate dynamic programming (ADP). Special characteristics of the proposed ANN control include: 1) The inputs to the ANN contain error signals and integrals of the error signals, enabling the ANN to have PI control ability; 2) The ANN receives voltage feedback signals from the dc/dc converter, making the combined system equivalent to a recurrent neural network; 3) The ANN is trained to minimize a cost function over a long time horizon, making the ANN have a stronger predictive control ability than a conventional predictive controller; 4) The ANN is trained offline, preventing the instability of the network caused by weight adjustments of an on-line training algorithm. The ANN performance is evaluated through simulation and hardware experiments and compared with conventional control methods, which shows that the ANN controller has a strong ability to track rapidly changing reference commands, maintain stable output voltage for a variable load, and manage maximum duty-ratio and current constraints properly. [ABSTRACT FROM AUTHOR]

This paper presents a low-profile and autonomous piezoelectric energy harvesting system consisting of an extraction rectifier and a maximum power point tracking (MPPT) circuit for powering portable electronics. Synchronized switch harvesting on capacitor-inductor (SSHCI) technique with its unique two-step voltage flipping process is utilized to downsize the ponderous external inductor and extend application areas of such harvesting systems. SSHCI implementation with small flipping inductor-capacitor combination enhances voltage flipping efficiency and accordingly attains power extraction improvements over conventional synchronized switch harvesting on inductor (SSHI) circuits utilizing bulky external components. A novel MPPT system provides robustness of operation against changing load and excitation conditions. Innovation in MPPT comes from the refresh unit, which continually monitors excitation conditions of piezoelectric harvester to detect any change in optimum storage voltage. Compared with conventional circuits, optimal flipping detection inspired from active diode structures eliminates the need for external adjustment, delivering autonomy to SSHCI. Inductor sharing between SSHCI and MPPT reduces the number of external components. The circuit is fabricated in 180 nm CMOS technology with 1.23 mm2 active area, and is tested with custom MEMS piezoelectric harvester at its resonance frequency of 415 Hz. It is capable of extracting 5.44x more power compared to ideal FBR, while using $100~\mu $ H inductor. Due to reduction of losses through low power design techniques, measured power conversion efficiency of 83% is achieved at 3.2 V piezoelectric open circuit voltage amplitude. Boosting of power generation capacity in a low profile is a significant contribution of the design. [ABSTRACT FROM AUTHOR]

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ($SS_{avg}$), off current (${I} _{OFF}$), and on current (${I} _{ON}$) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope. [ABSTRACT FROM AUTHOR]

This paper proposes a novel distributed fault-tolerant consensus tracking control design for multi-agent systems with abrupt and incipient actuator faults under fixed and switching topologies. The fault and state information of each individual agent is estimated by merging unknown input observer in the decentralized fault estimation hierarchy. Then, two kinds of distributed fault-tolerant consensus tracking control schemes with average dwelling time technique are developed to guarantee the mean-square exponential consensus convergence of multi-agent systems, respectively, on the basis of the relative neighboring output information as well as the estimated information in fault estimation. Simulation results demonstrate the effectiveness of the proposed fault-tolerant consensus tracking control algorithm. [ABSTRACT FROM AUTHOR]

In this paper, an efficient control strategy for three-phase four-switch inverter-fed Brushless DC Motor (BLDCM) drives with trapezoidal back Electromotive Force (EMF) is proposed. In the proposed approach, the outer control loop for adjusting the motor speed is designed using Model Predictive Control (MPC) while the inner control loop based on a hysteresis controller regulates the BLDC phase currents. To effectively adjust the current of the uncontrolled phase in the four-switch inverter, efficient switching strategies for motor and generator modes are suggested. The proposed control scheme achieves favorably low torque ripples and improves the speed transient response in terms of tracking error and speed overshoot/undershoot. Therefore, it can be an ideal candidate for low-cost low-power BLDCM applications. Also, the MPC-based speed control loop is tuned by solving a suitable cost function in an offline manner to minimize the real-time computational effort. Using the foregoing technique, it is shown that the implementation of the proposed MPC-based controller becomes as simple as the PI controller while the MPC-based controller achieves superior control performance. The proposed BLDCM drive scheme is experimentally verified in a Hardware-in-the-Loop (HiL) test setup with a 1200W BLDCM and dSPACE1104 development board. The experimental results demonstrate the benefits of the proposed drive system. [ABSTRACT FROM AUTHOR]

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter’s front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers’ inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC’s power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, the resilient control for linear discrete-time multi-agent networks subjected to unconfined cyber-attacks is investigated based on a data-driven method. Firstly, according to the evolution of the original network dynamics, a distributed data-driven estimation algorithm is presented. On this basis, a switching control law is proposed to solve the resilient consensus problem for the discrete-time multi-agent network under unconfined cyber-attacks. Further, some necessary and sufficient conditions for designing the resilient controllers are obtained by solving a nonlinear matrix inequation. Secondly, the proposed data-driven method is extended to study the resilient tracking control and formation control problems. Finally, some numerical simulations are provided to verify the effectiveness of the data-driven resilient control method. [ABSTRACT FROM AUTHOR]