Search

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

First-in first-out (FIFO) queues are ubiquitous building blocks in modern system-on-chips. Big FIFOs are often realized as static random access memories (SRAMs), and in many cases account for a significant portion of the area and power consumption of integrated circuits (ICs). Gain-cell embedded DRAM (GC-eDRAM) technology is an embedded memory alternative to the pervasive SRAM technology in ICs. It consumes less silicon area and less power than SRAM, but has the drawback of access blockage caused by its periodic data refreshing. In this paper we leverage the unique access patterns implied by the FIFO scheme to design a FIFO realized with GC-eDRAM. We show that such a FIFO is functionally indistinguishable from a FIFO realized with SRAM. The proposed FIFO has no access blockage time due to refresh, and no data integrity issues, and so can be used as an out-of-the-box replacement for FIFOs in existing and future designs, while providing as much as a $2\times $ reduction in both area and power as compared to SRAM. [ABSTRACT FROM AUTHOR]

This paper considers a large class of memristor circuits of arbitrary order, and containing an arbitrary number of flux- or charge-controlled memristors, for which a state equation (SE) description can be obtained. By means of the SEs, it is shown that the state space of each circuit can be decomposed in infinitely many manifolds, and that in the autonomous case, each manifold is positively invariant and is characterized by a different reduced-order dynamics and attractors. These results are the basis for extending the analysis to the non-autonomous case, where time-varying independent sources are present. In particular, the chief result obtained in this paper shows how to analytically design external pulses for programming memristor circuits, i.e., how invariant manifolds and attractors can be changed and controlled by applying suitable charge or flux sources via time-varying voltage and/or current pulses with finite time duration. The main results are obtained by relying on a recently introduced technique for the analysis of memristor circuits in the flux-charge domain. [ABSTRACT FROM AUTHOR]

In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18- $\mu \text{m}$ , 1-poly, and 4-metal CIS technology with a pixel array of $128 \times 160$ is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor $C_{\textit {FD}}$ on the floating diffusion node, which is remnant in VM. [ABSTRACT FROM AUTHOR]

This paper presents a fully on-chip mixed-mode low-dropout (LDO) regulator with improved regulation and transient responses. With the help of the digital regulation part, the supported maximum load current is significantly improved, while the chip area overhead is very small. A Miller compensation capacitor and a buffer stage are used to achieve stability and improve power MOS gate slew rate. The ultra-fast voltage buffer helps further improve the load transient recovery speed and reduce the chip area due to its wider voltage swing. A proof-of-concept LDO design is fabricated in a standard 0.18- $\mu \text{m}$ CMOS technology. The maximum load current is 150 mA, the output voltage is 1 V, and the dropout voltage is 0.2 V. The load regulation is 0.17 mV/mA, which is more than 480% improved over the traditional design without digital assistance. [ABSTRACT FROM AUTHOR]

This paper presents a 24-channel time-shared 8-bit digital-to-analog converter (DAC) with dual sampling to minimize the effective channel area of the column driver integrated circuit (IC) for high-resolution active-matrix organic light emitting diodes (AMOLED). The proposed time-shared DAC significantly reduces the effective channel area of the column driver IC, since a single high-speed DAC is shared among multi channels. The dual-sampling architecture for the output amplifiers also reduces the power consumption of the column driver IC, where the operating time of the time-shared DAC and the output amplifier is efficiently handled during the limited 1-horizontal time. The sampling accuracy of the dual-sampling architecture is improved by a simple dummy switch and a source follower. The proposed time-shared DAC with the dual sampling is implemented by a 0.13- $\mu \text{m}$ high-voltage complementary metal-oxide-semiconductor process and integrated in a 960-channel column driver IC, while the effective channel area of the column driver IC is 5520 $\mu \text{m}^{2}$. As a result of driving an 11-inch-wide quad extended graphics array AMOLED panel by using the prototype column driver IC, the panel uniformly generates a clear image. [ABSTRACT FROM AUTHOR]

This paper demonstrates a completely on-chip implementation of expansion and compression of continuous-time, wideband, analog pulses. The input pulse is fed to a continuous-time filter whose delay exceeds the pulse duration. Once the pulse is completely inside the filter, it is stored in the form of the filter’s state-variables, which can completely reconstruct the pulse. Instantaneously decreasing or increasing the filter’s bandwidth at this instant results in the output pulse being expanded or compressed, respectively, compared with when the bandwidth is unchanged. A 1.6 mm2, 370 mW, 0.13 $\mu \text{m}$ prototype has a delay filter whose bandwidth can be switched between 870 and 472 MHz. It achieves $1.8\times $ pulse expansion and $1.7\times $ pulse compression with an rms error which is 33 dB below the peak-peak pulse amplitude. [ABSTRACT FROM AUTHOR]

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

This paper presents a piezoelectric-based power management solution for battery-free wireless remote switches (BWSs). The proposed BWS IC, including a piezoelectric (PE) energy harvester and a buck converter, can collect the energy generated by a single PE-button press, and then supply that energy to a wireless transmitter to send a message. By combining a rectifier using the synchronized switch harvesting on inductor technique and a 6:1 series–parallel switched-capacitor converter, the proposed PE energy harvester can maximize the collected amount of energy, while supplying it at a low output voltage. In addition, by employing a switching-based start-up scheme and a variable ON-time pulse-frequency modulation scheme, the proposed buck converter can reduce the loss associated with charging the output capacitor during start-up, and then deliver the largest possible energy to the load, while maintaining low voltage ripples and high-power efficiency. A prototype BWS IC fabricated with high-voltage 250-nm CMOS technology was shown to be capable of harvesting a total energy of 246~\mu \textJ from a single button-pressing of a 300-mm2 lead magnesium niobate-lead titanate PE disc. More than 200~\mu \textJ was delivered to the load, sufficient to transmit a 4-B-long message via a 2.4-GHz wireless USB channel over a 10-m distance. [ABSTRACT FROM AUTHOR]

With reference to 48-V systems, used in electric and hybrid vehicles and for telecom and networking power supply, this paper presents the circuit/transistor-level design, implementation, and test of an inductorless dc/dc converter. Its architecture is a cascade of three switched-capacitor converters with step-up/down capabilities plus linear converters, working in parallel at the end of the cascade. It provides multiple regulated voltages, which are isolated from input failures. The design also includes on-chip control unit and a serial interface toward an external host. Experimental tests carried out on the chip, fabricated in 0.35- \mu \textm CMOS technology, proves that the design is suitable to face harsh operating environments, including the 48-V automotive one. Compared with the state-of-art, the proposed design stands for its wide input voltage regulation range, load/line regulation, power supply rejection ratio, and low electromagnetic interference emissions. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power compact analog circuit for processing time varying signals. The proposed circuit implements temporal differentiation, amplification and rectification, i.e., separation of outputs into on and off pathways. It is based on a hysteretic differentiator circuit, commonly used in neuromorphic vision sensors to implement temporal edge detection. This paper presents a thorough analysis of the original circuit and identifies the source of the problems and limitations it has for processing real-world sensory signals. The steps required to solve this problem are presented as well as an extended circuit with tunable gain and adaptable threshold that allows thresholding of small temporal changes (noise) and high-pass filtering of large temporal changes. The new circuit proposed is particularly suited for focal plane implementation of both gradient based and token based motion algorithms that require robust detection of temporal discontinuities. The circuit has been designed and successfully integrated into a 64 × 1 test prototype motion chip, fabricated in standard 350 nm CMOS technology. The paper provides extensive experimental characterization results. [ABSTRACT FROM PUBLISHER]

This paper presents a mutual capacitive touch screen panel (TSP) readout IC (ROIC) with a differential continuous-mode parallel operation architecture (DCPA). The proposed architecture achieves a high product of signal-to-noise ratio (SNR) and frame rate, which is a requirement of ROIC for large-sized TSP. DCPA is accomplished by using the proposed differential sensing method with a parallel architecture in a continuous-mode. This architecture is implemented using a continuous-type transmitter for parallel signaling and a differential-architecture receiver. A continuous-type differential charge amplifier removes the common-mode noise component, and reduces the self-noise by the band-pass filtering effect of the continuous-mode charge amplifier. In addition, the differential parallel architecture cancels the timing skew problem caused by the continuous-mode parallel operation and effectively enhances the power spectrum density of the signal. The proposed ROIC was fabricated using a 0.18-$\mu$m CMOS process and occupied an active area of 1.25 \text{mm}^{2}. The proposed system achieved a 72 dB SNR and 240 Hz frame rate with a 32 channel TX by 10 channel RX mutual capacitive TSP. Moreover, the proposed differential-parallel architecture demonstrated higher immunity to lamp noise and display noise. The proposed system consumed 42.5 mW with a 3.3-V supply. [ABSTRACT FROM PUBLISHER]

In this paper the power losses of efficient capacitive converters with multitude transfer ratio values are discussed. The loss mechanism circuits, based on general transposed series parallel (GTSP) topology, is studied and the losses are calculated, which in turn enables the “bottlenecks” to be identified and overcome. The calculations show that for a given number of switching cells the power losses of such converters are mainly dependent on the voltage conversion ratio, the topology function, the resistances of the switches in on and off states, the ESR of the capacitors, the switching frequency, the voltage drop, and the load. The theory explains the fact that was observed in experiments, that for low voltage conversion ratio values, efficiency decrease was measured. It is shown that for these low voltage ratio values the mechanism associated to the off resistance of the switches is more dominant and reduces the efficiency. This power loss estimation can be used as a powerful tool for the performance optimization of capacitive converters. The theoretical results are verified experimentally on a 10-cell GTSP converter prototype. The experimental results show good agreement with the proposed theory. [ABSTRACT FROM PUBLISHER]

This paper proposes a column-parallel two-step single-slope analog-to-digital converter (SS ADC) for high-frame-rate CMOS image sensors. The proposed two-step SS ADC circuit does not utilize an analog memory capacitor to store the value of the first ramp step. Instead, to handle problems such as the slope errors of the second ramp and the stored charge error from charge feed-through, it utilizes a very simple digital column circuit consisting of a coarse counter (coarse step counter) and a 4-to-16 decoder. The second ramp (fine ramp) slope has only one slope generator, regardless of the results of the first ramp decisions, to eliminate the slope mismatch between fine ramp slopes. A prototype sensor comprising 640 \times 480 pixels was fabricated with a 0.13-\mum CMOS process. The results of experiments conducted indicate that the proposed ADC can achieve a conversion time of 6.4 \mus at a main clock frequency of 62.5 MHz, which is 10.2 times faster than the conventional SS ADC. The maximum frame rate of the proposed VGA CMOS Image Sensor (CIS) is 320 frames per second (fps). Further, the proposed circuit employs redundancy error correction logic to calibrate the error between the coarse and fine steps. The total power consumption is 72 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital). The figure of merit (FoM) of the proposed VGA CMOS image sensor is 2.01 [e^-\ nJ]. [ABSTRACT FROM AUTHOR]

This paper proposes a multi-bit incremental analog-to-digital converter (ADC) based on successive approximation (SA) for column-parallel readout circuits. The proposed ADC suppresses the random noise and enhances the resolution by embedding the conventional SA ADC with an integrator and decimation filter. In addition, the operating speed is increased through the two-step operations of coarse conversion with the proposed ADC and fine conversion with the embedded SA ADC. A residue fitting method is adopted to adjust the residue voltage to the fine conversion range after the coarse conversion. The proposed ADC with 12-bit resolution was fabricated using a 0.13 \mum CMOS image sensor process with a pixel array that has an image format of 648 \times 488 and a pixel size of 5.6\ \mum\times 5.6\ \mum. The measured results show a random noise of 108 \muV, a dynamic range of 60.9 dB, a differential nonlinearity of +1.02/-0.34 least significant bit (LSB), and an integral nonlinearity of +0.64/-0.54 LSB. [ABSTRACT FROM AUTHOR]

Mismatch motivates many of the design decisions for binary weighted, ratiometric converters, such as successive approximation (SAR) analog-to-digital converters (ADC), but the statistical relationship between mismatch and signal-to-noise-plus-distortion ratio (SNDR) has not been precisely quantified. In this paper, we analyze the effects of capacitor mismatch in a binary weighted, charge redistribution SAR ADC and derive a new analytic expression relating capacitor mismatch and the effective-number-of-bits (ENOB). We then explore the statistics of this new expression and develop a model that accurately predicts yield in terms of ENOB. Finally, the major results of this paper are generalized into a simple and compact design equation that relates resolution, mismatch, and ENOB to yield for all binary weighted, ratiometric converters. The expressions derived in this paper offer practical insight into the relationship between mismatch and performance for all binary, weighted ratiometric converters with these results validated through numerical simulations. [ABSTRACT FROM PUBLISHER]

This paper proposes the design of a current-mode sample and hold circuit using subthreshold MOSFETs. The proposed circuit combines negative feedback and the compressive I-V characteristic of a class-AB weak inversion transconductor to achieve low switching error, high signal-to-noise ratio and high dynamic range from a low supply voltage and very low current consumption. The paper also provides a feedback analysis of current mode sample and hold circuits. Several design issues including circuit stability, mismatch, linearity, noise, and power consumption are discussed and a comparison of class-A and class-AB versions of subthreshold sample and hold circuits is made. The design verification of the proposed class-AB current mode sample and hold circuit is done by circuit simulations using 0.13 \mu \m CMOS model parameters. The results show that, from a 0.6 V supply and with a power consumption of 27.5 nW, the proposed circuit provides 73 dB signal-to-noise ratio, 77 dB dynamic range, and a figure of merit of 1.9 nW/MHz. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis and design of a quadrature charge-domain down-conversion sampling mixer with embedded finite-impulse-response (FIR), infinite-impulse-response (IIR), and 4-path bandpass filters. An in-depth investigation of the principles of periodic impulse sampling, periodic windowed sampling, and periodic N-path windowed sampling is presented and their characteristics are compared. A detailed mathematical treatment of charge-domain windowed samplers with built-in sinc, FIR and IIR filters is provided. A quadrature charge-domain sampler with embedded FIR, IIR, and 4-path band-pass filters is proposed and its performance including the effect of the non-idealities of devices is investigated. The proposed design is implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results demonstrate that the proposed design is tunable over 50–250 MHz frequency range. For an 100 MHz input, the proposed design exhibits 70 dB aliasing rejection, 60 dB stop band attenuation while consuming current of 145 \muA. The performance of the proposed design is further validated using the results of on-wafer measurement of the fabricated microchip. [ABSTRACT FROM AUTHOR]

In this paper a low-power switched-capacitor integrator based on a capacitive charge-pump (CP) is presented, and its practical effects are discussed. The CP integrator is employed as the first stage of a \Delta\Sigma ADC. The 0.13 \mum CMOS prototype of the CP based ADC achieves the same performance as a conventional ADC while consuming 66% lower OTA power in the front-end integrator. The CP based modulator realizes 87.8 dB SNDR, 89.2 dB SNR and 90 dB DR over a 10 kHz bandwidth with 148 \muW power consumption. The conventional ADC has similar performance but dissipates 241 \muW. The energy required per conversion-step for the CP based ADC (0.369 pJ/step) is almost 40% lower than that of the conventional ADC (0.607 pJ/step). [ABSTRACT FROM PUBLISHER]

As externally powered microsystems become more common, designers need better tools to understand power delivery systems such as non-resonant capacitive coupling. In this paper we present the first general method which allows a designer to easily model power delivery through capacitive coupling. The method uses a power iteration technique which allows one to analyze systems when the time to charge the coupling capacitor is longer than a charge cycle, enabling us to analyze a greater range of systems than previously possible. In fact, we are able to model the entire system with an equivalent resistance. We show that our model accurately reproduces both static and dynamic characteristics of the exact solution and that this model is general, in that it is valid for capacitor charge times that are longer as well as shorter than a charge cycle. This model also reveals several regions of operation where different parameters (e.g., capacitance, frequency and series resistance) dominate, allowing the designer to quickly and intuitively understand the design space for capacitive power transfer. [ABSTRACT FROM PUBLISHER]

Photovoltaic (PV) energy harvesting is commonly used to power autonomous devices, and maximum power point tracking (MPPT) is often used to optimize its efficiency. This paper describes an ultra low-power MPPT circuit with a novel sample-and-hold and cold-start arrangement, enabling MPPT across the range of light intensities found indoors, which has not been reported before. The circuit has been validated in practice and found to cold-start and operate from 100 lux (typical of dim indoor lighting) up to 5000 lux with a 55 cm2 amorphous silicon PV module. It is more efficient than non-MPPT circuits, which are the state-of-the-art for indoor PV systems. The proposed circuit maximizes the active time of the PV module by carrying out samples only once per minute. The MPPT control arrangement draws a quiescent current draw of only 8 μA, and does not require an additional light sensor as has been required by previously reported low-power MPPT circuits. [ABSTRACT FROM PUBLISHER]

The linearity of a high-resolution pipelined analog- to-digital converter (ADC) is mainly limited by the capacitor mismatch and the finite operational amplifier (OPAMP) gain in the multiplying-digital-to-analog converter (MDAC). Therefore, high resolution pipelined ADCs usually require high-gain OPAMP and large capacitors, which causes large ADC power. In recent years, various nonlinear calibration techniques have been developed to compensate both linear and nonlinear error from MDCAs so that low-power MDACs with small capacitors and low-gain OPAMP can be used. Hence, the ADC power can be greatly reduced. This paper introduces a novel interpolation- based digital self-calibration architecture for pipelined ADC. Compared to previous techniques, the new architecture is free of adaptation. Hence, long convergence is not needed. The complexity of the digital processor is also considerably lower. The new architecture does not use backend ADC to measure MDACs. Hence, it is free of the accumulation of measurement error, which leads to more accurate calibration. A prototype ADC with the calibration architecture is fabricated in a 0.35 3.3 V CMOS process. The ADC samples at 20 MS/s. The calibration improves the ADC DNL and INL from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590 kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio(SNDR) and spurious-free dynamic range (SFDR) from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB respectively. The 11.8-ENOB 20 MS/s ADC consumes 56.3 mW power with 3.3 V supply. The 0.78 pJ/step figure-of-merit (FOM) is low for designs in 0.35 CMOS processes. At the Nyquist frequency, SNDR of the calibrated ADC drops 8 dB due to the slow settling of the first pipeline stage. [ABSTRACT FROM PUBLISHER]

Scaled CMOS proves to be suitable for the design of transceiver ICs at micro- and millimeter-waves. The effort is presently toward compact and low-power solutions in view of integrating several transceivers on the same chip enabling phased array systems. In this paper we present a 24 GHz receiver, based on a subharmonic direct conversion architecture, designed in a 65 nm node. The local oscillator takes advantage of the half frequency operation proving significantly lower power consumption when compared to conventional solutions running at received frequency. Stacked switches for subharmonic down-conversion are passive to save voltage room, current driven and loaded by a transresistance amplifier. Optimum biasing of the switches allows maximizing linearity while saving power in the baseband. The integrated LNA matching network is the bottleneck toward low sensitivities. The LNA design trades-off power consumption, gain and sensitivity. Detailed insights into implementation issues, critical in a single-ended topology where both forward and return signal paths have to be supported, are provided. The chip consumes 78 mW and occupies 1.4 mm^2 of active area. Experiments show: 30.5 dB gain, 6.7 dB NF, -13 dBm IIP3. [ABSTRACT FROM PUBLISHER]

A general transposed series-parallel topology of a switched-capacitor converter is presented and analyzed in this paper. This topology evolved from the conventional series-parallel through rectangular matrices based topologies to partial arbitrary matrices which are constructed of different size strings of capacitors to arbitrary matrices, based on a bank of equally valued capacitors. Theoretically, these topologies have a large number of dc/dc voltage ratios, which lead to the capability to achieve very accurate fixed dc/dc voltage ratios. These topologies also have the capability for “fine tuning” when voltage regulation is necessary. For the general transposed series-parallel topology, it is shown that the number of possible dc/dc voltage transfer ratios escalates exponentially with an addition of each capacitor as the sum of partition functions. Therefore, relatively fewer components are required for an assumed accurate voltage ratio. Dispersion of parameters in the capacitance value is considered. Small ripple analysis, losses calculations and efficiency considerations are also discussed. Simulations are performed for 2.2 and 2.25 voltage ratios. The simulations are in good agreement with the theoretical calculations. [ABSTRACT FROM PUBLISHER]

A wide variety of voltage mixers and samplers are implemented with similar circuits employing switches, resistors, and capacitors. Restrictions on duty cycle, bandwidth, or output frequency are commonly used to obtain an analytical expression for the response of these circuits. This paper derives unified expressions without these restrictions. To this end, the circuits are decomposed into a polyphase multipath combination of single-ended or differential switched-series-RC kernels. Linear periodically time-variant network theory is used to find the harmonic transfer functions of the kernels and the effect of polyphase multipath combining. From the resulting transfer functions, the conversion gain, output noise, and noise figure can be calculated for arbitrary duty cycle, bandwidth, and output frequency. Applied to a circuit, the equations provide a mathematical basis for a clear distinction between a “mixing” and a “sampling” operating region while also covering the design space “in between.” Circuit simulations and a comparison with mixers published in literature are performed to support the analysis. [ABSTRACT FROM PUBLISHER]

This paper compares the performance among two-phase switched-capacitor multipliers to identify the optimum topology with the smallest circuit area. The optimum number of stages is calculated for every multiplier to minimize the circuit area under the condition that a certain current is outputted with a given output voltage. Then, the circuit areas of the serial–parallel, linear (LIN), Fibonacci, and 2^N multipliers are compared. Results show that the LIN cell is the best for integration because of the smallest total capacitor area and the highest current efficiency under the assumption that the parasitic capacitance is not smaller than 10% of the multiplier capacitance, and the Fibonacci cell is the best for discrete application because of the minimum number of capacitor components with moderate current efficiency under the assumption that the parasitic capacitance is not larger than 1% of the multiplier capacitance. [ABSTRACT FROM PUBLISHER]

Ground bouncing noise produced during the SLEEP to ACTIVE mode transitions is an important challenge in standard multithreshold CMOS (MTCMOS) circuits. The effectiveness of different noise-aware combinational MTCMOS circuit techniques to deal with the ground-bouncing-noise phenomenon is evaluated in this paper. An intermediate relaxation mode is investigated to gradually dump the charge stored on the virtual lines to the real ground distribution network during the SLEEP to ACTIVE mode transitions. The dependence of ground bouncing noise on the sleep transistor size and temperature is characterized with different power-gating structures. The peak amplitude of ground bouncing noise is reduced by up to 76.62% with the noise-aware techniques without sacrificing the savings in leakage power consumption as compared with standard MTCMOS circuits in a 90-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

In this paper, a fully integrated OC-192 clock-and-data recovery (CDR) architecture in standard 0.18-μm CMOS is described. The proposed architecture integrates the typically large off-chip filter capacitor by using two feed-forward paths configuration to generate zero and pole and satisfies SONET jitter requirements with a total power dissipation (including the buffers) of 290 mW. The measured RMS jitter of the recovered data is 0.74 ps with a bit-error rate less than 10-12 when the input pseudo-random bit sequence (PRBS) data pattern has a pattern length of 215 - 1 and a total horizontal eye closure of 0.54 peak-to-peak unit interval (UIpp) due to the added intersymbol interference distortion by passing data through 9-in FR4 printed circuit board trace. The chip exceeds SONET OC-192 jitter tolerance mask, and high-frequency jitter tolerance is over 0.31 UIpp by applying PRBS data with a pattern length of 231 - 1. [ABSTRACT FROM AUTHOR]

In this paper, two novel negative impedance converter (NIC) structures are proposed. One of the introduced NICs exhibits the property of both simultaneously reduced nonideal gain and parasitic impedance effects. Also, the other one shows the property of reducing only parasitic impedance effects and employs only second-generation current conveyors; accordingly, it can be realized with commercially available active devices such as AD844s. In order to show the performance of the introduced NICs, a versatile circuit employing a minimum number of active and passive elements for all the analog filters and lossy inductor simulators is developed. The proposed topology with appropriate component and input port selections gives four kinds of lossy grounded simulated inductors as well. Further, the presented multipurpose circuit is the first one that provides both of the current-mode and voltage-mode standard universal filter responses as well as synthetic inductors from the same topology. The developed topology employing only grounded capacitors can also realize transimpedance-mode low-pass and bandpass responses simultaneously; thus, it is convenient for integrated circuit (IC) realization. Likewise, positive lossy inductor simulators consist of a grounded capacitor. Nevertheless, the realized circuit requires a single resistive component-matching condition. Simulation results using SPICE program and experimental results are included to verify the theoretical ones. [ABSTRACT FROM AUTHOR]

This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (ac) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-μm CMOS technology, consuming only 65 μA of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures. [ABSTRACT FROM AUTHOR]

Jump resonance is a phenomenon where smooth changes in the input of a nonlinear filter lead to abrupt changes in its output. For over 50 years, research has defined the region of operation where jump resonance can occur so that this region may be avoided by limiting the signal amplitude of operation. This paper provides an intuitive understanding of jump resonance and predicts the behavior of the system in the jump resonance regime. This allows for further tradeoffs between system behavior and power consumption for highly power-efficient filtering systems. Our technique is verified against experimental data. Then we present a system that gracefully adapts its quality factor, avoiding jump resonance in a way qualitatively similar to biology. Finally, we demonstrate an integrated circuit realization. [ABSTRACT FROM AUTHOR]

Thermal noise represents a major limitation on the performance of most electronic circuits. It is particularly important in switched circuits, such as the switched-capacitor (SC) filters widely used in mixed-mode CMOS integrated circuits. In these circuits, switching introduces a boost in the power spectral density of the thermal noise due to aliasing. Unfortunately, even though the theory of noise in SC circuits is discussed in the literature, it is very intricate. The numerical calculation of noise in switched circuits is very tedious, and requires highly sophisticated and not widely available software. The purpose of this paper is twofold. It provides a tutorial description of the physical phenomena taking place in an SC circuit while it processes noise (Sections II-III). It also proposes some specialized but highly efficient algorithms for estimating the resulting sampled noise in SC circuits, which need only simple calculations (Sections IV-VI). A practical design procedure, which follows directly from the estimate, is also described. The accuracy of the proposed estimation algorithms is verified by simulation using SpectreRF. As an example, it is applied to the estimation of the total thermal noise in a second-order low-distortion delta-sigma converter. [ABSTRACT FROM AUTHOR]

An analytical approach to evaluate performance of analog integrated circuits and make a comparative study in different technology nodes is presented. To provide closed-form solutions, this article proposes using $\mathscr {C} = \text {C}/\text {I}_{\text {DS}}$ as an independent design variable, where C refers to any physical or parasitic capacitance associated with a Field-Effect Transistor (FET) biased at IDS. The proposed $\mathscr {C}$ -based methodology is used to study speed versus power trade-offs in both continuous-time (CT) and discrete-time (DT) circuits. Predictive Technology Models (PTMs) have been used to study performance of both MOSFET and FinFET (i.e. FET) devices in different technology nodes. This analysis shows that FinFET transistors exhibit a wider medium-inversion region compared to MOSFET devices, making them more convenient for high-speed and low-power designs. Additionally, this study proves that a lower sub-threshold slope factor results in an improved energy-efficiency of analog circuits. [ABSTRACT FROM AUTHOR]

In this article, first integrated circuit (IC) implementation of parallel synchronized switching harvesting on inductor (p-SSHI) is presented for triboelectric energy harvester targeting 1 Hz to 5 Hz mechanical motions. It is accompanied by on-chip buck and switched capacitor DC-DC converters, all capable of handling 70 V levels. Unlike piezoelectric harvesters, triboelectric nanogenerators (TENGs) can produce very high open-circuit voltages; thus, the proposed system utilizes this property within the technology limits to maximize the extracted power. An in-house manufactured TENG using steel and polytetrafluoroethylene (PTFE) is modeled for sub-5 Hz motions. The energy is extracted and stored in an external capacitance until its voltage reaches 70 V, which is achieved in three press-and-release mechanical cycles. 70-to-2 V down conversion is carried on by 70-to-10 V buck converter followed by a 10-to-2 V switched capacitor DC-DC converter. A chip is manufactured in $0.18~\mu \text{m}$ HV BCD process with an active area of 6.25 mm2. End-to-end peak efficiency is measured as 32.71% for 1 Hz motion with a 722 $\mu \text{W}$ total power delivery to the load for 4 ms. [ABSTRACT FROM AUTHOR]

A design methodology for an area-optimized integrated charge pump is described suitable for on-chip high-voltage reverse bias of single-photon avalanche diodes (SPADs). The high-voltage generation block is implemented in a general-purpose 0.13- $\mu \text{m}$ CMOS process and is capable of generating a maximum regulated output voltage of 17.7 V from an input of 1.8 V. An ON–OFF regulation scheme with dynamic charging and discharging capability of the charge pump provides fast recovery of the output bias voltage during SPAD transients, where overshoot and undershoot must both be corrected during active quench and reset. Following a SPAD avalanche current pulse, the measured transient recovery time is 500 ns from a 150-mV overshoot and a 500-mV undershoot to reach 99% of steady-state output. The implemented SPAD bias generation system occupies 0.175-mm2 chip area, without requiring an off-chip load capacitor. [ABSTRACT FROM AUTHOR]

Conventional capacitance-to-digital converters (CDCs) suffer limitations either on narrow capacitance range or low resolution for jitter-induced noise and high power consumption. In order to avoid these limitations, a 13-b 1 pF–10 nF generic CDC is presented. In the proposed CDC with the oversampled $\Delta \Sigma $ modulation, the zero-crossing-based circuits (ZCBCs) are used to replace the operational transconductance amplifier to avoid feedback loop stability issues. However, the ZCBCs inevitably incur the non-idealities and thus, a novel calibration scheme is presented for efficient non-ideality-error cancellation. In addition, for the purpose of making the proposed CDC sufficiently intelligent to adapt to a wide capacitance-sensing range, an adaptive auto-range mechanism is proposed. The above three techniques complement each other and work as a whole leading to the proposed CDC with wide range, high resolution, high linearity, and low power consumption. A prototype fabricated using 0.18- $\mu \text{m}$ CMOS technology is experimentally verified using a MEMS capacitive humidity sensor. The measurement results show that the CDC achieves a 13-b root-mean-square noise equivalent resolution with a 128- $\mu \text{s}$ conversion time and a 230 fJ/conversion-step figure of merit. The calibration scheme enhances the linearity from 7 to 11.4 b in the 1 pF–10 nF compatible capacitance range. [ABSTRACT FROM AUTHOR]

A new fS/4 bandpass $\Delta \Sigma$ -analog-to-digital converter (ADC) architecture is realized by feeding back the delayed quantization noise inherently produced by a pipelined ADC. Designed in a 55-nm global foundry (GF) LP-CMOS process, the prototype ADC sampling at 250 MHz achieves an Signal-to-Noise+Distortion Ratio of 72, 75.8, 80.1, and 85.3 dB in a 15.64-, 7.82-, 3.91-, and 1.953-MHz band, respectively, around a center frequency of 62.5 MHz with only first-order noise shaping, while consuming 103 mW of power, and achieving a maximum figure-of-merit of 158 dB. [ABSTRACT FROM PUBLISHER]

The longitudinal waveform relaxation (WR) proposed by Gander and Ruehli converges faster than the classical WR method. For the former, a free parameter \alpha is contained, which has a significant effect on the convergence rate. The optimization of this parameter is thus an important issue in practice. Here, we apply this new WR method to the fractional-order RC circuits, and optimize such a parameter at the continuous and discrete levels (this gives two parameters \alpha ^{c}_{\mathrm{ opt}} and \alpha ^{d}_{\mathrm{ opt}} ). We consider three simple but widely used convolution quadrature for discretization, based on the implicit-Euler method, the two-step backward difference formula, and the trapezoidal rule, and we derive the parameter \alpha ^d\mathrm{ opt} for each quadrature. Interestingly, it is found that for the former two quadratures, the optimized parameter \alpha ^d\mathrm{ opt} results in a much better convergence rate than \alpha ^c\mathrm{ opt} , while for the quadrature based on the trapezoidal rule, \alpha ^d\mathrm{ opt} and \alpha ^c\mathrm{ opt} result in the same convergence rate. [ABSTRACT FROM AUTHOR]

A new 96 \times 96 array of 30\ \mu\text{m}\times 30\ \mu\text{m} readout integrated circuit (ROIC) with an individual pixel tunable bias control is demonstrated. Detailed IC design, test structures, readout circuit building blocks, and applied techniques are discussed. The new ROIC is capable of providing a large voltage swing for the bias in both positive and negative polarities to each individual pixel, independently. These enhanced functionalities are achieved by modifying a capacitive transimpedance amplifier (CTIA) CMOS ROIC architecture. An FPGA-based test bench has also been developed to test and characterize the new ROIC system, for which software and hardware are described in detail. The test chip has been fabricated with 2P4M 0.35 \mu\text{m}$ high-voltage CMOS technology, where the bias voltage range is ±5 V and the output swing range is ±3.9 V. The demonstrated ROIC is an ideal infrastructure for implementation of region of interest enhancement and a solid base for infrared multispectral acquisition targeting an infrared retina. [ABSTRACT FROM PUBLISHER]

Memristor-based circuits are widely exploited to realize analog and/or digital systems for a broad scope of applications (e.g., amplifiers, filters, oscillators, logic gates, and memristor as synapses). A systematic methodology is necessary to understand complex nonlinear phenomena emerging in memristor circuits. The manuscript introduces a comprehensive analysis method of memristor circuits in the flux-charge $(\varphi,q)$-domain. The proposed method relies on Kirchhoff Flux and Charge Laws and constitutive relations of circuit elements in terms of incremental flux and charge. The main advantages (over the approaches in the voltage-current $(v,i)$-domain) of the formulation of circuit equations in the $(\varphi,q)$-domain are: a) a simplified analysis of nonlinear dynamics and bifurcations by means of a smaller set of ODEs; b) a clear understanding of the influence of initial conditions. The straightforward application of the proposed method provides a full portrait of the nonlinear dynamics of the simplest memristor circuit made of one memristor connected to a capacitor. In addition, the concept of invariant manifolds permits to clarify how initial conditions give rise to bifurcations without parameters. [ABSTRACT FROM PUBLISHER]

We present a DC-DC converter for photovoltaic (PV) applications that is suitable for distributed power conversion obtained by transferring part of the electronics from the inverter to the module. The proposed circuit implements a high-efficiency four-phase interleaved boost converter employing relatively low-valued inductive and capacitive components. Its compact realization is made possible thanks to the innovative design of a dedicated integrated circuit (IC) embedding the power MOS switches and performing the converter control section as well as the Maximum Power Point Tracking (MPPT) algorithm. The solution is designed for a maximum delivered power of 300 W and to work with an MPPT voltage between 9 V and 36 V, with maximum allowed panel current of 9 A. The area of the complete printed-circuit board is 4 cm\,\times\,7 cm. Experimental measurements show that the average power conversion efficiency is between 93% and 99% and that the MPPT efficiency is always greater than 99.7%. [ABSTRACT FROM PUBLISHER]

A new approach to an analog ultra-low power medium-resolution vision chip design is presented. The prototype chip performs low-level image processing algorithms in real time. Only a photo-diode, MOS switches and two capacitors are used to create an analog processing element (APE) that is able to realize any convolution algorithm based on a full 3\,\times\,3 kernel. The proof-of-concept circuit is implemented in 0.35 \mum CMOS technology, and contains a 64\,\times\,64 SIMD matrix with embedded APEs. The matrix dissipates less than 0.3 mW (less than 0.1 \muW per APE) of power under 3.3 V supply, and its image processing speed is up to 100 frames/s. [ABSTRACT FROM AUTHOR]

The stability of a stepwise waveform of an adiabatic charge recycling circuit with tank capacitors is investigated. We propose a new tank capacitor circuit with two-string capacitor arrays. We experimentally confirmed the stability of the five-step waveform from the tank capacitors. The voltage changes of tank capacitors in the experiment are consistent with the simulation. The power consumption is reduced to one-fifth due to the five-step waveform. We analyze the stability using matrix theory. The results prove that the step waveform is stable for any circuit topology. Moreover, we consider the effects of conductors fixed at a certain voltage and floating conductors and confirm the system is stable using matrix theory. [ABSTRACT FROM AUTHOR]

A memristor emulator which imitates the behavior of a \ TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp∼\ TiO2 memristor model in real circuit. [ABSTRACT FROM AUTHOR]

Online adaptive equalization is proposed to calibrate channel mismatch errors in time-interleaved (TI) analog-to-digital converter (ADC) arrays with a linear reference path. Code-domain filters are shown to be effective in removing interchannel as well as intrachannel nonlinearity and mismatch errors, including offset, gain, and differential nonlinearity (DNL) and integral nonlinearity (INL) mismatches. An 8-bit, 600-MS/s, 0.13- μm CMOS prototype measured a signal-to-noise plus distortion ratio (SNDR) of 31.0/47.4 dB, a spurious-free dynamic range (SFDR) of 32.8/63.6 dB, a DNL of 1.30/0.30 LSBs, and an INL of 1.70/0.23 LSBs in lab testing without/with equalization, respectively. [ABSTRACT FROM PUBLISHER]

Presented is a design of a mixed signal integrator, consisting of a traditional analog integrator (op-amp with capacitor in feedback) augmented with comparators, logic, counter registers, and a precharged capacitor that can be switched into, and out of, the input of the analog integrator. This device integrates with analog, but stores results in analog and digital. Whenever an analog integrator voltage equals or exceeds a threshold voltage, an amount of charge equivalent to the threshold voltage is cleared from the feedback capacitor of the analog integrator, and the counter register is incremented or decremented accordingly. With the threshold voltage representing one in a counting system, these actions convert the integrator contents to ±1. At any instant, the counter register holds the integer portion of the integral, and the analog integrator holds any fractional portion, permitting the integral to be internally stored as a real number. The mixed signal integrator accumulates integral beyond supply rails without op-amp saturation; has analog integrator bandwidth that extends into the limited gain low frequency region; avoids drift due to low pass filter effects and unbalanced input biases; and exhibits no sampled data or discrete system effects. Tests on a PCB prototype verified the design. [ABSTRACT FROM PUBLISHER]

A successive approximation analog-to-digital converter (ADC) architecture is presented that programs its comparator threshold at runtime to approximate the input signal via binary search. While targeting medium resolutions and speed, the threshold configuring (TC) ADC achieves low power consumption and small area occupation by using a fully dynamic configurable comparator and an asynchronous controller, with no need for a highly linear feedback D/A converter. The TC-ADC embeds its own references, and relies on a minimal amount of passive components or calibration loops. A 6-bit prototype implementation in 90-nm digital CMOS technology achieves 32-dB SNDR at 50 MS/s and consumes 240 μW from 1-V analog and 0.7-V digital supplies. This results in 150 fJ/conversion-step in a core area occupation of only 0.0055 mm . [ABSTRACT FROM AUTHOR]

Electrocorticography (ECoG) implants have recently demonstrated promising results towards potential use in brain-computer interfaces (BCIs). Spectral changes in ECoG signals can provide insight on functional mapping of sensorimotor cortex. We present a 6.4 \muW electrocorticography (ECoG)/electroencephalography (EEG) processing integrated circuit (EPIC) with 0.46 \mu Vrms noise floor intended for emerging brain-computer interface (BCI) applications. This chip conditions the signal and simultaneously extracts energy in four fully programmable frequency bands. Functionality is demonstrated by tuning the four bands to important frequency bands used by ECoG/EEG applications: \alpha (8–12 Hz), \beta (18–26 Hz), low-\gamma (30–50 Hz), and \gamma (70–100 Hz). Measured results from in vivo ECoG recording from the primary motor cortex of an awake monkey are presented. [ABSTRACT FROM PUBLISHER]

A two-stage fully differential CMOS amplifier comprising inverters as input structures and employing self-biasing techniques is presented. The proposed amplifier benefits from an optimum compensation through time-domain optimization which permits achieving high energy efficiency. Moreover, it achieves the highest efficiency of its class and although it relies on a quasi-class-A topology, it is comparable to class-AB amplifiers. Detailed circuit analyses such as differential-mode, common-mode feedback, noise, slew rate, and input/output range are carried out. Based on these analyses, a manual design methodology and a genetic algorithm based optimization are presented. Finally, the most relevant experimental results for an integrated circuit prototype designed in a 0.13 \mu \m 1.2 V standard CMOS technology are shown. [ABSTRACT FROM PUBLISHER]