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In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

Analyzing the timing properties of asynchronous systems is essential for characterizing their performance and power. Previous work on timing showed that such systems under and-causality and fixed delay exhibit periodicity properties. We give a different graph-based rigorous proof of the exact timing behavior of more general classes of such systems, and conclude their exact periodicity property, where each of the signal transition will occur with the same period after finite occurrences. We established our results under weaker assumption about system connectivity/topology, and this paper provides the theoretical foundation, for the exact periodicity property to be applied and exploited in circuits containing a combination of synchronous and asynchronous components. We provide simulation-based results for several typical asynchronous circuit topologies to quantify this time period in practical circuits. We also provide an extension of our analysis and methods to the case of bounded delay systems. A key result that is a consequence of our analysis is that asynchronous circuits can be integrated with synchronous logic via a metastability-free interface, thereby eliminating the high-overhead synchronizers when an asynchronous circuit is fully surrounded by synchronous logic. [ABSTRACT FROM PUBLISHER]

This paper proposes an adaptive model of modular multilevel converter (MMC) for electromagnetic transient (EMT) simulations. The model is applicable to MMCs with arbitrary numbers of half-bridge and full-bridge submodules. The proposed design includes average value model, arm equivalent model, and detailed equivalent model. It allows smoothly transitioning from one model to another during time-domain simulations depending on the desired accuracy and execution time constraints. Modifications required in conventional MMC models to achieve smooth transitions are presented in the paper. Time-domain initialization methods are developed for each constituting model, including initialization of the appropriate control system blocks. Validity and effectiveness of the proposed adaptive model is demonstrated using EMT simulations of 401-level MMC-HVDC system. [ABSTRACT FROM AUTHOR]

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits. [ABSTRACT FROM AUTHOR]

A diagnostic test generation procedure targets fault pairs in a set of target faults with the goal of distinguishing all the fault pairs. When a fault pair cannot be distinguished, it prevents the diagnostic test set from providing information about the faults, and consequently, about defects whose diagnosis would have benefited from a diagnostic test for the indistinguishable fault pair. This is referred to in this paper as a diagnostic hole. This paper observes that it is possible to address diagnostic holes by targeting different but related fault pairs, possibly from a different fault model. As an example, this paper considers the case where diagnostic test generation is carried out for single stuck-at faults, and related bridging faults are used for addressing diagnostic holes. Considering fault detection, an undetectable single stuck-at fault implies that certain related bridging faults are undetectable. This paper observes that, even if a pair of single stuck-at faults is indistinguishable, a related pair of bridging faults may be distinguishable. Based on this observation, diagnostic tests for pairs of bridging faults are added to a diagnostic test set when the related single stuck-at faults are indistinguishable. Experimental results of defect diagnosis for defects that do not involve bridging faults demonstrate the importance of eliminating diagnostic holes. [ABSTRACT FROM AUTHOR]

Exploring the design space of computer architectures generally consists of a trial-and-error procedure where several architectural configurations are evaluated by using simulation techniques. The final goal of the multiobjective design space exploration (DSE) process is the identification of architectural configurations optimal for a set of target objective functions, typically power consumption, and performance. Simulations are computationally expensive making it rather hard to efficiently explore the design space to identify high-quality configurations in an acceptable exploration time when relying solely on a single-core machine to run simulations. To tackle this problem, engineers proposed solutions based on either: 1) the use of approximate analytic performance models to prune the suboptimal regions of the design space by reducing the number of simulations to run or 2) the use of parallel computing resources to run different simulations concurrently. In this paper we demonstrate that, to efficiently speedup the DSE process while fully exploiting the parallel computing infrastructure, we need to combine the two techniques together in a structured manner. In this paper, we investigate this issue and we propose a DSE solution that exploits approximate analytic prediction models to improve the simulation schedule on a parallel computing environment rather than to prune the number of simulations. Experimental results demonstrate that the proposed technique provides a speedup from 1.26\boldsymbol \times to 4\boldsymbol \times with respect to other parallel state-of-the art DSE techniques. [ABSTRACT FROM PUBLISHER]

3-D integrated circuits (3-D ICs) are expected to have shorter wirelength, better performance, and less power consumption than 2-D ICs. These benefits come from die stacking and use of through-silicon vias (TSVs) fabricated for interconnections across dies. However, the use of TSVs has several negative impacts such as area and capacitance overhead. To predict the quality of 3-D ICs more accurately, TSV-aware 3-D wirelength distribution models considering the negative impacts were developed. In this paper, we apply an optimal buffer insertion algorithm to the TSV-aware 3-D wirelength distribution models and present various prediction results on wirelength, delay, and power consumption of 3-D ICs. We also apply the framework to 2-D and 3-D ICs built with various combinations of process and TSV technologies and predict the quality of today and future 3-D ICs. [ABSTRACT FROM PUBLISHER]

An enhanced full-wave method based on circuit analysis is presented in this paper, where the whole set of modes TEmnp and TMmnp are taken into account. The modeling of a split cylinder resonator is done with two circuit networks of one and three ports, characterized by their generalized admittance matrix, which is computed making use of the mode matching method. The improved full-wave circuit method has been applied to the accurate determination of dielectric properties of materials. The proposed method has been validated through comparisons with other published models and also with measurements. [ABSTRACT FROM PUBLISHER]

The random telegraph noise (RTN) is becoming more serious in advanced technologies. Due to the unpredictability of the physical phenomenon, RTN is a good randomness source for true random number generators (TRNG). In this paper, we build fundamental randomness models for TRNGs based on single trap- and multiple traps-induced RTN. We theoretically derive the autocorrelation coefficient, bias, and bit rate for RTN-based TRNGs. Two representative RTN-based TRNG schemes are simulated to verify the proposed randomness models. An oscillator-based TRNG is also studied based on the theoretical randomness model of multiple traps-induced RTN. We also provide basic guidelines for designing RTN-based TRNGs. [ABSTRACT FROM PUBLISHER]

The support for local variables in SystemVerilog assertions significantly enhances its expressive power. Handling local variables in analog and mixed-signal (AMS) extensions of assertion languages is tricky due to the dense time interpretation of AMS assertions, and has not been adequately treated in existing literature. This paper presents an approach for interpreting local variables in AMS assertions during simulation and a tool flow that works with standard mixed-mode simulators. [ABSTRACT FROM AUTHOR]

In this paper, we will focus on the problem of modeling global or die-to-die variation in semiconductor devices. We will demonstrate that the process corner-based approach for modeling global variation, which has been the dominant approach for design validation, has fundamental limitations in predicting the circuit performance variation. We will then show how a full statistical model of variation can accurately predict circuit behavior and discuss some of the challenges in moving from a corner-based design to statistical simulations. [ABSTRACT FROM AUTHOR]

With the continuous drive toward integrated circuits scaling, efficient performance modeling is becoming more crucial yet more challenging. In this paper, we propose a novel method of hierarchical performance modeling based on Bayesian co-learning. We exploit the hierarchical structure of a circuit to establish a Bayesian framework where unlabeled data samples are generated to improve modeling accuracy without running additional simulation. Consequently, our proposed method only requires a small number of labeled samples, along with a large number of unlabeled samples obtained at almost no-cost, to accurately learn a performance model. Our numerical experiments demonstrate that the proposed approach achieves up to ${3.6 \times }$ runtime speed-up over the state-of-the-art modeling technique without surrendering any accuracy. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

In this paper, a compact SPICE model of flexible transition metal dichalcogenide field-effect transistors (TMDFETs) is developed with considering effects when scaling the transistor size down to the 10-nm technology node. The model supports different transistor design parameters such as width, length, oxide thickness, and various channel materials, as well as the applied strain, which enables the evaluation of transistor- and circuit-level behavior under process variation and different levels of bending. Extensive device-level simulations are performed using this model, and TMDFETs are compared with different Si- and graphene-based devices. We performed circuit-level simulations, and reported the delay, power, and EDP of the benchmark circuits. Effects from process variation are also evaluated. These cross-technology studies show that TMDFET’s power is comparable to the low-power multigate devices (about 0.4% lower). The delay and EDP are 60% and 2.3% higher than the graphene-based devices, respectively. The developed compact model would enable SPICE-level circuit simulation for early assessment, design, and evaluation of futuristic TMDFET-based flexible circuits targeting advanced technology nodes. [ABSTRACT FROM AUTHOR]

With ever increasing design complexities, traditional cycle-accurate or instruction-set simulations are often too slow or too inaccurate for system prototyping in early design stages. As an alternative, host-compiled or source-level software simulation has been proposed, but existing approaches have largely focused on timing simulation only. In this paper, we propose a novel source-level simulation infrastructure that provides a full range of performance, energy, reliability, power and thermal (PERPT) estimation. Using a fully automated, retargetable back-annotation framework, intermediate representation code is statically annotated with timing, energy and resource accesses information obtained from low-level references at basic block granularity. The annotated model is natively compiled and combined with a cache model and occupancy analyzer to provide target performance, energy, soft-error vulnerability and power estimations. Finally, generated power traces are fed into thermal models for further temperature estimation. Comprehensive evaluations of our source-level models for PERPT estimations are performed. We applied our approach to PowerPC targets running various industry benchmark suites. source-level simulations are evaluated for different PERPT metrics and with cache models at various levels of detail to explore the speed and accuracy tradeoffs. More than 90% accuracy can be achieved for timing, energy, reliability and power estimation, and an average error of 0.05 K exists in steady-state thermal estimation. Simulation speeds range from 180 to 5740 MIPS for different types of metrics at different abstraction levels. [ABSTRACT FROM AUTHOR]

A novel method to accurately and efficiently model the interaction between radiating devices is proposed. Whereas previous work of the authors dealt with singleport devices (antennas), this paper constitutes an important extension to actual multiport devices, as such paving the way for electromagnetic interference assessment of real-life (sub)systems early in their design cycle. The method solely relies on the knowledge of the radiation patterns of the different ports of the devices, which can either be measured or simulated using a solver of choice. These patterns are then used to compute the electromagnetic interaction between the devices that may be positioned in each other's radiative near-field (Fresnel region) or far-field (Fraunhofer region). Furthermore, in the model, their relative positions and orientations can be altered at a very low computational cost. The technique is thoroughly validated and illustrated, demonstrating its appositeness to study the electromagnetic compatibility behavior of the multiport devices. [ABSTRACT FROM AUTHOR]

Quantum computation is a promising emerging technology which, compared to conventional computation, allows for substantial speed-ups, e.g., for integer factorization or database search. However, since physical realizations of quantum computers are in their infancy, a significant amount of research in this domain still relies on simulations of quantum computations on conventional machines. This causes a significant complexity which current state-of-the-art simulators try to tackle with a rather straight forward array-based representation and by applying massive hardware power. There also exist solutions based on decision diagrams (i.e., graph-based approaches) that try to tackle the exponential complexity by exploiting redundancies in quantum states and operations. However, these existing approaches do not fully exploit redundancies that are actually present. In this paper, we revisit the basics of quantum computation, investigate how corresponding quantum states and quantum operations can be represented even more compactly, and, eventually, simulated in a more efficient fashion. This leads to a new graph-based simulation approach which outperforms state-of-the-art simulators (array-based as well as graph-based). Experimental evaluations show that the proposed solution is capable of simulating quantum computations for more qubits than before, and in significantly less run-time (several magnitudes faster compared to previously proposed simulators). An implementation of the proposed simulator is publicly available online at http://iic.jku.at/eda/research/quantum_simulation. [ABSTRACT FROM AUTHOR]

Rapid increase in operating frequencies and power density necessitate the importance of examining electromagnetic compatibility/electromagnetic emissions (EMEs) from high-frequency and high-power integrated circuits (ICs). In this paper, a simulation method is demonstrated to study the EME using gallium nitride high electron mobility transistor power amplifier IC chip as a device under test. Simulation model is developed by collaborating a high-frequency structure simulator with a Keysight Advance Design System for simulation of three-dimensional layout of IC. The simulated EME results are verified with experimental measurement results; the hotspots obtained with higher EME as identified by a near-field scanner and simulation results are identical. With this simulation method, optimization is done using a response surface methodology to reduce the EME for the IC chip. It is found that small changes in the IC layout can make a significant difference in the EME. Simulation model developed with RSM optimization technique opens a gateway for the IC industry to investigate EME of their chip design without going through a costly and time-consuming process of fabrication for testing its EME. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient method for extracting the coupling capacitance between through-silicon via (TSV) and the adjacent redistribution layer (RDL) interconnections based on the scalar potential integral equation and cylindrical accumulation mode basis functions. As the numerical integration of capacitance is very complicated, we employed an approximation based on the use of double-exponent transformation and the segmentation method to improve the calculation efficiency. The maximum deviation is less than 5%. The scalability of the proposed model is verified by performing parametric studies on different physical design parameters; the results show good agreement between the proposed model and the numerical simulation. Additionally, we studied several different structures of TSVs with and without RDLs to explain the influence of the coupling capacitance between TSVs and RDLs on crosstalk noise. [ABSTRACT FROM AUTHOR]

In this paper, the plane-pair partial element equivalent circuit method coupled with the field equivalence principle is developed and applied to calculate the radiated fields of multilayer power planes. The proposed method can be used to solve near-field and far-field radiation problems for multilayer parallel-plane structures with decoupling capacitors. The proposed method is validated by full-wave simulation and experiment. In addition, the proposed method achieves ten times higher computational efficiency than the full-wave simulation. [ABSTRACT FROM AUTHOR]

Adiabatic logic is an energy-efficient technique, however, the time required in the design, validation, and debugging increases manifold for large-scale adiabatic system designs. In this endeavor, we present a hardware description language (HDL)-based modeling approach for 4-phase adiabatic logic design. The paper highlights the drawbacks of the existing approaches and proposes a new approach that captures the timing errors and detects the circuit’s invalid operation due to mutually exclusive inputs being violated. We develop a model library containing the function of the four periods used in the trapezoidal power-clock and the adiabatic logic gates. The validation and verification of the proposed approach were done on the ISO-14443 standard benchmark circuit, a 16-bit cyclic redundancy check (CRC) circuit. The system modeled using HDL shows the timing agreement with the transistor-level SPICE simulations. The novel use of the four periods of a power-clock improves the robustness and reliability for the design and verification of large adiabatic systems. [ABSTRACT FROM AUTHOR]

In this paper, a robust model-based battery state-of-charge (SOC) estimating algorithm is proposed with a novel approach based on combination of multimodels data-fusion technique and particle filter (PF). The proposed method is particularly adapted for SOC estimation under real-time conditions and the presence of measurement noise. In this innovative approach, multiple battery models have been used in order to accurately estimate a battery SOC. During the estimation process, the measured battery terminal voltage is compared with the multiple battery models output to generate individual residual, which is then used to calculate the weight of estimated value from each battery model. This weight, which represents the accuracy of observation equation of each battery model, is inversely proportional to the residual. The estimated SOC values from different models are then fused and the weights of estimated values from each battery model are adjusted dynamically using PF and weighted average methodology, in order to calculate the final SOC estimation of the battery. For each proposed battery model, the corresponding parameter-tuning strategies are also presented. In addition, the proposed method has been validated by experimental results. The results demonstrate that the proposed multimodels-based algorithm can be implemented effectively for real-time application, and achieve better accuracy than single model-based methods. [ABSTRACT FROM AUTHOR]

The aim of this paper is to present a six-phase induction machine (6PIM) model based on the so-called circuit-oriented approach suitable for simulation of electrical faults on both stator and rotor sides. This specific model has been developed by using only resistances, inductances, and controlled voltage sources. The coupling effects between both the stator and the rotor have been taken into account by the computation of stator–rotor mutual inductances. The model has been developed under the MATLAB/Simulink environment in order to have a universal tool that is easy to use with any control techniques. With this model, it is possible to simulate any type of electrical faults during the motion by closing or opening corresponding switches. The performances of the model have been validated by comparing simulation and experimental results of a 90-W 14-V 50-Hz two-pole 6PIM operating with different levels of load torque in healthy and faulty modes. Furthermore, this model has been associated to a fault-tolerant speed control method in phase opening occurrences in order to test the model accuracy. [ABSTRACT FROM AUTHOR]

With the steady growth of chip complexity and shrinking feature size, multiple challenges are emerging for transistor level circuit simulation. Compact SPICE models are a fundamental part of circuit verification, serving as a bridge between the semiconductor design and foundry. It is also an integral part of SPICE simulators, which directly affects tool performance and therefore design schedule. While the advanced 3-D technology nodes deliver superior level of scalability, simulation cost is rapidly increasing due to the computational complexity introduced by device model equations and the number of iterations required for numerical methods. In this paper, an efficient solution is proposed to reduce the computational cost associated with UC Berkeley BSIM-CMG device model evaluation, by applying robust Verilog compiler and computer algebra techniques to the device model equations. As a result of this implementation, simulation time reduction is up to 72% for complex blocks of the latest generation processor design. [ABSTRACT FROM PUBLISHER]

To improve the efficiency of direct solution methods in SPICE-accurate integrated circuit (IC) simulations, preconditioned iterative solution techniques have been widely studied in the past decades. However, it is still an extremely challenging task to develop robust yet efficient general-purpose preconditioning methods that can deal with various types of large-scale IC problems. In this paper, based on recent graph sparsification research we propose circuit-oriented general-purpose support-circuit preconditioning (GPSCP) methods to dramatically improve the sparse matrix solution time and reduce the memory cost during SPICE-accurate IC simulations. By sparsifying the Laplacian matrix extracted from the original circuit network using graph sparsification techniques, general-purpose support circuits can be efficiently leveraged as preconditioners for solving large Jacobian matrices through Krylov-subspace iterations. Additionally, a performance model-guided graph sparsification framework is proposed to help automatically build nearly-optimal GPSCP solvers. Our experiment results for a variety of large-scale IC designs show that the proposed preconditioning techniques can achieve up to 18 \times runtime speedups and 7 \times memory reduction in DC and transient simulations when compared to state-of-the-art direct solution methods. [ABSTRACT FROM PUBLISHER]

In this paper, a fast H(M) magnetostatic hysteresis model is presented, tested, and used in Simulink and partial element equivalent circuit (PEEC) environments. The model is primarily designed to achieve full compatibility with the current 3-D PEEC formalism for nonlinear isotropic magnetic materials, compatibility not met by any direct model. The capabilities of the proposed model are shown in stand-alone configuration and as a core of circuit components within the Simulink environment. Its effectiveness in the 3-D PEEC formulation is then demonstrated. [ABSTRACT FROM AUTHOR]

In the dark silicon era, a fundamental problem is given a real-time computation demand, how to determine if an on-chip multiprocessor system is able to accept this demand and to maintain its reliability by keeping every core within a safe temperature range. In this paper, a practical thermal model is described for quick chip temperature prediction. Integrated with the thermal model, we present a mixed integer linear programming (MILP) model to find the optimal task-to-core assignment with the minimum chip peak temperature. For the worst case where even the minimum chip peak temperature exceeds the safe temperature, a heuristic algorithm, called temperature-constrained task selection (TCTS), is proposed to optimize the system performance within chip safe temperature. The optimality of the TCTS algorithm is formally proven. Extensive performance evaluations show that our thermal model achieves an average prediction accuracy of 0.0741 °C within 0.2392 ms. The MILP model reduces chip peak temperature of ~10 °C comparing with traditional techniques. The system performance is increased by 19.8% under safe temperature limitation. Due to the satisfying scalability of our MILP formulation, the chip peak temperature is further decreased by 5.06 °C via the TCTS algorithm. The feasibility of this systematical technique is testified in a real case study as well. [ABSTRACT FROM PUBLISHER]

Near-threshold and sub-threshold voltage designs have been identified as possible solutions to overcome the limitations introduced by energy consumption in modern very large scale integration circuits. However, as we approach sub-10 nm transistor technology, aggressive voltage, and gate length scaling will reduce the reliability of logic circuits due to the increasing impact of noise and variability effects. Therefore, designers need new tools to simulate logic circuits in the presence of noise. Time-domain analysis helps understand how transient faults affect a circuit and can guide designers in producing noise-resistant circuitry. However, standard approaches to modeling intrinsic noise sources in the time domain are computationally expensive. Moreover, small noise-driven fluctuations in electron occupation of circuit nodes introduce time-varying biasing point fluctuations, increasing the modeling complexity. To address these challenges, this paper introduces a new approach to modeling thermal noise and random telegraph signal noise directly in the time domain by developing and solving a series of stochastic differential equations. In comparisons to traditional SPICE-based simulations, our approach can provide three orders of magnitude speedup in simulation time without sacrificing accuracy. Moreover, we introduce a novel, iterative threshold-crossing algorithm, aimed at the efficient sampling of rare noise transients. We show that Monte-Carlo simulations based on this approach can detect rare high-amplitude single event transients that would be impossible to uncover with standard transient simulators. [ABSTRACT FROM PUBLISHER]

With the increasing penetration of renewable energies in modern power grids, large amounts of voltage source converters (VSCs) have been installed, resulting in many new transient issues. Electromagnetic transient (EMT) simulation plays an essential role in investigating and solving the issues. However, simulation efficiency plunges when object grids contain multiple VSCs, because each switching event incurs modification or re-decomposition of the network matrix in traditional EMT programs, which is very time-consuming. Thus, this paper proposes a VSC model represented by pulse voltage-current source pairs. Accordingly, a unidirectional loosely-coupled solving algorithm is designed. Synthetically, the authors propose a novel EMT simulation approach adaptive to systems with multiple VSCs. The proposed approach keeps the computational network invariable while sufficiently considers detailed switching events, thereby significantly improving the simulation efficiency of the EMTP program without precision loss. [ABSTRACT FROM AUTHOR]

In comparison to single-model based trackers, the model-ensembled tracking strategy has shown a substantial adaptivity in handling various tracking challenges. As the performance of the tracker has been improved by combining different model outputs linearly, the insufficient consideration of each ensemble member’s contribution still limits the tracking performance to be further enhanced. As the performance of the tracker has been improved by combining different model outputs linearly, the insufficient consideration of each ensemble member’s contribution still limits the tracking performance to be further enhanced. In this paper, a tracking strategy based on multiple instance models regression (MIMRT) is proposed with a unified ensembling scheme. By formulating the tracking initialization with an instance model, the encoding process for an object’s specific detail is performed corresponding to the samples in each frame. The advantage of this operation is to guarantee the model frame-wise discrimination of short-term training, as well as to evaluate the reliability of each instance model by utilizing the long-lifetime samples obtained throughout the whole tracking procedure. To finalize the proposed tracking, all the independent instance models attached to the learned regression coefficients are ensembled with respect to the long-lifetime samples. This also effectively bridges the instance model as a latent variable to investigate a semantic association between the tracking model and the overall samples. A comprehensive experiment has shown that the proposed tracker is able to achieve superior performances compared to the state-of-art tracking approaches on both short-term datasets (e.g., OTB2013, OTB100, VOT2016, UAV123) and long-term dataset (UAV20L). [ABSTRACT FROM AUTHOR]

A cyber-physical system (CPS) is an integration of computation with physical processes whose behavior is defined by both computational and physical parts of the system. In this paper, we present a view of the challenges and opportunities for design automation of CPS. We identify a combination of characteristics that define the challenges unique to the design automation of CPS. We then present selected promising advances in depth, focusing on four foundational directions: combining model-based and data-driven design methods; design for human-in-the-loop systems; component-based design with contracts, and design for security and privacy. These directions are illustrated with examples from two application domains: smart energy systems and next-generation automotive systems. [ABSTRACT FROM AUTHOR]

Fast front pulses from lightning and switching conditions produce transient overvoltages and dielectric stresses that can result in premature deterioration or failure of transformer windings. Predicting these conditions in new transformer designs requires the implementation of internal winding models. This paper analyzes the accuracy and performance of different transformer winding models available in the literature, by means of comparisons with time- and frequency-domain measurements on a 2000-turns disk-type winding prototype, as well as evaluation of the computer time needed by each model to perform the corresponding simulation of the same prototype. The results show that including the frequency dependence of the model parameters is a decisive factor to accurately reproduce the measurements. They also show that a lumped parameter model described in a turn-by-turn basis can provide accurate results and requires shorter simulation time than a distributed parameter model. [ABSTRACT FROM AUTHOR]

This paper proposes a novel hardware implementation strategy to achieve low-cost design for digital predistortion of radio frequency power amplifiers (PAs) using a modified decomposed vector rotation-based behavioral model. To make the model hardware friendly, we first modify the model into a subdecomposed format, which significantly reduces the computational complexity in model extraction. We then reassemble the coefficients and propose a simple digital implementation structure for real-time signal processing in the transmit path. A new dual-direction coordinate rotation digital computer design is also proposed to simultaneously calculate both magnitude and e^j\theta n values to facilitate the model implementation. To validate hardware implementation, a wideband signal is employed to evaluate the performance with a Doherty PA. Experimental results show that the proposed approach can achieve comparable performance with much lower system complexity compared with that using the conventional approaches. [ABSTRACT FROM PUBLISHER]

Six-phase electrical machines are often found in special purpose applications, such as vehicular, ship, and aircraft power systems, and are now becoming considered in renewable energy generation. For design and analysis of such power systems, accurate and numerically efficient models are required for various transient simulation programs. Recently, a constant-parameter voltage-behind-reactance (CPVBR) model has been developed for magnetically linear six-phase synchronous machines as an alternative to the conventional qd0 and VBR machine models. In this paper, a saturable CPVBR model is presented for six-phase machines, which includes the main flux saturation and achieves magnetically decoupled and constant RL interfacing branches. The new magnetically decoupled CPVBR (DCPVBR) model has many advantages for implementation in commonly available simulation programs where it can be easily interfaced with inductive and/or power-electronic circuit elements. The proposed DCPVBR model is demonstrated to have improved computational performance compared to the conventional qd0 and VBR models. [ABSTRACT FROM AUTHOR]

Given a chip that produced a faulty output response to a test set, a defect diagnosis procedure produces a set of candidate faults that is expected to identify the defects that are present in the chip. The accuracy of the set of candidate faults is higher when the set is smaller or when its overlap with the defects that are present in the chip is larger. To increase the accuracy of a set of candidate faults, this paper describes an approach where several sets of candidate faults are computed based on different subsets of the test set. The subsets are obtained by removing small numbers of tests from the complete test set. The result is sets of candidate faults that are similar but not identical. The number of sets where a fault appears yields a confidence level that the fault actually belongs in a set of candidate faults. New sets of candidate faults are defined based on the confidence levels obtained. The smallest set of candidate faults can be used as the final result of defect diagnosis, or the sets can be used for ranking the candidates. Experimental results for benchmark circuits demonstrate the effectiveness of this approach. [ABSTRACT FROM PUBLISHER]

This paper proposes a numerical solution of the nonlinear equations that describes the hysteretic behavior of ferromagnetic materials. From the proper definition and solution of these equations, an equivalent circuit model for a ferromagnetic core is developed and proposed. The results obtained from the equivalent circuit are compared with those obtained by a rigorous numerical solution. [ABSTRACT FROM AUTHOR]

In this paper, we propose an efficient oscillation-diminishing cubic Hermite spline interpolation method for the table-based transistor model approximation. We use the cubic Hermite spline interpolation to ensure the continuity of the derivatives. Oscillation-diminishing techniques are proposed to reduce the oscillations (bumps) of interpolations such that both convergence and accuracy are significantly improved. Further, the oscillation-diminishing schemes do not rely on any real derivatives. Therefore, the proposed method can be used to build table models from measured data of the physical devices, where the real derivatives are not always available. In the proposed method, an adaptive approach is employed to generate the nonuniform interpolation grids such that the interpolation accuracy is guaranteed and the memory requirement is minimized. We also propose a novel combined exponential extrapolation method for off-state (leakage) current, which exactly follows the exponential-decay characteristic of that current. Test simulations on several classic industrial analog and mixed-signal circuits show that the proposed method can achieve high accuracy with lower computational cost compared with existing table-based model approximation methods. [ABSTRACT FROM PUBLISHER]

This paper presents photovoltaic-oriented nodal analysis (PVONA), a general and flexible tool for efficient spatially resolved simulations for photovoltaic (PV) cells and modules. This approach overcomes the major problem of the conventional Simulation Program with Integrated Circuit Emphasis-based approaches for solving circuit network models, which is the limited number of nodes that can be simulated due to memory and computing time requirements. PVONA integrates a specifically designed sparse data structure and a graphics processing unit-based parallel conjugate gradient algorithm into a PV-oriented iterative Newton–Raphson solver. This first avoids the complicated and time-consuming netlist parsing, second saves memory space, and third accelerates the simulation procedure. In the tests, PVONA generated the local current and voltage maps of a model with $316 \times 316$ nodes with a thin-film PV cell in 15 s, i.e., using only 4.6% of the time required by the latest LTSpice package. The 2-D characterization is used as a case study and the potential application of PVONA toward quantitative analysis of electroluminescence are discussed. [ABSTRACT FROM AUTHOR]

A wideband equivalent-circuit model of coaxial-annular through-silicon vias (TSVs) for three-dimensional (3-D) integrated circuits is proposed in this paper. Rigorous closed-form formulas for the resistance and inductance of coaxial-annular TSVs are derived by computing the longitudinal electrical field in Cu and the longitudinal magnetic vector potentials in ${\rm{SiO}}_{2}$ and Si substrate with Bessel functions. The equivalent-circuit model can appropriately capture the skin effect in Cu as well as eddy-current effect in Si substrate. The proposed model is verified using 3-D full-wave field solver high frequency simulator structure, showing that it can yields highly accurate results up to 100 GHz. [ABSTRACT FROM AUTHOR]

This paper describes a novel approach for passivity enforcement of compact dynamical models of electrical interconnects. The proposed approach is based on a parameterization of general state-space scattering models with fixed poles. We formulate the passivity constraints as a unitary boundedness condition on the \(\mathcal {H}_\infty \) norm of the system transfer function. When this condition is not verified, we use it as an explicit constraint within an iterative perturbation loop of the system state-space matrices. Since the resulting optimization framework is convex but nonsmooth, we solve it via localization based algorithms, such as the ellipsoid and the cutting plane methods. The proposed technique solves two critical bottleneck issues of the existing approaches for passivity enforcement of linear macromodels. Compared to quasi-optimal schemes based on singular value or Hamiltonian eigenvalue perturbation, we are able to guarantee convergence to the optimal solution. Compared to convex formulations based on direct Bounded Real Lemma constraints, we are able to reduce both memory and time requirements by orders of magnitude. We demonstrate the effectiveness of our approach on a number of cases for which existing algorithms either fail or exhibit very slow convergence. [ABSTRACT FROM PUBLISHER]

The ball grid array (BGA) structure is the interconnection between package to printed circuit board and the discontinuity from BGA affects the performance for the whole link path in the high-speed digital system. So, it is important to accurately model the BGA structures. In current methods, the current distribution of conductors is treated as isotropic. However, the pitch size of solder balls is comparable to the diameter. The current is no longer uniformly distributed. In this paper, a fast modal-based approach is developed to accurately and efficiently capture the proximity effect. Image theory is also applied in the proposed approach to reduce the computational domain from 3-D structure to 2-D. The matrix reduction approach is applied to obtain the physical loop inductance. The lumped capacitance is obtained in [1]. A $\pi $ topology equivalent circuit model for the BGA structure is built. Good agreement between the equivalent circuit model and full-wave simulation can be achieved up to 40 GHz. [ABSTRACT FROM AUTHOR]

This paper proposes the method of using bias-free vertical-cavity surface-emitting lasers (VCSELs) for in-circuit monitoring and effects-diagnosis of digital electronic equipment undertaking HPEM susceptibility test. A circuit level model for typical single mode VCSEL and standard I/O buffer information specification model for I/O ports of digital ICs are built to simulate VCSEL's load effects to the digital IC from specific logic families, as well as VCSEL's light output. Simulation results show that VCSELs connected in parallel to IC's I/O ports can be lighted up and its light output can achieve remote status-monitoring of I/O ports’ states in real time, while its load effects to the I/O ports are light enough not to deteriorate its signal integrity or disturb the circuit's normal operation. An experiment is performed on commercial mini sized drone to validate this study and demonstrate this method's feasibility and advantages in equipment level HPEM susceptibility test. [ABSTRACT FROM AUTHOR]

Invertible logic using a probabilistic magnetoresistive device model has been recently presented that can compute functions in bidirectional ways and solve several problems quickly, such as factorization and combinational optimization. In this article, we present a design framework for invertible logic circuits. Our approach makes use of linear programming to create a Hamiltonian library with the minimum number of nodes for small invertible-logic functions. In addition, as the device model is approximated based on stochastic computing in synthesizable SystemVerilog, a faster simulation using the compiled SystemC binary is realized than a conventional SPICE-level simulation and is verified using field-programmable gate array (FPGA) as prototyping. Using our design framework, several invertible-logic circuits are designed and emulated (verified) in SystemC, exhibiting five order-of-magnitude faster simulation than conventional work. [ABSTRACT FROM AUTHOR]

Test generation for hard-to-reach states is important in functional verification. In this paper, we present a path constraint solving-based test generation method (PACOST) which operates in an abstraction-guided semiformal verification framework to cover hard-to-reach states. PACOST combines concrete simulation and symbolic simulation on the design under verification for path constraint extraction and mutation, and uses a sequential path constraint extractor to generate a set of valid input vectors for exploring different simulation paths with different next states. It then works on a target state-oriented abstract model to select the next state with the smallest abstract distance. In addition, the value of register variables in control logic can be controlled by analyzing the data dependence between variables, which helps the simulation converge to the target states. Experimental results show that PACOST can generate shorter traces reaching hard-to-reach states, in comparison with previous abstraction-guided semiformal methods. [ABSTRACT FROM AUTHOR]

This paper deals with a new method of metamodel construction for electromagnetic compatibility (EMC) simulation of power electronic converters. The proposed method uses a compressed wavelet coefficients vector of a time-domain signal and a learning method [support vector regression (SVR)]. This can be applied for a black box approach of modeling of complex systems such as power converters. This allows the study of EMC behavior, the impact of the uncertainties and their propagations inside the model or the design of EMC filters. [ABSTRACT FROM PUBLISHER]

We present a computationally efficient method for the calculation of impedance matrices of a large class of standing- and traveling-wave structures used in klystrons, traveling-wave tubes, and other vacuum electronic (VE) devices. By treating the gaps as “lumped ports,” this method avoids the time and disk spaces consuming steps employed in , which required postprocessing the electromagnetic fields from a finite-element (FE) simulation. By applying analytical transformations to the impedance matrix, we show that it may be cast in a form suitable for the large-signal 1-D and 2-D beam-wave interaction codes CHRISTINE-CC , and TESLA-Z. These transformations are formulated in a way to avoid numerical errors near structure resonance frequencies (singularity points). We also derive and apply formulas by which the impedance matrix of a structure may be constructed from the impedance matrices of its component parts, without additional FE simulations; by inverting the algebraic operations, we show that the impedance matrix of a structure from which a selected subsection has been removed may also be computed. Application of these formulas greatly facilitates the accurate calculation of the impedance matrices of large complex circuits that are difficult or impossible to model whole in a single FE simulation. [ABSTRACT FROM AUTHOR]

The real-time coscheduling problem, where tasks may have multiple phases executing on different types of processors, is known to be hard. The (already hard) self-suspending task scheduling simplifies the coscheduling problem by assuming that the latency a task may experience on the other type of processors is naturally bounded, which is unfortunately not true in practice. In this article, we present a novel analysis technique, namely, the vertical view analysis, for analyzing the schedulability of coscheduling sporadic tasks under global earliest-deadline-first (GEDF) on a heterogeneous multiprocessor consisting of two types of processors. We derive both hard (no deadline miss) and soft (bounded response times) real-time utilization-based tests. To the best of our knowledge, these results are the first-of-its-kind for the coscheduling problem and may allow real-time schedulability analysis to be carried out on more practical scenarios under heterogeneous computing. [ABSTRACT FROM AUTHOR]