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Social media (such as Facebook, TikTok, Instagram, YouTube, etc.) is widely used for people's entertainment and education across the globe. Furthermore, utilizing this sort of technology assists learners in mastering foreign languages such as English, Chinese, French, Japanese, and so on, which was proved by many foreign language experts and researchers worldwide. The study aims to find out students' perceptions of using social media to develop English vocabulary. A mix of quantitative and qualitative methods was exploited with surveys for 154 students from different majors at Van Lang University (VLU) in Ho Chi Minh City (HCMC), Vietnam, and semi-structured interviews for 15. After the investigation, the research results show students' deep insights in using social media to improve their English vocabulary and its positive effects on students' learning vocabulary. Thanks to the findings, lecturers can consider more teaching methods with social media in their English courses.

This paper introduces a novel approach to deal with the multi-objective optimization of a two-stage bevel helical gearbox by applying the Taguchi method and Grey Relation Analysis (GRA). The goal of the study is to find optimal main design factors that minimize the gearbox volume and maximize the gearbox efficiency. To accomplish this, five main design parameters were selected: the coefficients of wheel face width (CWFW) of the bevel and the helical gear sets, the allowable contact stresses (ACS) of the first and the second stages, and the gear ratio of the first stage. Furthermore, two single targets were investigated: minimum gearbox volumes, and maximum gearbox efficiency. Also, the multi-objective optimization problem is solved through two steps: Step 1 for closing the gap between variable levels and Step 2 for determining the optimal main design factors. The study’s findings were used to introduce the optimum values of five major design parameters for designing a two-stage helical gearbox.

The volume of ribonucleic acid (RNA)-seq data has increased exponentially, providing numerous new insights into various biological processes. However, due to significant practical challenges, such as data heterogeneity, it is still difficult to ensure the quality of these data when integrated. Although some quality control methods have been developed, sample consistency is rarely considered and these methods are susceptible to artificial factors. Here, we developed MassiveQC, an unsupervised machine learning-based approach, to automatically download and filter large-scale high-throughput data. In addition to the read quality used in other tools, MassiveQC also uses the alignment and expression quality as model features. Meanwhile, it is user-friendly since the cutoff is generated from self-reporting and is applicable to multimodal data. To explore its value, we applied MassiveQC to Drosophila RNA-seq data and generated a comprehensive transcriptome atlas across 28 tissues from embryogenesis to adulthood. We systematically characterized fly gene expression dynamics and found that genes with high expression dynamics were likely to be evolutionarily young and expressed at late developmental stages, exhibiting high nonsynonymous substitution rates and low phenotypic severity, and they were involved in simple regulatory programs. We also discovered that human and Drosophila had strong positive correlations in gene expression in orthologous organs, revealing the great potential of the Drosophila system for studying human development and disease.

The somatic chromosome number of Panax vietnamensis Ha et Grushv. was determined to be 2n = 24, based on the hypotonic shock method by potassium chloride solution. In this study, we investigated the effect of potassium chloride and colchicine solutions on chromosome dispersion of Panax vietnamensis at different concentrations. The treatment using 0.2% KCl solution in 45 minutes combined with 0.05% colchicine solution in 2 hours subsequently resulted in proper hypotonia. The result showed that chromosomes were evenly dispersed. The hypotonic shock method seemed to be effective in equally distributing chromosomes. The result can be applied in cell genetic studies and selective breeding programs for Panax vietnamensis.

Through Silicon Via (TSV) is considered as the near-future solution to realize low-power and high-performance 3D-Integrated Circuits (3D-ICs) and 3D-Network-on-Chips (3D-NoCs). However, the lifetime reliability issue of TSV due to its fault sensitivity and the high operating temperature of 3D-ICs, which also accelerates the fault-rate, is one of the most critical challenges. Meanwhile, most current works focus on detecting and correcting TSV defects after manufacturing without considering high-temperature nodes’ impact on lifetime reliability. Besides, the recovery for defective clusters is also challenging because of costly redundancies. In this work, we present HotCluster: a hotspot-aware self-correction platform for clustering defects in 3D-NoCs to help understand and tackle this problem. We first give a method to predict normalized fault rates and place redundant TSV groups according to each region’s fault rate. In our particular medium fault-rate (normalized to the coolest area), HotCluster reduces about 60% of the redundancies in comparison to the uniformly distributed redundancies while having a higher ratio of router working in a normal state. Furthermore, HotCluster integrates both online (weight-based) and offline (max-flow min-cut offline method) mapping algorithms to help the system correct the faulty TSV clusters. The experimental results show that both the max-flow min-cut offline method and weight-based online mode with a redundancy of 0.25 exhibits less than 1% of routers disabled under 50% defect-rates.

Every year, in the Vietnam Mekong Delta Coastal Zone (VMDCZ), erosions cause approximately 300 ha of agricultural land loss. Therefore, measures for shoreline protection are urgently needed. This paper discusses the impacts of protection measures in the Go-Cong Coastal Zone to prevent erosion/accretion processes, predicted by two numerical models, MIKE21-FM and TELEMAC-2D. Hard and soft measures have been proposed using breakwaters and sandbars, respectively. The simulations show that the erosion/accretion trends provided by both models are similar. For breakwaters, MIKE21-FM provides less accretion than TELEMAC-2D in areas extending over 300 m and 500 m from shorelines. However, for sandbars, MIKE21-FM shows higher accretion within areas extending over 500 m but less than 300 m. Sandbars cause higher accretion in a larger area, extending over 1000 m offshore. The simulation results allow us to propose two alternative measures: (1) a row of several breakwater units will be implanted at 300 m offshore. The length of each unit is 600 m, with a gap between two neighbouring units of 70 m and a crest elevation of 2.2 m above mean sea level (MSL). (2) A row of sandbar units will be posed at 500 m offshore, with a unit length of 1000 m and a gap between the two neighbouring units of 200 m. The crest elevation is fixed at MSL.

For most Internet-of-Things (IoT) applications, embedded processors typically execute lightweight tasks such as sensing and communication. The typical IoT program senses some information and sends them via a channel, usually a wireless channel with an RF circuit. These IoT nodes often require a system with networking capabilities and a low-power harvester implementation. This brief presents a sub- $\mu \text{W}$ 8-bit processor which is suitable for such IoT applications. The processor implements the Open8 Instruction Set Architecture (ISA) with an 8-bit datapath and 16-bit bus addressing. The chip contains the processor and a 4-KB of Static Random-Access-Memory (SRAM), and is fabricated by the 65-nm Silicon-On-Thin-Box (SOTB) process. The SOTB process is one of the Fully-Depleted Silicon-On-Insulator (FD-SOI) technology. Hence, the ability to control biasing voltages is one of its key advantages to achieve low-power. The experimental results show that the power consumption at the reverse-body bias can reach down to 50-nW with 0.5-V supply voltage and 32-KHz operating clock frequency. The completed microcontroller consists of the Open8 processor, 32-KB of Read-Only-Memory (ROM), 4-KB of SRAM, Serial Peripheral Interface (SPI), SPI programmer, debug module, General-Purpose In-Outs (GPIOs), and UART. The system was tested using an XC7A100T Xilinx Field-Programmable Gate Array (FPGA); it yielded 1.8% of the total FPGA utilization.

Multi-criteria decision making (MCDM) is a research area that entails analyzing various available options in a situation involving social sciences, medicine, engineering, and many other fields. This is due to the fact that it is used to select the best solution from a set of alternatives. The MCDM methods have been applied not only in economics, medicine, transportation, and the military, but also in mechanical processing processes to determine the best machining option. In this study, determining the best dressing mode for external grinding SKD11 tool steel using an MCDM method—the MABAC (multi-attributive border approximation area comparison) method—was introduced. The goal of this research is to find the best dressing mode for achieving the minimal surface roughness (RS), the maximum wheel life (T), and the minimal roundness (R) all at the same time. To perform this work, an experiment was carried out with six input parameters: the fine dressing depth, the fine dressing passes, the coarse dressing depth, the coarse dressing passes, the non-feeding dressing, and the dressing feed rate. In addition, the Taguchi method and an L16 orthogonal array were used to design the experiment. Furthermore, the MEREC (method based on the removal effects of criteria) and entropy methods were used to determine the weight of the criteria. The best dressing mode for external cylindrical grinding has been proposed based on the results. These findings were also confirmed by comparing them to the TOPSIS (technique for order of preference by similarity to ideal solution) and MARCOS (measurement of alternatives and ranking according to compromise solution) methods.

The authors present a novel wideband two‐dimensional voltage‐controlled attenuator (VCA). The proposed design employs both stacked‐FET configuration and distributed structure to achieve wideband performance, high power, and high dynamic range simultaneously. A systematic design methodology is also illustrated along with a fabricated prototype to verify the concept. The chip fabricated in a 0.15‐μm Gallium Arsenide (GaAs) process exhibiting a measured power at 1‐dB compression (P1dB) of 25.5 dBm with a corresponding dynamic range of 32 dB. The insertion loss ranges from 2 to 5 dB over the bandwidth from 2 to 40 GHz. Furthermore, the chip is not only very compact (0.84 mm2), but it also requires only a single positive supply voltage, which makes it more appealing to highly integrated wireless applications.

Zebrafish (Danio rerio) has been used as a promising animal model to study gonadal development and gametogenesis. Although previous studies have identified critical molecules participating in zebrafish gonad differentiation, a landscape view of the biological processes involved in this process is still lacking. Here we isolated intact zebrafish differentiating gonads, at 25 days post-fertilization (dpf) and 30 dpf, and conducted RNA-seq analysis between the juvenile gonads that tended to develop into ovaries or testes. Our study demonstrates that the juvenile ovary and testis at 25 dpf and 30 dpf are different at the level of biological process. During ovary differentiation, the biological processes related to metabolic activities in production of energy and maternal substances, RNA degradation, and DNA repair were enriched. During testis differentiation, the biological processes related to cell proliferation, differentiation, and morphogenesis were enriched, with a total of 15 signaling pathways. Notably, we reveal that the immune-related processes are extensively involved in the regulation of testis development. Overall, this study provides a landscape of differentiated biological processes and novel insights into the initiation of sex differentiation in zebrafish.

With the large-scale grid connection of new energy power, the random fluctuation existing in the power system is intensified, which leads to frequent fluctuation of load instructions of thermal power units. It is of great significance to improve the variable load performance of the coal-fired units. It is more difficult to control the superheated steam temperature (SST). In order to improve the control performance of SST, a state variable fuzzy predictive control method is proposed in this paper. Firstly, Takagi-Sugeno fuzzy state observer is used to approximate the non-linear plant of the SST. At the same time, based on the state observer, a fuzzy state feedback controller is designed to improve its dynamic characteristics. Thirdly, based on the extended predictive model of the state feedback controller, a model predictive controller is designed to realize the SST tracking control. Dynamic simulation shows the effectiveness of the strategy.

A peptide biphenyl hybrid compound {systematic name: dimethyl 2,2′-[((2S,2′S)-2,2′-{[(2S,2′S)-1,1′-([1,1′-biphenyl]-2,2′-dicarbonyl)bis(pyrrolidine-1,2-diyl-2-carbonyl)]bis(azanediyl)}bis(3-phenylpropanoyl))bis(azanediyl)](2S,2′S)-dipropionate hemihydrate}, C50H56N6O10·0.5H2O, was prepared by coupling of [1,1′-biphenyl]-2,2′-dicarbonyl dichloride, triethylamine and the tripeptide Pro–Phe–Ala in CH2Cl2 at 273 K under an N2 atmosphere. In the crystal, the asymmetric unit contains the peptide biphenyl hybrid accompanied by one-half of a water molecule. A C atom of one of the proline rings is disordered between two positions in a 0.746 (11):0.254 (11) ratio. An important structural aspect of peptide compounds is their capacity to self-associate mediated by intermolecular and intramolecular hydrogen bonding. This characteristic can be useful in understanding the interactions between peptides and biomacromolecular targets, as well as to explain peptide properties.

As one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs), Through-Silicon-Via (TSV) acts as the inter-layer link inside 3D Networks-on-Chip. However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To ensure the correctness of TSV connections at run-time, detecting multiple (clustering) defects is an important feature. While Error Correction Codes are limited by a certain number of detectable faults, using Built-In-Self-Test (BIST) prevents the system from operating normally during the test time. This paper first presents a Parity Product Code (PPC) with the ability to correct one fault and detect, at least, two faults. Second, we present extended PPC (EPPC) to detect multiple defects within the links of Networks-on-Chip by using two or more additional matrices. Furthermore, we present the distance-aware version of EPPC to detect multiple defects by using only one extra matrix. The results show that the distance-aware EPPC can detect 100% of clustering defects and multiple random defects within two and three cycles, respectively. The performance evaluation for Network-on-Chip testing also shows no degradation while providing an extremely short response time (2-3 cycles).

The design of cryptographic engines for the Internet of Things (IoT) edge devices and other ultralightweight devices is a crucial challenge. The emergence of such resource-constrained devices raises significant challenges to current cryptographic algorithms. PHOTON is an ultra-lightweight cryptographic hash function targeting low-resource devices. The currently implemented hardware architectures of PHOTON hash function utilize a large amount of resources and have low operating frequencies with a low rate of throughputs. Maximum operating frequency and throughput of PHOTON architecture can be improved but at the cost of larger area utilization. Therefore, to improve the area-performance trade-offs of PHOTON hash function, an iterative architecture is implemented in this work. The concern is with the most lightweight version of PHOTON hash function with the hash size of 80 bits. It is implemented and verified on several Xilinx and Altera Field Programmable Gate Array (FPGA) devices using their synthesis and simulation tools. Low-cost and high-processing FPGA devices were both considered. The design is optimized for performance, whereas the area utilization is also taken into consideration. The overall performance and logic utilization are benchmarked with the existing implementations. The results show an improvement rate of 10.26% to 51.04% in the speed performance and a reduction rate of 7.55% to 60.64% in area utilization compared to existing implementations of PHOTON hash functions.

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R+1 defects. Moreover, by using G groups, it can localize up to GxR and detect up to G x (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

Deep Learning (DL) has contributed to the success of many applications in recent years. The applications range from simple ones such as recognizing tiny images or simple speech patterns to ones with a high level of complexity such as playing the game of Go. However, this superior performance comes at a high computational cost, which made porting DL applications to conventional hardware platforms a challenging task. Many approaches have been investigated, and Spiking Neural Network (SNN) is one of the promising candidates. SNN is the third generation of Artificial Neural Networks (ANNs), where each neuron in the network uses discrete spikes to communicate in an event-based manner. SNNs have the potential advantage of achieving better energy efficiency than their ANN counterparts. While generally there will be a loss of accuracy on SNN models, new algorithms have helped to close the accuracy gap. For hardware implementations, SNNs have attracted much attention in the neuromorphic hardware research community. In this work, we review the basic background of SNNs, the current state and challenges of the training algorithms for SNNs and the current implementations of SNNs on various hardware platforms.

Offshore breakwaters can be effective in reducing the energy of incident waves through dissipation, refraction or reflection. Breakwaters are increasingly constructed to stabilize eroded muddy coasts, particularly in developing countries. Accumulation of fine-grained sediment and wave attenuation are two attributes of a stable muddy coast. Effective interventions in stabilizing eroded muddy coasts include two important elements: accumulation of fine-grained sediment and wave reduction. The efficacy of offshore breakwaters in stabilizing eroded muddy coasts is, however, not yet adequately understood. A crucial question needing attention is whether accumulation of fine-grained sediment and wave attenuation should be used in evaluating the efficacy of these offshore breakwaters in stabilizing eroded muddy coasts. To address this issue, a pile-rock offshore breakwater in Huong Mai, Tieu Dua of Ca Mau, Vietnam was selected as an appropriate example in this regard. Accumulation of fine-grained sediment and wave attenuation were tested as means to investigate the efficacy of the Huong Mai structure in stabilizing the eroded muddy coast. The study was undertaken using field-based measurements and semi-structured interviews in three stages between October 2016 and December 2020. We found that this structure has had limited efficacy in stabilizing the eroded muddy coast. The structure was effective in dissipating the energy of incident waves, but we found no evidence of fine-grained sediment accumulation due to an inappropriate structural design. There was also no monitoring system in place, leading to difficulties in evaluating its efficacy in terms of wave attenuation and accumulation of fine-grained sediment. The gaps between the shoreline and the structure have not been adequately explained, resulting in substantial challenges in replicating the structure elsewhere. The Huong Mai structure should be strengthened using supplementary measures and granulometric tests in order to improve the efficacy in stabilizing eroded muddy coasts. The methods in this study provide new insights in this regard.

In this paper, a PCA and ANN-based face recognition system is proposed and implemented on a Coarse Grain Reconfigurable Computing (CGRC) platform. Our work is quite distinguished from previous ones in two aspects. First, a new hardware-software co-design method is proposed, and the whole face recognition system is divided into several parallel tasks implemented on both the Coarse-Grained Reconfigurable Architecture (CGRA) and the General-Purpose Processor (GPP). Second, we analyzed the source code of the ANN algorithm and proposed the optimization solution to explore its multi-level parallelism to improve the performance of the application on the CGRC platform. The computation tasks of ANN are dynamically mapped onto CGRA only when needed, and it's quite different from traditional Field Programmable Gate Array (FPGA) methods in which all the tasks are implemented statically. Implementation results show that our system works correctly in face recognition with a correct recognition rate of approximately 90.5%. To the best of our knowledge, this work is the first implementation of PCA and ANN-based face recognition system on a dynamically CGRC platform presented in the literature.

The origination of new genes contributes to the biological diversity of life. New genes may quickly build their own network in the genomes, exert important functions, and generate novel phenotypes. Dating gene age and inferring the origination mechanisms of new genes, like primate-specific gene, is the basis for the functional study of the genes. However, no comprehensive resource of gene age estimates across species is available. Here, we systematically dated the age of 9,102,113 protein-coding genes from 565 species in the Ensembl and Ensembl Genomes databases, including 82 bacteria, 57 protists, 134 fungi, 58 plants, 56 metazoa, and 178 vertebrates, using protein-family-based pipeline with Wagner parsimony algorithm. We also collected gene age estimate data from other studies and uniformed the gene age estimates to time ranges in million years for comparison across studies. All the data were cataloged into GenOrigin (http://genorigin.chenzxlab.cn/), a userfriendly new database of gene age estimates, where users can browse gene age estimates by species, age and gene ontology. In GenOrigin, the information such as gene age estimates, annotation, gene ontology, ortholog and paralog, as well as detailed gene presence/absence views for gene age inference based on the species tree with evolutionary timescale, was provided to researchers for exploring gene functions.

Through-Silicon-Via (TSV) is one of the most promising technologies to realize 3D Integrated Circuits (3D-ICs). However, the reliability issues due to the low yield rates and the sensitivity to thermal hotspots and stress issues are preventing TSV-based 3D-ICs from being widely and efficiently used. To enhance the reliability of TSV connections, using error correction code to detect and correct faults automatically has been demonstrated as a viable solution.This paper presents a 2D Parity Product Code (2D-PPC) for TSV fault-tolerance with the ability to correct one fault and detect, at least, two faults. In an implementation of 64-bit data and 81-bit codeword, 2D-PPC can detect over 71 faults, on average. Its encoder and decoder decrease the overall latency by 38.33% when compared to the Single Error Correction Double Error Detection code. In addition to the high detection rates, the encoder can detect 100% of its gate failures, and the decoder can detect and correct around 40% of its individual gate failures. The squared 2D-PPC could be extended using orthogonal Latin square to support extra bit correction.

As one of the most promising technologies to reduce footprint, power consumption and wire latency, Three Dimensional Integrated Circuits (3D-ICs) is considered as the near future for VLSI system. Combining with the Network-on-Chip infrastructure to obtain 3D Networks-on-Chip (3D-NoCs), the new on-chip communication paradigm brings several advantages. However, thermal dissipation is one of the most critical challenges for 3D-ICs, where the heat cannot easily transfer through several layers of silicon. Consequently, the high-temperature area also confronts the reliability threat as the Mean Time to Failure (MTTF) decreases exponentially with the operating temperature as in Black’s model. Apparently, 3D-NoCs and 3D ICs must tackle this fundamental problem in order to be widely used. However, the thermal analyses usually require complicated simulation and might cost an enormous execution time. As a closed-loop design flow, designers may take several times to optimize their designs which significantly increase the thermal analyzing time. Furthermore, reliability prediction also requires both completed design and thermal prediction, and designer can use the result as a feedback for their optimization. As we can observe two big gaps in the design flow, it is difficult to obtain both of them which put 3D-NoCs under thermal throttling and reliability threats. Therefore, in this work, we investigate the thermal distribution and reliability prediction of 3D-NoCs. We first present a new method to help simulate the temperature (both steady and transient) using traffic values from realistic and synthetic benchmarks and the power consumption from standard VLSI design flow. Then, based on the proposed method, we further predict the relative reliability between different parts of the network. Experimental results show that the method has an extremely fast execution time in comparison to the acceleration lifetime test. Furthermore, we compare the thermal behavior and reliability between Monolithic design and TSV-based design. We also explore the ability to implement the thermal via a mechanism to help reduce the operating temperature.

HEVC-standardized encoders employ the CABAC (context-based adaptive binary arithmetic coding) to achieve high compression ratios and video quality that supports modern real-time high-quality video services. Binarizer is one of three main blocks in a CABAC architecture, where binary symbols (bins) are generated to feed the binary arithmetic encoder (BAE). The residual video data occupied an average of 75% of the CABAC&rsquo, s work-load, thus its performance will significantly contribute to the overall performance of whole CABAC design. This paper proposes an efficient hardware implementation of a binarizer for CABAC that focuses on low area cost, low power consumption while still providing enough bins for high-throughput CABAC. On the average, the proposed design can process upto 3.5 residual syntax elements (SEs) per clock cycle at the maximum frequency of 500 MHz with an area cost of 9.45 Kgates (6.41 Kgates for the binarizer core) and power consumption of 0.239 mW (0.184 mW for the binarizer core) with NanGate 45 nm technology. It shows that our proposal achieved a high overhead-efficiency of 1.293 Mbins/Kgate/mW, much better than the other related high performance designs. In addition, our design also achieved a high power-efficiency of 8288 Mbins/mW, this is important factor for handheld applications.

Perivascular adipose tissue (PVAT), a special type of adipose tissue, closely surrounds vascular adventitia and produces numerous bioactive substances to maintain vascular homeostasis. PVAT dysfunction has a crucial role in regulating vascular remodeling, but the exact mechanisms remain unclear. In this study, we investigated whether and how obesity-induced PVAT dysfunction affected adventitia remodeling in early vascular injury stages. Mini pigs were fed a high sugar and fat diet for 6 months to induce metabolic syndrome and obesity. In the mini pigs, left carotid vascular injury was then generated using balloon dilation. Compared with normal mini pigs, obese mini pigs displayed significantly enhanced vascular injury-induced adventitial responses, evidenced by adventitia fibroblast (AF) proliferation and differentiation, and adventitia fibrosis, as well as exacerbated PVAT dysfunction characterized by increased accumulation of resident macrophages, particularly the M1 pro-inflammatory phenotype, increased expression of leptin and decreased expression of adiponectin, and production of pro-inflammatory cytokines interleukin (IL)-1β and IL-18. Primary AFs cultured in PVAT-conditioned medium from obese mini pigs also showed significantly increased proliferation and differentiation. We further revealed that activated nod-like receptor protein 3 (NLRP3) inflammasome and its downstream products, i.e., IL-1 family members such as IL-1β and IL-18 were upregulated in the PVAT of obese mini pigs; PVAT dysfunction was also demonstrated in preadipocytes treated with palmitic acid. Finally, we showed that pretreatment with IL-1 receptor (IL-1R) antagonist or IL-1R knockdown blocked AF proliferation and differentiation in AFs cultured in PVAT-conditioned medium. These results demonstrate that obesity-induced PVAT dysfunction aggravates adventitial remodeling after early vascular injury with elevated AF proliferation and differentiation via activating the NLRP3/IL-1 signaling pathway.

High-Efficiency Video Coding (HEVC), also known as H.265 and MPEG-H Part 2, is the newest video coding standard developed to address the increasing demand for higher resolutions and frame rates. In comparison to its predecessor H.264/AVC, HEVC achieved almost double of compression performance that is capable to process high quality video sequences (UHD 4K, 8K; high frame rates) in a wide range of applications. Context-Adaptive Baniray Arithmetic Coding (CABAC) is the only entropy coding method in HEVC, whose principal algorithm is inherited from its predecessor. However, several aspects of the method that exploits it in HEVC are different, thus HEVC CABAC supports better coding efficiency. Effectively, pipeline and parallelism in CABAC hardware architectures are prospective methods in the implementation of high performance CABAC designs. However, high data dependence and serial nature of bin-to-bin processing in CABAC algorithm pose many challenges for hardware designers. This paper provides an overview of CABAC hardware implementations for HEVC targeting high quality, low power video applications, addresses challenges of exploiting it in different application scenarios and then recommends several predictive research trends in the future.