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The recipients of the 2021 NSREC Outstanding Conference Paper Award are Daisuke Kobayashi, Kazuyuki Hirose, Keita Sakamoto, Yuta Tsuchiya, Shogo Okamoto, Shunsuke Baba, Hiroyuki Shindou, Osamu Kawasaki, Takahiro Makino, and Takeshi Ohshima for their paper titled “An SRAM SEU Cross Section Curve Physics Model.” [ABSTRACT FROM AUTHOR]

B Abstract b Fin Field-Effect Transistor (FinFET) technology enables the continuous downscaling of Integrated Circuits (ICs), using the Complementary Metal-Oxide Semiconductor (CMOS) technology in accordance with the More Moore domain. In the year 2004 she received her M.Sc. Degree in Electrical Engineering at Pontifical Catholic University of Rio Grande do Sul (Brazil) and in 2008 her Ph.D. in Computer Engineering from the Politecnico di Torino (Italy). Graph B Tiago Roberto Balen b received the Electrical Engineering degree, MSc and PhD degrees from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 2004, 2006, and 2010, respectively. [Extracted from the article]

The article discusses the use of Physical Unclonable Functions (PUFs) in electronic systems for secret key generation and device authentication. Specifically, it focuses on the use of SRAM PUFs, which are popular due to the randomness they possess during power-on. The authors propose two methods that utilize both stable and unstable SRAM bits as PUF bits to increase the usage rate of SRAM bits and resist PUF clone attacks. Extensive experiments have been conducted to demonstrate the effectiveness of these methods. The article also provides brief biographies of the authors. [Extracted from the article]

The increasing demand for high-density Very Large-Scale Integrated (VLSI) circuits, driven by the scaling of CMOS technology, is primarily challenged by the need for uniformity in SRAM cells. Given that most programs frequently seek dependable data, the primary cache and memory caching (MC) component in SRAM tends to be relatively steady. Resolving power and delay imbalances is the main problem with SRAM cells. The issues with CMOS-based SRAM cells include high cost, wide parameter variation, and worse dependability. CMOS devices also experience a loss of channel control by the gate. It is therefore advised to use FinFET-based SRAM cells rather than CMOS. This paper presents a design study of a 1T-1D SRAM cell using FinFET and CMOS technology. Without changing the logic state of the SRAM cell, the objective of this paper is to lessen power leakage. The cell structure's ease of design also contributes to its remarkable affordability and accessibility. A 1T-1D cell with the bare minimum of transistors has a smaller overall area. The suggested 1T-1D SRAM cell is implemented using the Tanner EDA working platform, which uses 7nm FinFET technology. With this study, low power was reached up to 99%, and delay reduction was improved to 98%. [ABSTRACT FROM AUTHOR]

Transistor random threshold voltage variations due to process fluctuations seriously affects the stability of Static Random Access Memory (SRAM). In this paper, a SRAM bit transistors threshold voltage $({Vth})$ deviation monitoring scheme and system is proposed. This scheme ingeniously achieves on-chip measurement of all transistors threshold voltages without altering compact SRAM bit array layout. Control signal strategies and Transistor ${Vth}$ Determination Circuit (TVDC) for different types of Devices Under Test (DUTs) have been proposed. The system is implemented using a 65 nm CMOS process with a core area of 0.01875mm2. Through Monte Carlo analysis, the Weighted Average (WA) difference of the proposed scheme and the direct measurement method is not more than 10mV, and the Root Mean Square Error (RMSE) difference is not more than 3mV. This system can also effectively detect the cell position of the transistor threshold voltage mismatch simulated by modifying the substrate voltage. For SRAM arrays of different scales, the method proposed in this paper has area efficiency and flexible reconfigurability. [ABSTRACT FROM AUTHOR]

Static Random Access Memory (SRAM) is volatile and uses latching flip-flops to store each bit. To make SRAM work as non-volatile memory (NVM), memristor-based SRAM is a feasible choice mainly due to its high-speed operation and low power consumption. In this paper, the operational characteristics of 4T2M SRAM have been studied based on three different memristor models developed by Biolek et al. (2009), Joglekar and Wolf 2009, and Prodromakis et al. (2011), and comparative performance analysis has been made to assess its adaption to NVM. These three different models are compared in terms of delay, power consumption, and static noise margin. From the simulation, it has been observed that Biolek 4T2M SRAM produces better performance in write delay calculation scoring 0.873 ns when '0' is written and 0.166 ns when '1' is written. This model also provided a low power consumption value compared to other models. However, ternary plot analysis finds that Prodromakis is performing in average better in all positive traits. All the simulations are done in LTSpice and the transistor uses TSMC 180 nm CMOS technology. [ABSTRACT FROM AUTHOR]

With the human stepping into the information society and the rapid increase of information, various display facilities and display devices are getting unprecedented development. In the display industry, Micro-LED has become the focus of development because it has the advantages of both traditional LED and small size, and can achieve extremely high PPI. However, it is precisely because of its small size, in order to drive Micro-LED display, it is particularly important to design a separate driver circuit that meets its characteristics. In this paper, different structures of pixel drivers in Micro-LED display driver circuits are studied. By comparing DRAM and SRAM structures, the performance of pixel driver under different frequency conditions is analyzed. This paper introduces and analyzes the circuit structure and design flow of various pixel drivers. Simulation is carried out by Cadence software, and its actual performance is verified by taping out. [ABSTRACT FROM AUTHOR]

With the rapid growth of big data information and the continuous iteration progress of CPU architecture, the implementation of a new memory-based cache architecture is urgent and challenging. In the paper, a CPU cache architecture system based on MRAM is built. Firstly, the performance of SRAM, STT-MRAM and SOT-MRAM as caches from 8 kb to 32 Mb is evaluated. Secondly, by summarizing the performance of SRAM and MRAM in different cache levels, a new quad-core CPU cache architecture design scheme with SOT-MRAM as the first level of cache and STT-MRAM as the second level of cache is determined. Thirdly, the built cache system is simulated. A non-inclusive strategy is proposed to replace the inclusive strategy in order to solve the problem of high dynamic energy of STT-MRAM at the second level. The idea of having a quad-core CPU dynamically share the second-level cache is proposed in the paper. Finally, the caching system in the paper is compared with the other previous works, showing up to 60.78% energy consumption advantage and 33.22% leakage power advantage. The proposed MRAM-based CPU cache system and the corresponding cache strategy have potential application with the benefits of low power and less area. [ABSTRACT FROM AUTHOR]

In this paper, a schmitt trigger-based single-sided 7T stable SRAM is proposed for ultra-low energy and near-threshold operation, which supports a bit interleaving scheme. The proposed ST-7T SRAM design improves the WSNM (Write Static Noise Margin) and RSNM (Read Static Noise Margin) and consumes less energy. Moreover, obtain high read strength by utilizing a single-sided ST (schmitt trigger) inverter. Furthermore, write ability is also enhanced by applying an ST inverter write assist scheme (Negative VWWL technique), which can limit the tripping voltage of the ST inverter circuit. The PST-7T (Proposed ST-7T) circuit minimizes the read power by 49.96%, write power by 39.27%, and leakage power by 39.17% compared to conventional-6T SRAM. The RSNM and WSNM of the proposed SRAM circuit are enhanced by 66.28% and 18.97% compared to conventional-6T SRAM. The write energy and read energy utilization are also lowered by 14.87% and 14.19% compared to the SE7T SRAM cell. [ABSTRACT FROM AUTHOR]

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

Non-invasive side-channel attacks (SCAs) based on leakage power analysis (LPA) have received more attention recently, since leakage current has gradually become more dominant with further scaled technologies. For SRAM cells, LPA exploits the correlation between data in memory cells and their corresponding leakage power. This paper proposes a novel SRAM design in 7 nm node for countering LPA attacks, based on a single-ended PMOS-reading 9T (nine-transistor) cell design. The leakage current imbalance, delay, stability, and robustness of SRAM cells are examined for the proposed memory cell architecture with layout designs, and results are compared against other SRAM cell designs. Simulation results and failure of LPA attacks in case studies confirm the enhanced resilient behavior for the new SRAM cell design. [ABSTRACT FROM AUTHOR]

Low-power memories typically operate in the subthreshold region of the device; however, as the supply voltage continues to decrease, the impact of leakage current on SRAM stability becomes more significant. The traditional method of measuring static noise tolerance only considers the effect of voltage, and the measurement results are not accurate enough. Therefore, this paper proposes a leakage-current-based stability analysis that provides better metrics, reads current noise tolerance (RINM) and writes current noise tolerance (WINM) to measure the stability of subthreshold SRAMs. Both currents and voltages were taken into account. The results demonstrate that the method is more accurate than the conventional method under subthreshold levels. [ABSTRACT FROM AUTHOR]

Summary: Static Random Access Memory (SRAM) is vital in aerospace applications, but it may experience soft errors in strong radiation environments. This paper proposes a reconfigurable radiation SRAM with two operating modes catering to different environmental requirements: (1) traditional triple modular redundancy mode used when the radiation environment is strong and (2) SRAM cell expansion mode used when the radiation is not very strong. For example, when the memory capacity of a single module is 8 k, the memory capacity is 8 k in traditional triple modular redundancy mode, but it can be tripled to 24 K in extended mode. As can be obviously seen, this design can adjust the size according to the needs. In SRAM cell expansion mode, the proposed 14T SRAM cell enables the memory to maintain radiation resistance. Compared with DICE, RHBD‐12T, and WHIT, the read speed is improved by 3.8%, 5.7%, and 11.5% respectively, but compared with WE‐QUATRO, the read speed is reduced by 1.9%. The hold static noise margin is 1.378 times than DICE, 1.201 times than WE‐QUATRO, 1.045 times than RHBD‐12T, and 1.14 times than WHIT, respectively. The proposed 14T cell in this paper exhibits the highest critical charge value compared with the other cells. Combined with the expansion mode of the reconfiguration design, it shows great stability. [ABSTRACT FROM AUTHOR]

This paper investigates a low leakage power 8 T (LP8T) SRAM cell with high read and write stability. The proposed LP8T (PLP8T) SRAM cell has separate write and read bit lines. As an outcome, the read disturbance is removed. Furthermore, the utilization of a schmitt-trigger (ST) inverter enhances the read stability. Moreover, the write assist technique can enhance the writing ability. When compared to conventional-6 T SRAM, the PLP8T SRAM cell improves HSNM, RSNM, and WSNM by 1.4× 2.3 × and 1.3× respectively. The PLP8T SRAM's read and write access times are lowered by 53.24 and 42.18%, respectively. The PLP8T SRAM has a 50% lower read and write power than conventional-6 T SRAM. In addition, there will be a sufficient improvement when compared to chang10T, HSWA9T, SEDFC8TT, and ST11T SRAM cells. [ABSTRACT FROM AUTHOR]

In this paper, the temperature dependence of single event upset (SEU) cross-section in 28 nm embedded Static Random Access Memory (SRAM) of System in Package (SiP) was investigated. An atmospheric neutron beam with an energy range of MeV~GeV was utilized. The SEU cross-section increased by 39.8% when the temperature increased from 296 K to 382 K. Further Technology Computer Aided Design (TCAD) simulation results show that the temperature has a weak impact on the peak pulse current, which is mainly caused by the change of bipolar amplification effect with temperature. As the temperature increases, the critical charge of the device decreases by about 4.8%. The impact of temperature on the SEU cross-section is determined competitively by the peak pulse current and the critical charge. The impact of temperature on critical charge is expected to become more severe as the feature size is further advanced. [ABSTRACT FROM AUTHOR]

In this paper, a 12-transistor radiation tolerant SRAM cell has been proposed in 16-nm CMOS predictive technology model. The proposed 12T SRAM cell offers higher immunity to soft error than all other compared memory cells. The proposed SRAM cell proves its robustness against radiation strike by showing the largest amount (4.1 fC) of critical charge (QC) among all the comparison SRAM cells. The proposed 12T cell consumes 48.03%, and 48.68% lower hold power than QUCCE 12T and QUCCE 10T SRAM cell, respectively. It exhibits 79.92%, 33.77%, 84.84%, and 59.97% shorter read delay compared to 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively at a nominal supply voltage of 0.7 V. In terms of write delay the proposed 12T exhibits 68.49% shorter write delay as compared with QUCCE 10T. The proposed circuit has higher RSNM as compared to other SRAM cells and consumes lesser silicon area than other comparison cells except 6T and QUCCE 10T SRAM cell. The read stability of proposed 12T is 3.10×, 1.76×, 2.09×, 1.62 × times higher than 6T SRAM, QUCCE 10T, WE QUATRO, and QUCCE 12T, respectively. The proposed 12T exhibits 65.85%, 41.46%, 26.82%, and 41.46% improvement in critical charge (QC) in comparison with 6T SRAM, QUCCE 10T, WE QUATRO and QUCCE 12T, respectively. However, these improvements are achieved at the cost of marginal degradation of write margin as compared to 6T, QUCCE 10T, WE QUATRO and QUCCE 12T SRAM cells, respectively. In terms of area, the proposed 12T acquires lesser area as compared to QUCCE 12T (6.32%) and WE QUATRO (12%). Hence, the proposed 12T SRAM cell is a promising selection for future highly reliable terrestrial applications. [ABSTRACT FROM AUTHOR]

Physically unclonable functions (PUFs) are crucial for enhancing cybersecurity by providing unique, intrinsic identifiers for electronic devices, thus ensuring their authenticity and preventing unauthorized cloning. The SRAM-PUF, characterized by its simple structure and ease of implementation in various scenarios, has gained widespread usage. The soft-decision Reed–Muller (RM) code, an error correction code, is commonly employed in these designs. This paper introduces the design of an RM code soft-decision attack algorithm to reveal its potential security risks. To address this problem, we propose a soft-decision SRAM-PUF structure based on the elliptic curve digital signature algorithm (ECDSA). To improve the processing speed of the proposed secure SRAM-PUF, we propose a custom ECDSA scheme. Further, we also propose a universal architecture for the critical operations in ECDSA, elliptic curve scalar multiplication (ECSM), and elliptic curve double scalar multiplication (ECDSM) based on the differential addition chain (DAC). For ECSMs, iterations can be performed directly; for ECDSMs, a two-dimensional DAC is constructed through precomputation, followed by iterations. Moreover, due to the high similarity of ECSM and ECDSM data paths, this universal architecture saves hardware resources. Our design is implemented on a field-programmable gate array (FPGA) and an application-specific integrated circuit (ASIC) using a Xilinx Virtex-7 and an TSMC 40 nm process. Compared to existing research, our design exhibits a lower bit error rate ( 2.7 × 10 − 10 ) and better area–time performance (3902 slices, 6.615 μ s ECDSM latency). [ABSTRACT FROM AUTHOR]

Many IoT applications require high computational performance and flexibility, and FPGA is a promising candidate. However, increased computation power results in higher energy dissipation, and energy efficiency is one of the key concerns for IoT applications. In this paper, we explore adiabatic logic for designing an energy efficient configurable logic block (CLB) and compare it to the CMOS counterpart. The simulation results show that the proposed adiabatic-logic-based look-up table (LUT) has significant energy savings for the frequency range of 1 MHz to 40 MHz, and the least energy savings is at 40 MHz, which is 92.94% energy reduction compared to its CMOS counterpart. Further, the three proposed adiabatic-logic-based memory cells are 14T, 16T, and 12T designs with at least 88.2%, 84.2%, and 87.2% energy savings. Also, we evaluated the performance of the proposed CLBs using an adiabatic-logic-based LUT (AL-LUT) interfacing with adiabatic-logic-based memory cells. The proposed design shows significant energy reduction compared to a CMOS LUT interface with SRAM cells for different frequencies; the energy savings are at least 91.6% for AL-LUT 14T, 89.7% for AL-LUT 16T, and 91.3% AL-LUT 12T. [ABSTRACT FROM AUTHOR]

The reconfigurable capability of static random‐access memory (SRAM) field programmable gate array (FPGA) can be used for its fault self‐repair method. As a machine learning method, the genetic algorithm (GA) is an FPGA fault repair method that can be automatically executed on‐orbit without any ground support. However, the GA‐based fault repair method has disadvantages, such as the dependency on processors, the knowledge requirement for user designs in FPGAs, and the small size of repaired circuits. To address these issues, this paper presents a comprehensive analysis of the FPGA bitstream in the aerospace industry. An accurate on‐orbit fault location can be identified by bitstream copying and exhaustive test and the executed area of the GA can be reduced to one tile. In addition, the probability function of the algorithm is optimized, which converts floating‐point operations into integer arithmetic operations that are easily implemented in FPGAs without processors. The method is outstanding compared with existing ones, considering: (1) The size of repaired circuits is hundreds of times larger than those from other methods. (2) Its implementations are totally up to FPGAs' own logic, with no requirement for processors. (3) There is no knowledge requirement for user design. (4) It reaches the leading level with a success rate of 81%–93%. The method has been verified by various applications in XC7VX330T, which demonstrates its engineering practicability. [ABSTRACT FROM AUTHOR]

Today's high speed data processing and memory storage operations demand immediate data write and retrieval to meet up to benchmark. To act as a volatile or nonvolatile data storage for electronic devices such as mobile phones, laptops, the Static Random-Access Memory (SRAM) has been perfect choice for industrialists. So, memory usage is significant and more than 65% of electronic devices uses memory as its heart. Nevertheless, memory turns out to be a leading factor affecting speed, power and data retention in a handheld system. The urge for optimization in power is all time relevant. The proposed system is designed to optimize a single bit memory cell of conventional static random-access memory and hence developed a stable system with low power consumption and obtained significantly low Power-Delay-Product (PDP) by varying operating frequencies in MHz (Mega Hertz) range. Also, a comparative analysis of a 4 × 4 SRAM array is carried out between 6 T SRAM cell and 9 T SRAM cell. Here 62.83% power reduction is obtained in the proposed system as compared with the existing system at an operating frequency of 2 GHz. In this paper, a power reduction of 62.273% is obtained for the array structure. The power dissipation and Power Delay Product [PDP] of the single bit 9 T SRAM cell is also lower than the conventional 6 T SRAM. Thus, the paper implements the proposed scheme of SRAM into an array along with all connecting peripherals. [ABSTRACT FROM AUTHOR]

This paper presents the benefit of the near-threshold design of random-access memory (SRAM) design to reduce software errors during very low-power operations in nanosatellites. The near-threshold design is based on an optimization of the use of the Schmitt trigger structure for a 45 nm technology. The results of the soft error susceptibility of the optimized design are compared to a standard 6T SRAM cell. These two designs are modeled and validated by comparing the results with experimental measurements of both static noise margin (SNM) and single event upset (SEU). The optimized circuit reduces the multiple upsets occurrence from 95% down to 14%. Based on the use of simulation tools, the paper demonstrates that the near-threshold design of SRAM is an excellent candidate for the radiation point of view for agile nanosatellites. The results computed for the near-threshold SRAM device demonstrate an improvement of a factor of up to 25 of the soft error rate (SER) in a GEO orbit. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable negative bit line collapsed supply (RNBLCS) write driver circuit for the 9T Schmitt trigger-based static random-access memory (SRAM) cell (9T-ST), significantly improving write performance for real-time memory applications. In deep sub-micron technology, increasing device parameter deviations significantly reduce SRAM cells' write-ability. The proposed RNBLCS write-assist driver for 9T-ST SRAM cell has 0.84×, 0.48×, 0.27× optimized write access delay and 1.05×, 1.08×, 1.19× improvement in write static noise margin (WSNM), 1.05×, 1.13×, and 1.39× improvement in write margin (WM), 0.96×, 0.89× and 0.72× minimum write trip-point (WTP) from transient-negative bit line (Tran-NBL), capacitive charge sharing (CCS), and conventional write circuits respectively. The proposed RNBLCS is functionally verified using a synopsys custom compiler with a 16 nm BSIM4 model card for bulk complementary metal-oxide semiconductor (CMOS). [ABSTRACT FROM AUTHOR]

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

In this paper, a mathematical model for obtaining energy consumption of IMC architectures is constructed. This model provides energy estimation based on the distribution of a specific dataset. In addition, the estimation reduces the required simulation time to create an energy consumption model of SRAM-based IMC architectures. To validate our model with realistic data, the energy consumption of IMC is compared by using NeuroSim V3.0 for the CIFAR-10 and MNIST-like datasets. Furthermore, an application is created with our model to select highest performing quantization mapping based upon the parameters of energy consumption and accuracy. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the effects of negative bias instability (NBTI) and self-heating effect (SHE) on threshold voltage in NSFETs. To explore accurately the interaction between SHE and NBTI, we established an NBTI simulation framework based on trap microdynamics and considered the influence of the self-heating effect. The results show that NBTI weakens the SHE effect, while SHE exacerbates the NBTI effect. Since the width of the nanosheet in NSFET has a significant control effect on the electric field distribution, we also studied the effect of the width of the nanosheet on the NBTI and self-heating effect. The results show that increasing the width of the nanosheet will reduce the NBTI effect but will enhance the SHE effect. In addition, we extended our research to the SRAM cell circuit, and the results show that the NBTI effect will reduce the static noise margin (SNM) of the SRAM cell, and the NBTI effect affected by self-heating will make the SNM decrease more significantly. In addition, our research results also indicate that increasing the nanosheet width can help slow down the NBTI effect and the negative impact of NBTI on SRAM performance affected by the self-heating effect. [ABSTRACT FROM AUTHOR]

Embedded memories occupy an increasingly dominant part of the area and power budgets of modern systems-on-chips (SoCs). Multi-ported embedded memories, commonly used by media SoCs and graphical processing units, occupy even more area and consume higher power due to larger memory bitcells. Gain-cell eDRAM is a high-density alternative for multi-ported operation with a small silicon footprint. However, conventional gain-cell memories have limited data availability, as they require periodic refresh operations to maintain their data. In this paper, we propose a novel multi-ported gain-cell design, which provides up-to N read ports and M independent write ports (NRMW). In addition, the proposed design features a configurable mode of operation, supporting a hidden refresh mechanism for improved memory availability, as well as a novel opportunistic refresh port approach. An 8kbit memory macro was implemented using a four-transistor bitcell with four ports (2R2W) in a 28 nm FD-SOI technology, offering up-to a 3× reduction in bitcell area compared to other dual-ported SRAM memory options, while also providing 100% memory availability, as opposed to conventional dynamic memories, which are hindered by limited availability. [ABSTRACT FROM AUTHOR]

This paper presents a novel reconfigurable SRAM CRP PUF that can achieve high reliability and randomness. In conventional reconfigurable SRAM CRP PUFs, imprecise timing control can produce a biased response output, which is typically attributed to mismatches in the connection of input control signals to the two inverter arrays in the layout floorplan. We propose a timing control scheme along with the addition of an adjunct NMOS transistor to address this issue. This eliminates the connection mismatches for the challenge and word-line inputs to the two inverter arrays. Furthermore, we employ symmetric layout techniques to achieve the randomness of response output. The symmetric arrangement of the two inverter arrays maximizes the inherent random output characteristics derived from process variation. The pre-charge input signal is symmetrically connected to each array to prevent delay mismatches. A 16 × 9-bit reconfigurable PUF array is fabricated by using a 180 nm CMOS process, with a PUF cell area of 1.2 × 10 4 F 2 /bit. The experimental results demonstrate an inter Hamming distance of 0.4949 across 40 chips and an intra Hamming distance of 0.0167 for a single chip in 5000 trials. The measured worst bit error rate (BER) is 4.86% at the nominal point (1.8 V, 25 °C). The proposed prototype exhibits good reliability and randomness, as well as a small silicon area when compared to the conventional SRAM CRP PUFs. [ABSTRACT FROM AUTHOR]

Decoders are one of the significant peripheral components of static random-access memory (SRAM). As the CMOS technology moves towards nano scale regime, the leakage power starts dominating dynamic power. In this paper, we propose decoders using NAND logic in 32 nm CMOS technology. Leakage power is reduced by employing dual-threshold technique. Dual thresholding is a technique that uses transistors of two different threshold voltages. The technique is implemented in simulation by two methods; first method uses transistors with different threshold voltage and the second method uses substrate biasing to vary the threshold voltage. Row and column decoders are designed and simulated in H-Spice. The leakage power is calculated and compared for both the methods. The NAND gate implemented by Method-1 and Method-2 provides a maximum leakage power savings of 87.67% and 90.81% respectively. The maximum leakage power savings of 96.76% and 98.74% is reported for the row decoder implemented by Method-1 and Method-2 respectively. Similarly, Method-1 gives maximum leakage power savings of 97.09% and Method-2 gives a savings of 99.11% for column decoder. The difference in leakage power savings of Method-1 and Method-at same threshold voltage is 3.14%, 1.98%, and 2.02% for NAND gate, row decoder and column decoder respectively. [ABSTRACT FROM AUTHOR]

This paper presents multistate spatial wavefunction switched (SWS)-quantum dot channel (QDC) field-effect transistor (FET) static random access memory (SRAM)-based Compute-in-Memory (CIM) cell. The SWS-QDC FETs have two or more vertically stacked coupled quantum dot channels, and the spatial location of carriers within these channels is governed by the applied gate voltage. The location of the carriers can be utilized to encode multiple logic levels within a single device. The utilization of SWS-QDC FETs in CIM cell increases the data storage and energy-efficient computation in the memory. CIM reduces the data access time and improves performance for energy-efficient artificial intelligence (AI) edge devices. [ABSTRACT FROM AUTHOR]

In SRAM cells, as the size of transistors and the distance between transistors decrease rapidly, the critical charge of the sensitive node decreases, making SRAM cells more susceptible to soft errors. If radiation particles hit the sensitive nodes of a standard 6T SRAM cell, the data stored in the cell are flipped, resulting in a single event upset. Therefore, this paper proposes a low-power SRAM cell, called PP10T, for soft error recovery. To verify the performance of PP10T, the proposed cell is simulated by the 22 nm FDSOI process, and compared with the standard 6T cell and several 10T SRAM cells, such as Quatro-10T, PS10T, NS10T, and RHBD10T. The simulation results show that all of the sensitive nodes of PP10T can recover their data, even when S0 and S1 nodes flip at the same time. PP10T is also immune to read interference, because the change of the '0' storage node, directly accessed by the bit line during the read operation, does not affect other nodes. In addition, PP10T consumes very low-holding power due to the smaller leakage current of the circuit. [ABSTRACT FROM AUTHOR]

This paper presents a CNFET (Carbon Nano-tube FET) based MT (Multi-Threshold)-SRAM (Static Random Access Memory) design based on the leakage reduction mechanism. A multi-threshold logic is employed for reducing the leakage current during read/write operations. Here, the multi-threshold technique is used to insert the high threshold sleep control to the low threshold circuit. The insertion is performed in a serial manner. The high threshold transistors are very useful for deriving the low sub-threshold current. Meanwhile, the low threshold transistors are promising for improving the circuit performance. The high-low threshold transistor pairs are used to change the channel length by modifying the oxide thickness of the transistors. The overall implementation of the Multi-threshold-based SRAM cells are implemented with the help of CNFET in-order to avoid the short channel effect, mobility degradation which is occurred while considering the channel length below 32 nm in CMOS (Complementary Metal Oxide Semiconductor) devices. The paper clearly represents the performance improvement of the proposed SRAM cells with above-mentioned technologies. [ABSTRACT FROM AUTHOR]

Summary: As transistor feature size is scaling down, the probability of charge sharing in a space‐radiation environment increases because of the reduced distance between adjacent transistors. The single‐event multiple‐node upset (SEMNU) caused by charge sharing is a major source of data errors in high‐density static random‐access memory (SRAM). In this paper, a radiation‐hardened SRAM using polarity hardening is proposed. Compared to other cells (RHPD‐12T, RSP14T, SEA14T, We‐Quatro, QUCCE12T, SARP12T, SIS10T, and 12T), the proposed RHC‐14T cell saves 8.47%, 91.34%, 162.71%, ‐20.63%, −20.50%, 113.18%, 63.27%, and 20.60% of the read‐delay time and 7.96%, 66.17%, 68.16%, 57.71%, 22.39%, 12.44%, 1,010.45%, and 13.43% of the write‐delay time, respectively. Moreover, this excellent performance entails only minimal power consumption. The proposed cell can work well in the radiation‐intensive space environment. [ABSTRACT FROM AUTHOR]

Static random-access memory (SRAM), a pivotal component in integrated circuits, finds extensive applications and remains a focal point in the global research on single-event effects (SEEs). Prolonged exposure to irradiation, particularly the displacement damage effect (DD) induced by high-energy protons, poses a substantial threat to the performance of electronic devices. Additionally, the impact of proton displacement damage effects on the performance of a six-transistor SRAM with an asymmetric structure is not well understood. In this paper, we conducted an analysis of the impact and regularities of DD on the upset cross-sections of SRAM and simulated the single-event upset (SEU) characteristics of SRAM using the Monte Carlo method. The research findings reveal an overall increasing trend in upset cross-sections with the augmentation of proton energy. Notably, the effect of proton irradiation on the SEU cross-section is related to the storage state of SRAM. Due to the asymmetry in the distribution of sensitive regions during the storage of "0" and "1", the impact of DD in the two initial states is not uniform. These findings can be used to identify the causes of SEU in memory devices. [ABSTRACT FROM AUTHOR]

This paper presents an error resilience evaluation of the intra prediction step in Versatile Video Coding decoders when approximate storage is employed in the Reference Line Buffer (RLB). We present an error injection framework to simulate the use of approximate storage in the RLB buffer with commonly used bit error rate (BER) values from literature for static random-access memory and dynamic random-access memory technologies. We perform an error resilience evaluation based on peak signal-to-noise ratio and structural similarity for twelve video sequences, considering different decoding settings, with four quantization parameters, two encoding configurations, and seven BERs. We also present a few examples, showing how approximately decoded sequences can look and performing a subjective visual quality analysis. Our analysis characterizes how the impacts of approximation are dependent on video content and configurations. The results show that approximate storage can be used in some of the evaluated scenarios with very low degradation on the final visual quality of the decoded video sequences. [ABSTRACT FROM AUTHOR]

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput.30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model. [ABSTRACT FROM AUTHOR]

With the percentage of embedded SRAM increasing in SoC chips, low-power design such as the near-threshold SRAM technique are getting increasing attention to reduce the entire chip energy consumption. However, the descending operating voltage will lead to longer write latency and a higher failure rate. In this paper, we present a novel low Vth ultradynamic voltage scaling (UDVS) 9T subthreshold SRAM cell to improve the write ability of SRAM cells. The proposed Low Vth UDVS SRAM cell is demonstrated with a low threshold voltage speed-up transistor and an ultradynamic voltage scaling circuit implemented in 16 nm low-leakage CMOS technology. This wide supply range was made possible by a combination of circuits optimized for both subthreshold and abovethreshold regimes. This write assist technique can be operated selectively to provide write capability at very low voltage levels while avoiding excessive power overhead. The simulation findings reveal that with 16 nm technology, the write ability is improved by 33% over the normal case at 0.9 V supply voltage. [ABSTRACT FROM AUTHOR]

The impact of 0.1–10 MeV neutron-induced single-event upsets (NSEUs) on terrestrial SER (soft error rate) prediction is analyzed for several broad spectrum neutron sources based on 0.1–200 MeV NSEU energetic-dependent cross-sectional data of a 40 nm SRAM. The results show that for test facilities with abundant <10 MeV neutrons, such as ISIS ChipIR, J-PARC BL10, CSNS Back-n, and CSNS BL09, the terrestrial SER is overestimated. The overestimation could reach 78%–287%. By reducing the cutoff energy (Emin) from 10 to 6 MeV, the overestimation can be decreased. However, the overestimation can still reach up to 164% in this case, significantly larger than the results reported by previous studies. By analyzing the contribution of neutrons in different energy bins to NSEUs, the discrepancy is proved to be attributed to the sensitivity of NSEUs to 0.1–1 MeV neutrons, along with the overpopulation of 0.1–1 MeV neutrons for certain test facilities, such as ISIS ChipIR and CSNS BL09. Therefore, it is necessary to take 0.1–1 MeV NSEU sensitivity into account when studying the prediction method using broad spectrum neutron sources. [ABSTRACT FROM AUTHOR]

This paper presents a single-ended 11T sub-threshold SRAM (SE11T) based on 10-nm FinFET technology. The performance of the proposed design is evaluated and compared with those of other state-of-the-art SRAMs namely 6T, 8T, DIRP10T, ST2, PPN10T, and FC11T at VDD = 0.3 V. The proposed design improves read stability by 2.08X/1.31X/1.03X compared to 6T/ST2/PPN10T due to the read-decoupling technique. Furthermore, it improves writability by 1.42X/2.85X/1.35X/1.28X compared to 6T/DIRP10T/ST2/PPN10T owing to feedback-cutting scheme. The use of write bitline free structure make the proposed SRAM consumes at least 2.79X lower dynamic power. The static power is reduced in the proposed SRAM by at least 1.09X. The reduction is because of the stacking of the transistors, the long path from power VDD to ground, and eliminated leakage in read path. The proposed SRAM works reliably even when exposed to extreme process variations. The proposed bitcell occupies a 1.46X/1.19X higher area than that of 6T/8T. The proposed design improves most of the design metrics and can be an efficient candidate for portable applications with budgeted power. [ABSTRACT FROM AUTHOR]

Summary: As the scale of the integrated circuit increases, the distance between transistors decreases, a trend that reduces the critical charge of the sensitive nodes of the memory cell. Consequently, Static Random Access Memory cells in high radiation environments are very prone to soft errors. A novel radiation‐hardened memory cell, the Polarity Reinforcement Feature (PRF)‐18T, is proposed in this paper, which uses the polarity reinforcement feature to reduce the number of sensitive nodes in the memory cell and can entirely and effectively tolerate single event upset and double node upset. A comparison is made in this paper with DICE‐12T, Quatro‐10T, SEA‐14T, RHBD‐14T, NASA‐13T, and SCCS‐18T memory cells in a simulation environment with Semiconductor Manufacturing International Corporation 55 nm process, the supply voltage of 1.2 V, and temperature of 25°C. In comparison, the PRF‐18T proposed in this paper has the highest critical charge value, improving by more than 15× and 3.1× compared to the DICE‐12T and RHBD‐14T, respectively, and by more than 79% and 17.6% compared to the Quatro‐10T and SEA‐14T, respectively. In the high hold static noise margin comparison, the improvement over the SEA‐14T, DICE‐12T, RHBD‐14T, and Quatro‐10T is 26.7%, 3.8×, 1.5×, and 1.2×, respectively. In the write static noise margin comparison, the results were similar to the Quatro‐10T, DICE‐12T, and SEA‐14T, with a 68.5% improvement compared to the RHBD‐14T. Finally, the robustness of the proposed cell to process, voltage, and temperature variations is verified by temperature change experiments and 2000 Monte Carlo model simulations. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

This paper introduces an 8T single-ended SRAM cell to improve stability and decrease energy consumption. It cuts the pull-down path to the storage node written '1', enhancing the write ability. It uses an isolated read path to enhance the read stability with low power and energy consumption. At a supply voltage of 0.5 V, the read static noise margin, write margin, read energy, and write energy of the proposed cell are superior by 320%, 233%, 12%, and 26%, respectively, compared to the conventional 6T. We performed 5,000 Monte Carlo simulations in the 32 nm technology to evaluate read yields. The results show that our cell has 6.9x more yields than the conventional 6T SRAM cell. Therefore, the proposed cell can be a good option for high stability and low power/energy applications. [ABSTRACT FROM AUTHOR]

Today’s era is a digital world where each and every section of the society is experiencing and encountering with semiconductor chips. In very large-scale integration (VLSI) circuits the design of static random-access memory (SRAM) plays a crucial role in ensuring both low-power consumption and high-speed performance. The sense amplifiers (SA) are integral parts for information accessing storage in SRAM IC design. This paper introduces a dual voltage latch sense amplifier (DVLSA) for SRAM integrated circuits (IC). The comparative analyses of various SA are studied and then design a low-power SA through the implementation of energy-efficient technique. Further, we have elucidated the causes of delay and power dissipation in different SA with useful solutions and performance evaluation is conducted by comparing the proposed design with existing SA reported in the literature. The performance parameters such as power 1.604 uw, energy 470.50 fJ, delay 80.04 ps, and current 5.406 are scrutinized to assess the efficiency of the designs. The cell outcomes have been validated with cadence tool on 180 nm technology and operate at 1.8 V. The proposed design, namely, DVLSA demonstrates minimal energy consumption and low power dissipation, making it a promising advancement in SRAM IC technology. [ABSTRACT FROM AUTHOR]

Transition metal dichalcogenide field‐effect transistors (TMDFETs) as a replacement for conventional metal–oxide–semiconductor field‐effect transistors (MOSFETs) have attracted the attention of researchers in recent years. The efficiency of these devices should be investigated in different aspects in digital systems. One of the important components of such systems is dynamic random‐access memory (DRAM), which is used in most computers and many electronic systems as the main memory due to its small area and simple structure, compared to static memory (SRAM) cells. In this paper, a regular DRAM cell is designed based on TMDFET devices and its performance is compared with a similar cell in conventional MOSFET technology from various aspects, including DRAM‐specific timing characteristics considering changes in design and environmental parameter variations using Monte Carlo simulations. The simulations have been carried out in HSPICE with 16 nm technology under fair conditions for different technologies, at room temperature with a 0.7‐V power supply. The results show that the TMD‐DRAM has 3.55×, 3.08×, and 2.23× faster bitline recovery, merge time, and sense time than Si‐MOS‐DRAM, respectively. The Si‐MOS‐DRAM, on the other hand, has 1.65× faster write time compared to TMD‐DRAM. However, TMD‐DRAM consumes overall higher power than Si‐MOS‐DRAM, and shows higher average read power variability with the σ/μ = 0.476. The TMD‐DRAM also shows higher variability in the studied timing characteristics than Si‐MOS‐DRAM except merge and sense times. [ABSTRACT FROM AUTHOR]

This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment. [ABSTRACT FROM AUTHOR]

A novel reduced power with enhanced speed (RPES) technique for Static Random Access Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) instead of traditional MOSFETs which is in demand for edge AI devices, energy efficient deep neural networks, smart wearable devices and high-speed era is proposed in this paper. This work reduces propagation delay and sub-threshold leakage current using RPES technique with a power supply of 0.9V. The performance and power delay product (PDP) of 6T, 8T and 10T SRAM cells is analysed for CNTFET based RPES technique at 45nm technology. Simulated results using Stanford CNTFET model shows improvement in PDP of proposed 6T SRAM cell by 66% compared to Conv6T and 27% compared to Ternary 4TSTI 6T SRAM. Conv 8T and Diff 8T are implemented using RPES technique which shows improvement by 40.9% and 74.3% respectively. Among SE10T and Diff 10T topologies, Diff 10T has better PDP when implemented using RPES technique. All SRAM cells mentioned are analyzed for various high-k dielectric materials, oxide thickness and pitch values of CNTFET and best fitting results are proposed for SRAM cells. [ABSTRACT FROM AUTHOR]

In the prominent era of the digital world and Very Large-Scale Integration (VLSI) circuits, Static Random Access Memory (SRAM) provides a vital contribution to low-power and high-speed performance. Sense Amplifiers (SA) are a part of Complementary Metal-Oxide-Semiconductor (CMOS) memories used to read the stored information. This paper indicates a Dual-Voltage, Dual-Tail Level Restoration Voltage Latch Sense Amplifier (DVDTLR-VLSA). The design has been implemented using the LT SPICE tool at 180 nm technology node with a 1.8 V supply. Performance comparison of existing SA presented in literature with the proposed SA is examined based on different parameters like power, energy, delay, and current. The proposed design maintains power at 2.167 µW that is decreased to half as against Dual Switch Transmission Gate Voltage SA (DTGVSA) and shows an appreciable depletion. Also, the current and delay results are improved. Dimensional analysis is also done for the proposed SA to examine the performance. After that, the effect of sleep transistors on the proposed SA examines the performance in comparison to delay and power parameters without sleep transistors. The DVDTLR-VLSA has minimal energy and power. Also, the delay is improved which may be determined more advisable for low-power operations. [ABSTRACT FROM AUTHOR]