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This paper presents radiation hardened SRAM (namely LPDNUR and HSDNUR), both of which can self-recover from single-node and double-node upsets. LPDNUR uses a two-input C-element structure, which reduces the average power consumption because the stacked effect. Moreover, in order to reduce read access time (RAT) and write access time (WAT), the paper proposes HSDNUR, which uses a combination of NMOS and PMOS as the transistor for one-node data transmission, an approach that increases the current drive capability and reduces transmission delays. Compared to the state-of-the-art radiation-hardened SRAM design, such as QUCCE10T, QUCCE12T, We-Quatro, etc. The model results show that the average power consumption of LPDNUR is reduced by 24.59% on average, and the RAT and WAT of HSDNUR are reduced by an average of 35.71% and 24.14% respectively. • LPDNUR and HSDNUR fully achieve SNU and DNU recovery. • Average power of LPDNUR is 24.59% lower on average than other SRAM hardened since stack structure. • WAT and RAT of HSDNUR are 24.14% and 35.71% lower than other SRAM hardened on average by using TG. [ABSTRACT FROM AUTHOR]

Content addressable memory (CAM) is a hardware search engine (HSE) used for accelerating lookup functions in tagged cache, translation lookaside buffers (TLBs) and network routers. Despite its speedy search feature, augmentation of compare-evaluate blocks to storage units costs additional area. Activation of cells and matchlines (MLs) during search operations is responsible for huge dynamic-power dissipation. This paper proposes a shared ML scheme (SMS) based on a two-step evaluation CAM cell, in order to reduce ML transitions per word besides improving density in the comparison units. A 64 × 32-bit proposed SMS-CAM, using 45-nm CMOS technology, dissipates 1.06 fJ/bit/search and achieves 100.77-ps search time. At the cost of 6.55% sacrificial delay over a conventional CAM, the proposed CAM reduces 12.38% – 30.48% energy over a self-power off gating, the conventional and an early terminate ML precharge designs. Low energy-delay results better trade-off budget besides decreasing macro area in the SMS-CAM, which could be useful in search applications of network devices. • A 2-bit storage with common evaluation (2B-CE) involving two-step comparison • Two side-by-side CAM cells (one 2B-CE based cell) share one matchline (ML) node • Shared matchline scheme limits ML discharge to only 1 path per 2-bit mismatches • Lesser ML discharge paths with shared matchline scheme (SMS) saves dynamic power • N/2 proposed 2B-CE cells are designed in NOR-type ML to form an N-bit CAM word • SMS-CAM sustains high-speed searches owing to the parallel cells in NOR-type ML • Comparison of SMS-CAM with referred CAMs verifies performance and reliability [ABSTRACT FROM AUTHOR]

This paper presents a new family of innovative operational transconductance amplifier (OTA) topologies based on CMOS inverter structures, with improved gain and energy-efficiency. This new family of OTA designs is suitable for biomedical and healthcare circuits and systems, due to the high energy-efficiency, improved gain and low level of noise contribution, when compared to the state-of-the-art in this field. In this paper, two fully-differential implementations are presented, a first one with a double CMOS branch biased by two pairs of voltage-combiners structures in both NMOS and PMOS configurations, and a second one with folded voltage-combiners specifically targeting low voltage applications, e.g., supplies below 1 V. The usage of voltage-combiners to bias the OTAs improves the gain and the gain-bandwidth product, therefore improving the energy-efficiency figure-of-merit. High values of figure-of-merit are achieved in both implementations, i.e., more than 1600 MHz × pF/mA and 2000 MHz × pF/mA, gain values above 53 dB and 50 dB under supply sources of 2 V and 0.7 V respectively. The folded voltage-combiners biased OTA is able to operate correctly under a voltage supply down to 0.7 V with proper DC biasing. The results are finally compared with state-of-the-art in this field and the potential of the circuits is fulfilled using a state-of-the-art layout-aware integrated-circuit optimization framework, AIDA, particularly relevant in order to overcome the device stacking problematic for lower voltages. [ABSTRACT FROM AUTHOR]

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. • In dynamic comparators, the pre-amplifier amplifies the input differential signal to some extent then the latch finalizes the comparison. After some moment from the latch activation, the pre-amplifier is wasting power and sometimes reduces the gain worsening the power consumption and offset voltage. The aim of the proposed comparator is to overcome this issue. In low-offset comparators, the sizing of the input transistors of the pre-amplifier is chosen large for matching purposes so that the pre-amplifier consumes the dominant part of the total power consumption making it a good candidate to work on for low-power applications. In this paper, a low power method for dynamic comparators is presented using which the power consumption of the pre-amplifier is controlled in a proper way. Therefore, not only the power is saved but also the input referred offset voltage is improved. • In the paper, analytical derivations are presented to quantify the amount of power saving. Simulations showed the derivations are consistent with the circuit. The proposed method is able to reduce the power consumption by about 30%-40% and the offset voltage by about 20%. Post layout simulation of the RC-CC extracted circuit confirms the benefits of the proposed comparator. • The proposed method is applicable to different types of the double tail comparators. This method is simple yet effective in power reduction. [ABSTRACT FROM AUTHOR]

This paper proposed a 12-bit 2.5-bit/phase two-stage cyclic Analog-to-Digital Converter (ADC) with phase scaling and low-power Sub-ADC for CMOS image sensors. The phase scaling technique reduces the performance requirements of operational amplifiers for the cyclic ADC. Furthermore, the Sub-ADC architecture based on tri-state comparators reduces the power consumption of the Sub-ADC. The implemented cyclic ADC is designed with 110 nm process. Simulation results demonstrate that the proposed 12-bit, 1 MS/s, 2.5-bit/phase, two-stage cyclic ADC achieves an effective number of bits (ENOB) of 11.4-bit with a power consumption of 0.185 mW per column. Compared with the traditional fixed phase structure, the power consumption of the phase scaling structure is reduced by 22.3 %. Additionally, the cyclic ADC attains a Figure of Merit (FoM) of 68.5fJ/step. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient CMOS image sensor (CIS) for always-on object detection by using 1-bit log-gradient feature extraction in analog current domain. Compared with traditional image sensors with high-resolution ADCs, the proposed CIS extracts gradients in ratio form and generates feature maps at 1-bit resolution, which eliminates unnecessary background information and illumination-related data, and reduces the data computation in the later detector. The system containing the proposed CIS and back-end ANN detector is modeled with python and the simulation achieves an accuracy of 93.2 % for person detection. The CIS employs current mode divider and comparator to compute the gradient ratios. An accurate and configurable muti-input and muti-output (MIMO) current divider is proposed, composed of two cascaded modified second generation current controlled conveyors (M-CCCIIs). The proposed CIS was fabricated in a 0.18 μm standard CMOS process and realized a frame rate of 170 fps and an energy efficiency of 337 pJ/pixel in a power consumption of 1.1 mW. Experimental results show that the proposed CIS can realize the function of extracting log-gradients. [ABSTRACT FROM AUTHOR]

Abstract Most ultra low power SRAM cells operating in the sub and near threshold region deploy 8 or more transistors per storage cell to ensure stability. In this paper we propose and design a low voltage, differential write, single ended read memory cell that consists of a total of 6 transistors. The innovative idea is to bring the loadless 4-transistor latch into the realm of low voltage memory cells by exploiting features of the 28 nm FDSOI Process and by adding a 2-transistor readbuffer with a footer line. Stand-alone and on a system level, the cell is stable during read, write and hold operations and it has great write-ability due to its differential write and loadless nature. The single NWELL option in 28 nm FD-SOI allows the loadless core to have minimal device widths while greatly improving the time it takes to evaluate the read bit-line. The cell has, in this paper, been used in a 128 kb (217) SRAM in a 16 block configuration exploring 3 different types of logic libraries for the peripheral logic of the system. Depending on the application, the IO-peripheral logic may be implemented using either high threshold voltage transistors or low threshold voltage transistors in where the power consumption of the 128 kb system was found to range from 1.31 µW to 71.09 µW, the maximum operational frequency lies within 1.87 MHz and 14.97 MHz while the read energy varies from 13.08 to 75.21 fJ/operation/bit for a supply voltage of 350 mV. The minimum retention voltage of the loadless SRAM cell is found to be 230 mV covering 5 σ of variation with Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

This paper proposes a 4th-order class-AB low-pass filter (LPF) for wearable biological healthcare applications designed by cascading two 2nd-order LPFs. The proposed class-AB LPF uses quasi-floating gate (QFG), flipped source follower (FSF) and level-shifter (LS) techniques to boost its performance. The LPF is designed and validated in CMOS 180 nm technology which emulates the post-layout gain of −0.212 dB, bandwidth of 100 Hz, dynamic range (DR) of 50.26 dB, total harmonic distortion (THD) of −52.5 dB and figure of merit (FOM) of 1.71 × 10-15 J. The class-AB QFG FSF LPF consumes power and area of 0.224 nW and 0.0196 mm2, respectively. Furthermore, the statistically determined coefficient of variation for proposed LPF with 1000 iterations for gain is −0.035, THD is −0.172 and DR is 0.04, respectively. The class-AB QFG FSF LPF is compared with other LPFs which establishes its advantage in terms of low-power consumption and least figure of merit thus confirming its suitability for wearable healthcare applications. [ABSTRACT FROM AUTHOR]

This paper presents a 10 bits low-power direct digital IF to RF digital-to-analog (RF-DAC) fabricated in a 110 nm CMOS technology with a core area of 0.08 mm 2. The DAC uses sixteen current mode double balanced mixers designed without a tail transistor with different weights to convert IF output to RF output. The digital IF signal is modulated by a digital Σ − Δ modulator with 1-bit IF output. The RF-DAC with a bandwidth of 300 KHz consumes 17.3 mA from a 1.5 V supply. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power full-adder circuit based on the proper combination of dynamic logic style and Gate Diffusion Input (GDI) low-power technique is proposed in Carbon Nanotube Field Effect Transistor (CNFET) technology. Using the proposed approach, the basic logic circuits such as XOR and XNOR gates are implemented which results in a full-swing, full-adder cell in the CNFET technology. The proposed circuit is simulated in HSPICE using CNFET model parameters. Finally, the simulation results justify a good improvement in the major circuit performances such as power consumption, delay and power-delay product (PDP) parameters for the proposed full-adder circuit. • A new Dynamic-GDI Low-Power Full-Adder circuit in CNFET technology is presented. • The design is based on the proper combination of Dynamic and GDI logic design techniques. • The proposed design not only significantly reduces the power consumption, but also reduces the PDP and layout area considerably. • The performance of the proposed circuit is simulated in HSPICE, using the STANFORD CNFET model parameters. [ABSTRACT FROM AUTHOR]

The paper deals with a new solution for an ultra-low-voltage loser take all (LTA) circuit, capable to operate from supply voltages ranging from 0.3 to 0.5 V. The proposed circuit exploit the idea of multiple voltage buffers with a common output. In order to obtain a compact and precise LTA, a new kind of an ultra-low-voltage buffer has been developed. Owing to the fact that for such a low supply voltage the available voltage swing is highly reduced, the impact of transistor mismatches and speed-accuracy-power tradeoffs have extensively been discussed in the paper. While implemented in a standard 0.18 μm CMOS process, the proposed LTA circuit in a two-input version consumes 3.0 μW from a 0.5 V supply and provides 10 μs crossover recovery time for a 1 pF load capacitance. [ABSTRACT FROM AUTHOR]

This paper presents a low-voltage low-power current mode full wave rectifier. The proposed configuration operates at maximum supply voltage of ±0.75 V with quiescent power consumption of 2.1 µW, and has current range of ±100 µA. The output resistance and bandwidth of the designed rectifier are 0.89 MΩ and 85.85 MHz, respectively. Moreover, the operating frequency of the proposed rectifier is improved from 85 MHz to 153.2 MHz, by using the resistive compensation method of bandwidth extension. The proposed circuit is designed by using TSMC 0.18 µm CMOS process and BSIM3 Level 49 device model at±0.75 V. The circuits are simulated on Spectre simulator of Cadence to validate the analytical results obtained in the paper. [ABSTRACT FROM AUTHOR]

Modern battery-enabled systems, such as IoT, require SRAM cells that can maintain data and respond quickly to requests. However, achieving low-power and stable SRAM cells, which are essential for IoT systems, is not possible with CMOS technology due to scaling issues. As a result, new nanoscale devices, such as FinFET, have been introduced as a potential replacement for CMOS in SRAM design. This paper presents a new FinFET-based 8 T SRAM cell with separate reading and writing paths. The cell uses read-decoupling and write-assist pull-down path cut techniques to improve read stability and writability, respectively. Single-ended reading and writing structures reduce power consumption, and stacking transistors, along with read bitline leakage elimination, reduces leakage power dissipation. The proposed cell's efficiency is evaluated using HSPICE simulator with 10-nm FinFET technology and is compared with conventional 6 T, single-bitline 7 T (SB7T), single-ended 8 T (SE8T), and transmission gate read-decoupled 9 T (TRD9T) SRAM cells at V DD = 0.35 V. The proposed cell improves read stability by 2.59×/1.04 × and enhances writability by 1.38×/1.01 × compared to 6 T/TRD9T and 6 T/SB7T, respectively. It also reduces read power by 28.25 %/19.60 % compared to the 6 T/SB7T and reduces write power by at most 33.40 % and at least 5.46 %. Moreover, the leakage power is reduced by at least 5.80 %. However, the proposed cell increases read/write delay by 1.77×/1.40 × and shows 1.23 × larger layout area compared to 6 T. [ABSTRACT FROM AUTHOR]

In this paper, a high current efficiency two-stage amplifier using multipath nested feedforward compensation (MNFC) method is proposed. For the purpose of achieving the high current efficiency, the first stage of the amplifier uses a recycling folded cascode amplifier (RFC) and a nested small-gain stage is added between the two stages of the amplifier so that there are two paths in the feedforward path. This two-stage amplifier improves the phase margin (PM) and extends the gain bandwidth (GBW) by using the MNFC technique which can eliminate the non-dominant pole. The chip area of this two-stage MNFC amplifier which using 0. 18 μ m CMOS process is 0.01272 mm 2. The simulated and measured results shows that the phase margin(PM), DC gain, gain-bandwidth(GBW), average 1% settling time, slew rate- (SR-) and slew rate+ (SR+) is 72.7°, 104.4 dB, 4.29 MHz, 246.2 ns, 16 V/ μ s , and 6.15 V/ μ s , respectively, when the load capacitance is 120 pF. The supply voltage of this circuit is 1.8 V and the power consumption is 0.13 mW. • This multipath nested feedforward compensation (MNFC) method has higher current efficiency. • The frequency compensation effect is better than that of traditional feedforward compensation methods. • The gain-bandwidth is extended and the phase margin is improved. [ABSTRACT FROM AUTHOR]

In this paper we target the design of a dedicated low-power computing platform for neuroprosthetic applications. The system must be capable of decoding the information encoded in neural signals, to extract the patients’ motion intention. To this aim, a highly-portable and reliable integrated processing device is required. However, a commonly acknowledged design methodology, to be used in such kind of design cases, is still not available in literature. In this work, we propose and assess the adoption of the MPSoC paradigm as a prospective solution. We present a design-case of a custom MPSoC integrated solution, implementing an on-line neural signal decoding algorithm. The proposed system executes parallel software tasks onto customized ASIP processing cores. Experimental results, obtained by placement- and activity-aware power evaluations carried out using an industrial 40 nm technology node as a reference, assess that the performance and power-related features of the designed architecture are compliant with the implantability constraints and with the battery lifetime required for real-life use. Moreover, besides the effectiveness of the proposed solution, this paper demonstrates also that custom heterogeneous MPSoCs can successfully challenge ultra-low power bio-medical signal processing problem. [ABSTRACT FROM AUTHOR]

Image based sensing in wireless multimedia sensor network (WMSN) is mainly depend on the capability of the deployed scheme to ensure low-power consumption. In depth, the approach of periodic image transmission to the end user, even after compression, will shortly exhaust the energy of the sensors and dramatically reduces the network life time. Thus, detecting an event of interest and extracting the useful information's to decide at source node will avoid flooding the network with unusable data and contributes to extend the whole network life-time. The efficiency of this approach for image-based sensing, in severely resource-constrained sensors, heavily depends on the complexity of the designed sensing scheme. The main contribution of this paper is to present a low-complexity scheme using Zernike Moment to detect a new object and to recognize the appearance of a specific target before sending a notification to the end user. The paper presents the specification of the proposed scheme and its implementation on wireless multimedia sensors. It addresses the performance's evaluation in terms of time and energy consumption. The results show the high accuracy of the proposed approach to efficiently recognize the target and notify the end user with interesting performance that overcomes the efficiency of other similar sensing approaches proposed in the literature. [ABSTRACT FROM AUTHOR]

Power consumption plays a major role in present day VLSI design technology. The demand for low power consuming devices is increasing rapidly and the adiabatic logic style is said to be an attractive solution. This paper investigates different methods for designing adiabatic logics such as CMOS adiabatic circuits, ECRL, PFAL, CAL, DFAL, 2N-2P and 2N-2N2P. A lot of research has been already done using adiabatic technique. This paper presents a review of above mentioned adiabatic inverters in literature from basic elements. The SPICE simulation results show the comparison of power dissipation between conventional CMOS circuits and adiabatic logic based circuits. [ABSTRACT FROM AUTHOR]

Content addressable memory (CAM) is a specialized search engine mostly used for speeding memory lookup in network devices. Despite fast searching, activation of all comparison circuits in every clock cycle costs huge power. Power dissipation is more severe in high capacitive NOR match-line (ML) because of higher precharge activity and multiple transitions in ML. This paper proposes a two-layer ML scheme to reduce power due to frequent ML switching between precharge and evaluation phases. The complementary charging property of P and N matching circuits of NOR cells are utilized with the help of a ML precharge and sensing (MLPS) block to charge up only the matched entry while the mismatched entries are held at pre-discharged levels. Also, charging up the first layer due to mismatch limits the discharge levels of the mismatched second layer. These techniques reduce precharge activity besides lessening evaluate-power. Based on a 45-nm CMOS technology, post-layout analysis of the 64 × 32-bit proposed CAM at 1-V supply shows 56% and 24% reductions in precharge-power over a conventional CAM and a gated-power ML sensing CAM, respectively. In addition, the total ML power saving of approximately 2× is achieved when compared to a high-performance master-slave ML and a local-NOR global-NAND ML based CAMs besides decreased macro area. With the help of a charge-hold and charge-up sensing scheme, the proposed design achieves a match function in only 223.52 ps and dissipates 1.42 fJ/bit/search favouring it to be an efficient energy-delay design among the compared designs. • A novel two-layer CAM architecture using complementary charging properties of P and N match-lines. • Mismatched MLs of longer layer are discharged to low-swing to reduce precharge levels. • Matched ML of final output changes its state while mismatched MLs do not change, lessens precharge-power and evaluate-power. • A sense amplifier senses the ML states quickly based on charge-hold/up scheme. • Comprehensive analysis and comparison with referred CAM designs to demonstrate power and delay improvements. [ABSTRACT FROM AUTHOR]

With the recent surge in popularity of Convolutional Neural Networks (CNNs), motivated by their significant performance in many classification and related tasks, a new challenge now needs to be addressed: how to accommodate CNNs in mobile devices, such as drones, smartphones, and similar low-power devices? In order to tackle this challenge we exploit the Vision Processing Unit (VPU) that combines dedicated CNN hardware blocks and very low power requirement. The lack of readily available training data and memory requirements are two of the factors hindering the training and accuracy performance of 3D CNNs. In this paper, we propose a method for generating synthetic 3D point-clouds from realistic CAD scene models to enrich the training process for volumetric CNNs. Furthermore, an efficient 3D volumetric object representation Volumetric Accelerator format (VOLA) is employed. VOLA is a sexaquaternary (power-of-four subdivision) tree-based representation which allows for significant memory saving for volumetric data. Multiple CNN models were trained and pruning techniques for the weights were applied to the trained 3D Volumetric Network in order to remove almost 70% of the parameters and outperform the existing state-of-the-art networks. The top performing and efficient model was ported to the Movidius™Neural Compute Stick (NCS). After deployment on the NCS, it takes 11 ms (∼ 90 frames per second) to perform inference on each input volume, with a reported power requirement of 1.2 W, which leads to 75.75 inferences per second per Watt. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm2. The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art. [ABSTRACT FROM AUTHOR]

This paper presents a fourth-order sigma-delta (ΣΔ) ADC applied to a micro-electro-mechanical system (MEMS) gyroscope system. First, a system-level model of ΣΔ modulator containing non-ideal factors is established, and the optimal system performance of the ΣΔ modulator is determined by optimizing the feedforward path and the feedback coefficient of the feedback path. Then, the operational transconductance amplifier (OTA) with chopping technique and clock timing to control bias current in the first stage integrator of the circuit design is able to reduce not only the flicker noise of the modulator, but also reduce the system power consumption. Third, the design of other essential circuit modules is presented, and the circuit performance meets the requirements and low-power consumption is achieved. The designed ΣΔ ADC uses a 0.18 μm CMOS BCD process, with a ΣΔ modulator area of 0.64 mm2 and a digital filter area of 2.03 mm2. When the sampling frequency is 2 MHz and the signal bandwidth is 7.8 kHz, the experimental measurement results show that the proposed ΣΔ modulator with the fourth-order CIFF structure can achieve a signal-to-noise ratio (SNR) of 66.3 dB and an effective number of bits (ENOB) of 10.07 bits, with a dynamic range (DR) of 89 dB and a power consumption of 9 mW. The SNR of ΣΔ ADC after filtering is 63 dB, which meets the requirements of high DR and low-power consumption of MEMS digital gyroscope sensors. [ABSTRACT FROM AUTHOR]

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]

Abstract: The use of bed/couch occupancy sensors is imperative for certain ubiquitous computing systems such as ambient assisted living (AAL). DIA (Dispositivo Inteligente de Alarma, in Spanish) is an AAL system that allows to infer a potential dangerous action of a dependant person living alone at home. This inference is obtained by a specific sensitization with sensor nodes and a reasoning layer embedded in a personal computer. In this kind of systems, energy is a limited resource therefore sensor devices need to be properly managed to conserve energy. A first approach to solve the bed/couch occupancy detection problem is found in pressure mats, but several environmental dependencies make them weak to be an efficient and reliable solution for large volume deployments. Solutions based on force-to-resistor transducer imply a too high power consumption to be integrated on wireless sensor nodes. In our previous paper, an occupancy sensor based on force-capacitive transducer has been proposed, implemented and tested. This sensor is based on electro-mechanical film (EMFi) transducer which is able to detect force variations in a quasi-passive way and, besides, is a capacitor with variable capacitance depending on the static force exerted on its surface. This detection of force change is used to trigger an active mechanism to measure the weight by means of the transducer capacitance. In this paper, we present a new low-power circuit to measure weight, by means of the capacitance of the EMFi transducer, which enhances accuracy and power consumption, simplifies the signal sampling procedure and can be implemented as a standalone device. A low-power wireless sensor node prototype including this new design has been assembled and tested with a wide range of weights. The occupancy detection was successful and the power consumption of the occupancy sensor accounts for only 2%, which is acceptable for implementation. [Copyright &y& Elsevier]

This paper presents a performance evaluation of an ultra low-voltage non-clocked voltage comparator, designed and fabricated in a standard twin-well 130 nm CMOS technology. The comparator can handle the input voltage within rail-to-rail range and is capable of working in temperature range from −20 to 85 °C and with power supply voltage as low as 0.4 V. The comparator is intended to be employed in an on-chip energy harvester system with minimized quiescent current consumption. So-called g m / I D low-voltage design methodology in combination with the bulk-driven design approach have been selected in the circuit topology. The measurement results obtained from fabricated prototype chips, including static and dynamic parameters, are presented and discussed as well. An excellent correlation between simulations and the measured bench data has been observed with the supply voltage value of 0.6 V, while slightly less tight correlation has been reported for V DD = 0.4 V. Anyhow, simulations and measurements both confirm that the presented silicon-proven comparator topology is capable of reliable operation with power consumption within nW range. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power multi-mode Gm-C universal filter is proposed in carbon nanotube field-effect transistor (CNTFET) technology using only 11 inverters and 2 grounded capacitors. The proposed circuit reduces the power consumption effectively due to the proper use of inverters as operational transconductance amplifier (OTA) blocks. Moreover, the center frequency and quality factor of the proposed filter can be tuned electronically with low sensitivity values. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters at ±0.2 V supply voltage, and its performance is compared with the circuit proposed in 32 nm CMOS technology. As simulation results show, for certain value of center frequency, the proposed CNTFET filter not only reduces the power consumption by 66%, but also extends the center frequency up to 54%, at the same power consumption value in comparison with 32 nm CMOS technology. Finally, the proposed CNTFET filter benefits from a considerable reduction in chip area. [ABSTRACT FROM AUTHOR]

Abstract This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a new low-power CMOS optical transimpedance amplifier (TIA) for 10 Gbps applications is proposed. The main objective of this work is to achieve low-power consumption while meeting other required performances. The input resistance is considerably decreased due to the use of diode-connected input stage at the input node. Moreover, the output node benefits from an active inductive peaking technique which is used as the output load to extend the frequency bandwidth while keeping the low-power performance of the proposed TIA. Moreover, the core amplifier uses no passive elements which leads to a small chip area. Furthermore, to verify the performance of the proposed TIA, the circuit simulations are done in HSPICE using 90 nm CMOS technology parameters. So, the simulation results show the transimpedance gain of 40.5 dbΩ, -3 dB frequency bandwidth of 7 GHz, input referred noise of 20.3pA/√Hz and the power consumption value of only 1.4 mW at 1 V supply. Finally, other simulation results such as Monte-Carlo analysis, eye diagram and noise analysis justify the proper performance of the proposed TIA which can be operated as a low-power building block in a 10 Gbps optical receiver system. [ABSTRACT FROM AUTHOR]

Abstract: This paper revisits the design trade-offs for low-power and low-voltage rectifiers required for sensor interfacing in a variety of biomedical applications. The paper discusses why most previously reported rectifiers are not going to be suitable in these emerging devices since design constraints are different from those in other more conventional applications. A novel rectifier topology is presented that meets the specifications required by a wearable breathing detector and is also suitable for many other devices described in the introduction. The novel rectifier consumes up to 90nW of power, operates at only power supply voltages down to 1V and achieves a dynamic range (DR) of 73dB. The rectifier outperforms other previously reported topologies suitable for this kind of application. [Copyright &y& Elsevier]

The split-radix fast Fourier transform (SRFFT) is attractive for low-power FFT processors as it has the lowest numbers of multiplication operations among all FFT algorithms. FFT algorithms differ from one another by the location of the twiddle factor. The irregular locations of the twiddle factors in the SRFFT lead to complex address generators for the memory containing the twiddle factors. This paper proposes a novel twiddle factor addressing architecture for the split-radix FFT processor, which can effectively reduce its power consumption. This is then used to design a simple memory address generator and a low-power pipelined SRFFT. The proposed algorithm is used to implement a 1024-point pipelined circuit. Post-layout simulation shows that the proposed 1024-point design achieves over 24% and 14.7% lower power consumption for the multiplications and ROM, respectively, compared to a traditional radix-2 single delay feedback (SDF) FFT architecture. • In this paper, a novel twiddle factor addressing architecture is proposed, which can reduce the power consumption of the SRFFT processor. • Under the TSMC 65 nm process, we compared the newly proposed SRFFT processor with the traditional radix-2 FFT processor. • SRFFT processor can reduce the power consumption of the multiplier by 24% and the power consumption of the ROM by 14.7%. [ABSTRACT FROM AUTHOR]

For the processing of signals in battery-powered and portable biological healthcare systems, there is a huge requirement for low-pass-filter (LPF) architecture. However, it's challenging to achieve low-power operation of LPF with improved figure-of-merit (FOM). This paper presents a 4th-order cascoded flipped source follower filter (CFSF) which consumes ultra-low power of 0.4 nW from 0.5 V supply. The proposed architecture has been designed in 180 nm technology using BSIM3V3 MOS models. The post-layout simulation result shows that the proposed architecture delivers a gain of −4.7 dB, bandwidth (BW) of 100 Hz, dynamic range (DR) of 57.141 dB, input referred noise (IRN) of 97 μV rms , Total harmonic distortion (THD) of −40.833 dB and FOM of 1.39 × 10−15 J. The proposed architecture occupies an area of 0.052 mm2. Further, the statistically determined values for gain, DR, and THD with 200 Monte Carlo samples indicate mean values of −7.594 dB, 48.482 dB and −48.335 dB with standard deviation values of 7.063 dB, 5.779 dB and 12.316 dB, respectively. The proposed CFSF LPF architecture can be used in portable as well as wearable biological healthcare systems. [ABSTRACT FROM AUTHOR]

• Effect of channel epilayer thickness on Analog/RF-linearity performance of a U-TFET. • Optimization of channel epilayer thickness of a U-TFET in three low-power regimes. • Impact of process-induced variation in three low-power regimes for the U-TFET. In this paper, the impact of vertical channel epilayer thickness (T epi) of a unique U-TFET has been investigated in the RF domain along with its linearity aspect. Then, a glance has been thrown to the analog domain as well. The entire study has been carried out for the three low-power performance zones. After scrutinizing the linearity vs. analog/RF performance, it has been observed that the most enhanced device in the analog/RF domain is the worst performer with respect to the linearity aspect and vice-versa. This calls for optimization. The 6-nm-T epi device turns out to be the one. Next, for the first time, a unique process-induced variation study in terms of the deviated T epi from its optimized value has been introduced to find out the degree of sensitivity of different linearity parameters with respect to the deviation. Intriguingly, no single trend has been observed in terms of the dominance of linearity parameters for the said three zones – the result remains application specific. [ABSTRACT FROM AUTHOR]

Abstract This paper describes the design of 1.5–5 GHz CMOS power amplifier (PA) for broadband applications that uses 0.18- μ m CMOS technology. This UWB PA uses a cascode topology with current-reuse, to enhance the gain at the upper end of the desired band, and a resistive feedback amplifier stage to achieve optimum output power and gain while maintaining a wide bandwidth. The measured results for the proposed UWB PA show an excellent gain in flatness of 20 ± 1 dB over the 2.0–4.0 GHz frequency range. The average gain is about 17.8 dB from 1.5 to 5 GHz. The reverse isolation is less than −42 dBm. The PA has an efficiency of a maximum of 30.5% at 2 GHz, 24.8% at 3 GHz, 28.1% at 4 GHz and 15.2% at 5 GHz with a 50 Ω load termination. The amplifier delivers a P 1dB output power of 6.7 dBm and a PAE of 22% at 4 GHz is obtained with a power consumption of 24.5 mW from a 1.8 V supply voltage. The chip area is 1.222 × 1.004 mm2, including the pads. The proposed UWB PA exhibits high gain and is highly efficient. It has the highest FOM for power amplifiers in the 2–6 GHz band. Highlights • The proposed UWB PA exhibits high gain and is highly efficient. • It has the highest FOM for power amplifiers in the 2–6 GHz band. • The main advantages of the UWB PA topology are the wide bandwidth, the high gain, the very good efficiency, the moderate output power and a low power consumption. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a novel current mode enhanced input range four-quadrant analog multiplier is presented. The proposed class AB based translinear current squarer allows the designer to control the input range via a digital code. Moreover, the proposed scheme improves the linearity of the circuit and has a high robustness against process variations. The Post-layout and Monte Carlo simulations of the multiplier in a 0.18 μm standard CMOS technology show an input range of (1+m) × 10 μA (where 'm' is an adjustable parameter), a THD of 1% (@1 MHz), a −3 dB bandwidth of 332.3 MHz (for m = 3) and a power consumption of 186 μW. Highlights • A wide and programmable operating range current mode multiplier is proposed. • The structure is based on modified ‏class AB current buffer and translinearity principal. • The designer can control the input range via a digital code according to the requirements of different applications. • The proposed scheme improves the linearity and robustness of the circuit against process variation. [ABSTRACT FROM AUTHOR]

In this paper, a new high-precision, pressure sensor for sensing gas molecules using a controllable voltage-mode instrumentation amplifier (VMIA) in carbon nanotube field-effect transistor (CNTFET) technology is designed. The sensing mechanism is based on the applied force by Oxygen atoms on the surface of the carbon nanotube (CNT), which is considered as a movable electrode of sensing capacitor. The sensing mechanism is simulated in ANSYS which justifies the variations of sensing capacitance, while the sensor’s output voltage is applied to an accurate instrumentation amplifier (IA) via a switched-capacitor sensor driver. Therefore, due to the controllability of the transconductance and gain parameters of a CNTFET, the IA circuit provides a constant and controllable differential gain of up to 52 dB in a flat −3dB bandwidth of up to 3.6 MHz, which provides a tunable common-mode rejection ratio (CMRR) of up to 121 dB in a 1.8 GHz flat, −3dB frequency bandwidth. Moreover, due to the use of the differential pair stage, the total harmonic distortion (THD) value is obtained less than 0.67%. Finally, the proposed IA circuit consumes only 45.1 µW with a 22.52 nV/√Hz equivalent input referred noise value at ±0.5 V supply. [ABSTRACT FROM AUTHOR]

This paper proposes a new gate driver circuit using depletion mode a-IGZO TFTs. The proposed gate driver circuit can prevent Q node, the gate node of pull-up TFT, from discharging during the output pulse duration. For that purpose, our circuit applies sufficient negative gate-to-source bias (V gs ) to the switch TFTs connected to the Q node during that time. Consequently, the leakage current through them is suppressed even though they have a negative threshold voltage (V th ). The proposed circuit has eleven transistors and two capacitors and it requires only two clock signals, which enables us to adopt the circuit at minimum extra cost. It works properly even when V th is as low as −7.1 V. The normalized power consumption of the proposed circuit is also lowered compared with the previously reported circuits when the transistor has negative V th . The power consumption of the proposed circuit for V th of −5 V increases only nine times that for V th of 3 V. [ABSTRACT FROM AUTHOR]

Secure transmission of multimedia contents is computationally challenging due to the sheer volume of data involved, and achieving this by fully encrypting multimedia contents is not a viable solution for mobile devices, as they run on limited battery power and employ relatively slower processors compared to their desktop counterparts. Also, in some particular application scenarios, the value, secrecy, and/or privacy of the information is time dependent and short lived. This paper presents a highly scalable approach for securing multimedia streams on mobile devices by encrypting intelligently only selected portions of the bit stream. More importantly, the proposed solution works mainly on compressed bit stream and does not require any media decoding. It encrypts on the average less than 3% of a packet load and provides robust security equivalent to that of a fully encrypted bit stream. This solution has been implemented on desktop, laptop, netbook and Nokia N series platforms. The proposed scheme is approximately 15 times faster (on average) and processes 8 to 12 times more information for a given battery life when compared to a state of the art full encryption based solutions. [ABSTRACT FROM AUTHOR]

A novel full-swing, low-power and energy-aware full adder using hybrid logic scheme is presented in this paper. At first, a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T XOR-XNOR gates combined with a feedback loop. The performance of this new cell is compared with some reported ones and then, using this new cell and two other modules, a novel full adder circuit is proposed and evaluated in TSMC 0.18 μm CMOS process technology. Post-layout simulations using Cadence Virtuoso tool showed 33%–74% and 35%–81% improvement in terms of power consumption and power-delay product (PDP), respectively, compared with some well-known counterparts in the literature. Furthermore, high-performance claim of our proposed full adder cell is verified through the process, voltage and temperature (PVT) variations' simulation of the adders. Finally, implementation of different full adders in 4-bit ripple carry adders (RCAs) proved our new design has high performance in the aspects of power dissipation and PDP. [ABSTRACT FROM AUTHOR]

This paper presents a bandgap reference with a high-order curvature compensation circuit which can improve the temperature coefficient (TC) in a wide temperature range. The proposed compensation circuit includes a second-order and a third-order curvature current generators as well as an I-V converter. These two curvature currents are achieved by utilizing the exponential behavior of sub-threshold MOSFET and used for compensating the high-order temperature dependence of BJT base-emitter voltage via I-V converter. The proposed BGR is implemented in a CMOS 0.18 μm process with the active area of 0.056 mm 2 . Measurements on ten samples showed that at the minimum supply voltage 1.2 V, the TC varies from 1.7 to 6.9 ppm/°C over a temperature range of 170 °C (−45 °C–125 °C) with an average value of 3.0 ppm/°C and the total current consumption of 3.6 μA at room temperature. In the supply voltage range of 1.2–1.8 V, the line regulation (LR) is 0.025%/V. [ABSTRACT FROM AUTHOR]

In this paper, a new ultra low-power universal OTA-C filter which can properly operate in all modes of operation (voltage, current, trans -resistance and trans -conductance) is presented. However, in order to reduce the power consumption effectively, the proposed circuit uses subthreshold transistors which are biased at I a = 50 nA, I b = 150 nA. Furthermore, using the bulk-drive technique leads to a reduced power consumption as well as the supply voltage of ±0.3 V. Moreover, the grounded capacitors are used to effectively reduce the parasitic effects. However, the result of sensitivity analysis shows that the proposed circuit has a very low sensitivity to the values of active and passive circuit elements such as: trans -conductance (g m ) and capacitance (C) values. Furthermore, the proposed circuit uses the minimum number of active elements to effectively reduce the power consumption as well as the chip area. Finally, the proposed filter is designed and simulated in HSPICE using 0.18µm CMOS technology parameters, while HSPICE simulation results have very close agreement with theoretical results obtained from MATLAB, which justifies the design accuracy and low-power performance of the proposed universal filter. [ABSTRACT FROM AUTHOR]

This paper presents a dual-channel low-noise bio-signal amplifier for the low-power wireless body area network (WBAN) nodes. A dual-channel three-input current-reuse (DTCR) structure is proposed to optimize the noise performance of amplifier. The chopper-stabilized technique is employed to reduce 1/f noise and the offset voltage. Moreover, a high input impedance is achieved by using the pre-charge technique. In addition, a DC offset canceling loop is employed to suppress the electrode offset. The proposed amplifier is implemented in a standard 0.18 μm CMOS process with an active area of about 0.68 × 0.73 mm 2 . The experimental results demonstrate that an input referred noise of 1.12 μV rms has been achieved over a bandwidth from 0.35 Hz to 150 Hz. The total power consumption of each channel is about 1.44 μW at the supply voltage of 1.2 V. And the amplifier achieves an input impedance of about 200 MΩ, a CMRR of 111 dB at 50 Hz and a PSRR of 87.5 dB at 50 Hz. [ABSTRACT FROM AUTHOR]

In this paper a new low-power high-speed offset-compensated dynamic latched comparator is presented. The proposed comparator uses a two-stage charge-steering preamplifier to achieve high pre-amplification voltage gain. Higher input voltage range of the latch stage significantly reduces the delay time of the latch and relaxes the need for high current in the regeneration process which ensures low-power structure. In addition, a new digitally controlled offset cancellation circuit based on the current-steering structure is used to reduce the offset of comparator. Offset voltage reduction in the startup time is the key advantage of the proposed calibration technique which does not require refreshing the offset cancellation process. Post-layout simulation results in 0.18 µm standard TSMC CMOS process show that the designed comparator dissipates 135 µW of power consumption from a 1.2 V supply voltage and has the 1 mV accuracy while operating at 1 GHz clock frequency. The power and delay time of the proposed comparator are less than about 10% of the new state-of-the-art comparator. Furthermore, from the Monte-Carlo analysis, the standard deviation of the input referred offset voltage in typical process corner and temperature is obtained about 17.53/1.09 mV before and after offset cancellation, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low-power two-step double-data-rate (TS-DDR) counter without calibration for column-parallel single-slope analog-to-digital converter (SS ADC) in CMOS image sensor. A resolution alterable TS counting logic, which drives counting circuit to operate as a (N + M)-bit counter for the fine quantization and a M-bit MSB counter for the coarse quantization, is proposed to reduce the dynamic power consumption. As no calibration is required, the proposed counter is compatible with both digital correlated double sampling (D-CDS) and digital correlated multiple sampling (D-CMS). Moreover, a DDR structure without phase matching required for TS counter is employed to further reduce the power consumption. The proposed TS-DDR counter is implemented in 12-bit column-parallel SS ADCs for a CMOS image sensor. As a result, the proposed TS-DDR counter achieves a power consumption saving of at least 55.2% compared to a traditional one. The proposed SS ADC consumes 47.6 μW and has a DNL of +0.45/-0.55 LSB and an INL of +0.73/-2.36 LSB each column at 6.1 μs conversion time. [ABSTRACT FROM AUTHOR]

Approximate multipliers are widely used in error-tolerant applications to improve circuit performance. For signed multiplication, previous approximate Booth multipliers usually have a large relative error with operands around "0", while approximate leading one detector based (LOD-based) multipliers are not energy-efficient due to the extra preprocessing module. In this paper, a low relative error leading one/zero detector based approximate multiplier (LOZDAM) is proposed for signed multiplication, which dynamically truncates the operands according to the location of their most significant bits for signed complement data. Its accuracy can be configured to suit fault-tolerant applications with different accuracy requirements. A compensation strategy is proposed to reduce the calculation error of LOZDAMs at a low cost. All proposed designs are evaluated in 28nm/0.9 V/TT/25 °C CMOS. Compared with the exact design, the proposed LOZDAM6/7/8/9 with the width of Booth multiplier being 6/7/8/9-bit reduces average power by 64%/43%/33%/21%, with the mean relative error distance by 2.94%/1.46%/0.73%/0.36%, respectively. Case studies of image sharpening and serial Fast Fourier Transform system both show acceptable error and good power/area savings, which verifies the feasibility of our designs. In general, our proposed LOZD-based approximate multipliers achieve both high accuracy and low power. [ABSTRACT FROM AUTHOR]

This paper presents a capacitor sample-hold oscillator architecture which realizes temperature-stabilized operation without a precise reference generator by using a capacitor to sample-hold the peak charge voltage of the previous phase as the reference for the current phase. Due to its dual-way charging and discharging structure, the peak charge voltage for each phase will eventually stabilized around half the supply voltage. The frequency of the oscillator depends on the RC time constants of capacitors charging (discharging) across passively-temperature-stabilized resistive elements and the comparator delay time. By analyzing the temperature characteristics of the comparator delay time and using temperature compensated bias currents to achieve temperature stabilization of the delay time, this architecture improves the overall temperature stability. This architecture has been designed and verified in 0.18-μm CMOS technology. The simulation results demonstrate this design consumes 7.99 μW from a 1.8 V supply voltage at 58.9 kHz and achieves a temperature stability of best 22.19 ppm/℃(TT Corner) from −40◦C to 90◦C, and frequency variations of ± 0.3 % for supply changes from 1.25 to 1.8 V. [ABSTRACT FROM AUTHOR]

Static random access memory (SRAM) is a critical cell of VLSI, which is sensitive to the charge generated by high-energy particles and susceptible to logical errors. In this paper, the cross-coupled 18T SRAM cell (CC18T) is proposed, which uses the NMOS stack structure to reduce average power consumption, and employs redundant transistors to build a feedback loop to improve reliability. The model simulation results show that CC18T can fully achieve single-node-upset recovery and partial double-node-upset recovery. Compared with RHMD10T, QUCCE10T, QUCCE12T, We-Quatro, S4P8N, S8P4N, DNUCTM, DNUSRM, SESRS and SEA14T, the average power consumption of CC18T is reduced by 30% on average, the read access time and write access time are also reduced by 9.27% and 10.35% on average. [ABSTRACT FROM AUTHOR]

Physical unclonable function (PUF) is a promising hardware security primitive for secure key generation and chip identification. This paper proposes a multi-port and low-power PUF based on MOSFET current-division deviation. Owing to the multi-port, it can parallelly generates multi-bit identifications (IDs) in one clock cycle. Moreover, with the MOSFET current-division array operating at sub-threshold region, it displays a low power consumption characteristic. As an embodiment, a 32-port PUF is implemented with full-custom design on 65 nm CMOS process, wherein the layout area and the power dissipation are 35178 µm 2 and 10.3 μW (@1.2 V/100 MHz), respectively. Post-layout simulation results show that it has a high performance in terms of randomness and uniqueness. In addition, it exhibits a worst case reliability of 98.62% over temperature range of – 40 °C to 120 °C and 10% fluctuations in supply voltage, indicating an encouraging reliability and effectiveness. [ABSTRACT FROM AUTHOR]

A low-power low-supply high-LR high-PSR MOSFET-only voltage reference is proposed in this paper. The proposed voltage reference is designed in the standard 0.18 µm CMOS process. In the typical case, when the temperature sweeps from −20 °C to 80 °C, the simulation result shows that the proposed voltage reference achieves a temperature coefficient of 25 ppm/°C. And the line regulation is as high as 0.067%/V, at room temperature. At the low frequency (<100 Hz), a PSR of 44 dB is obtained. The reference succeeds in working at the supply voltage as low as 0.6 V, with the power consumption being 31nW. The proposed voltage reference occupies an area of 130 µm × 55 µm. [ABSTRACT FROM AUTHOR]

The design of ultra-low cost wireless body sensor networks for wearable biomedical monitors has been made possible by today technology scaling. In these systems, a typically multi-channel biosignal sensor takes care of the operations of acquisition, data compression and final output transmission or storage. Furthermore, since these sensors are usually battery powered, the achievement of minimal energy operation is a fundamental issue. To this aim, several aspects must be considered, ranging from signal processing to architectural optimization. In this paper we consider the recently proposed rakeness-based compressed sensing (CS) paradigm along with its zeroing companion. With respect to a standard CS base sensor, the first approach allows us to further increase compression rate without sensible signal quality degradation by exploiting localization of input signal energy. The latter paradigm is here formalized and applied to further reduce the energy consumption of the sensing node. The application of both rakeness and zeroing allows for trading off energy from the compression stage to the transmission or storage one. Different cases are taken into account, by considering a realistic model of an ultra-low-power multicore DSP system. [ABSTRACT FROM AUTHOR]

This paper presents a high-stability low-power 10 T (HSLP10T) sub-threshold SRAM cell with single-ended operations. The HSLP10T cell uses a decoupled read path, formed by a transmission gate and a dynamic inverter, thereby, resulting in read stability improvement. In addition, it employs a feedback-cutting transistor to facilitate the write operation, which increases writability. Due to single-ended operations, direct-write on complementary node, floated bitline, and use of more p-type transistors, the power consumption reduces in the proposed cell. Simulated results in the 7-nm FinFET technology indicate that at a 300 mV supply voltage, the read stability/writability of the proposed HSLP10T cell is 2.06X/1.31X as that of the conventional 6 T cell. Moreover, the dynamic/leakage power consumption is reduced by 1.82X/2.92X when compared with the conventional 6 T SRAM. The proposed HSLP10T SRAM bitcell has a layout area of 0.047 µm2, which is 1.67 × larger than the conventional 6 T SRAM. However, the highest ON-to-OFF currents ratio related to the proposed design compensates for this area overhead by connecting more number of cells to the same bitline in the columns of the SRAM array. Moreover, the minimum operation voltage is reduced by 48.28 % using proposed design compared to the conventional 6 T SRAM. [ABSTRACT FROM AUTHOR]

This paper presents a methodology to estimate the dissipation of energy in hardware, at any level of abstraction, with Powersim. Powersim is a C++ class library aimed to the calculation of energy dissipation of hardware described in SystemC. To this end C++ operators are monitored and a different energy model is used for each data type. Energy models are functions of operator inputs, constant parameters and variables, like supply voltage. The main advantage of this approach is that energy estimation does not require any change in the source code describing the hardware. As application examples, the computational complexity of a JPEG encoder, implemented in a FPGA, and a FIR filter, implemented in a microcontroller, are presented. [ABSTRACT FROM AUTHOR]