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This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al 2 O 3 . Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator. The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability. [ABSTRACT FROM AUTHOR]

This paper reviews most recent results concerning reliability of InP-based and metamorphic high electron mobility transistors (HEMTs). Thanks to research work carried out in the last 10 years, a deeper understanding of failure mechanisms of these devices has been achieved, and process and technology solutions have been found for the control of premature breakdown (related to the reduced energy gap of InGaAs) and of parasitic effects, such as “kink” effects, and transconductance frequency dispersion. After a brief description of impact-ionization effects in InGaAs, an analysis of failure modes and mechanisms of InP and metamorphic HEMTs is carried out, including hot-carrier-induced degradation, gate sinking and Schottky/ohmic contact interdiffusion, hydrogen effects, and donor compensation due to fluorine atoms indiffusion. Results show that reliability of these devices is continuously improving, opening the way for applications in microwave and millimeter-wave systems. [Copyright &y& Elsevier]

• Record current density for a 2 μm thick-CdTe based devices. • Cd-rich absorber is beneficial for CdSeTe/CdTe solar cells. • Reduction of deep levels (negative U-center) by Se diffusion. Recently, the introduction of a CdSe x Te 1-x (CST) buffer in the CdTe absorber has increased the photon absorption at both short wavelengths in the visible range (by removal of the parasitic absorption of the CdS layer) and at the infrared range (by reduction of the absorber band gap). But, moreover, the efficiency improvement is also attributed to a longer minority carrier lifetime when Se is added. This paper presents CdSe x Te 1-x /CdTe devices fabricated by evaporation at low substrate temperature and with a reduced absorber thickness (2 µm). These cells achieve record current densities, exceeding 28 mA/cm2 for this absorber thickness with efficiencies close to 15 %. We have compared CdSe x Te 1-x /CdTe devices made with different approaches and we have found that the performance improvement is due to a lower amount of interstitial Te in the absorber, suggesting that the increase of the minority carrier lifetime is connected with a change of the stoichiometry due to the selenium diffusion. [ABSTRACT FROM AUTHOR]

Abstract: The purpose of this work is an in depth reliability analysis of Blu-Ray InGaN laser diodes (LD) submitted to CW stress at different currents and temperatures. During reliability tests, LD devices exhibit a gradual threshold current increase, while slope efficiency is almost not affected by the ageing treatment. Furthermore we demonstrate that: (i) the degradation rate shows a linear correlation with stress current level; (ii) the Ith increase is correlated to the decrease in non-radiative lifetime (τnr ); (iii) stress temperature acts as an accelerating factor for LD degradation; (iv) pure thermal storage does not significantly degrade LDs characteristics. [Copyright &y& Elsevier]

In this paper we report on the study of sintered ceramic composites based on a low melting glass in which ZnO nanocrystals and commercial YAG:Ce3+ phosphor are embedded. A low T g is necessary to avoid high temperature sintering which can damage the optical properties of the embedded phosphor, while ZnO is introduced to increase the thermal conductivity of the system. The compositions have been optimized in terms of stability, sintering efficiency and thermal conductivity. Selected samples were optically characterized using a GaN high power multimode 450 nm Laser Diode, with a maximum output power of 1.6 W at 1.5 A. [ABSTRACT FROM AUTHOR]

• CdSe is applied for the first time as buffer layer on vacuum evaporated Sb 2 Se3. • Higher current densities are obtained with CdSe. • Diffusion of S in Sb 2 Se 3 is demonstrated. • Se loss in the absorber for devices with CdS is shown. • Se Sb antisite is observed with CdSe is applied as buffer layer. • Sb 2 Se 3 show high stability after 7000 h under 1 sun and 80 °C. In this work, for the first time, CdSe is applied as a buffer layer on thermally evaporated Sb2Se3-based solar cells on superstrate configuration. The influence of this buffer layer on the growth of Sb 2 Se 3 and the performance of the finished devices have been analyzed and compared with the typical CdS/Sb 2 Se 3 junction. Selenium vacancies in Sb 2 Se 3 thin film act as recombination centres, for this reason applying an excessive amount of Se is beneficial to the performance of the devices. In the case of the CdS/Sb 2 Se 3 structure, the high concentration gradient enhances the selenium diffusion into the CdS and the sulphur diffusion into the Sb 2 Se 3 resulting in an increased number of defects. The replacement of CdS with CdSe would allow us to avoid this detrimental effect. In this work, we show that CdSe improves the external quantum efficiency in the entire light spectrum, increasing the average current density of the devices up to 2 mA/cm2 in comparison to CdS/Sb 2 Se 3. Also, the fill factor improves while the Voc slightly decreases due to the narrower band gap. Moreover, CdSe/Sb 2 Se 3 samples demonstrate excellent stability under accelerated stability tests. [ABSTRACT FROM AUTHOR]

We analyze the impact of scaling on the off-state, three-terminal, lateral breakdown of 100 V E-mode p-GaN/AlGaN/GaN HEMTs for low-voltage/low on-resistance applications. To this aim, we compared device structures with different SiO 2 dielectric thickness below the field plate, and varying gate-to-drain spacing and field-plate dimensions. The results indicate that: a) the breakdown voltage depends on the geometry and on the thickness of the dielectric under the field plate (t Si O 2 ) ; b) scaling the dielectric thickness increases the sensitivity of breakdown voltage to the gate-drain distance, while preserving device robustness (breakdown voltages above 150 V for a 100 V technology); c) for the devices with thinner dielectric, breakdown voltage scales linearly with gate drain distance, and with field plate length. A further analysis of the data reveals that the critical parameter in terms of reliability is the distance between the field-plate edge and the drain contact; d) scaling of the dielectric thickness does not enhance charge trapping phenomena. In summary, the results provide guidelines for scaling GaN HEMT device dimensions, while preserving reliability and immunity to charge trapping phenomena. • Breakdown voltage depends on geometry and on the thickness of the dielectric under the field plate; • Scaling dielectric thickness increases the sensitivity of breakdown voltage to the gate-drain distance preserving robustness; • Wafer with thinner dielectric is sensitive to either a variation in gate-drain spacing, or in field plate length; • Scaling of the dielectric thickness does not enhance charge trapping phenomena. [ABSTRACT FROM AUTHOR]

Abstract One of the major improvements for CdTe solar cells is the increase of the current density by enhancing the transparency of the buffer layer. CdS, with its 2.4 eV band gap, results in being opaque at low wavelength regions. For this reason, in order to gain in blue and UV light, extremely thin CdS has to be applied, if the buffer is not substituted with other materials. On the other hand, by thinning the CdS layer we create pinholes also due to the wide intermixing of CdTe and CdS layers and subsequently consumption of CdS. For this reason we have applied and compared different CdS post-deposition treatments in order to stabilize the layer and avoid excess intermixing. Treatments at temperatures above 500 °C in an argon and chlorine atmosphere on 80 nm thick CdS have led to the fabrication of more stable samples compared to untreated CdS, resulting in improved performance with a 10% increase in current density and a 5% increase in open circuit voltage and fill factor. Moreover, light transmission of the CdS treated layers from 300 to 450 nm is increased by about 10%. In this paper, a study of treated thin CdS with recrystallization treatments is presented; the layers have been analysed by means of X-ray photoelectron spectroscopy, X-ray diffraction and atomic force microscopy. Finished CdTe devices made on thin CdS are characterized in terms of current-voltage and quantum efficiency. Highlights • Thin CdS layers were treated in vacuum, argon and with Cl 2 containing gases. • Difluorochloromethane was used for CdS treatment for first time. • Cl 2 -treated thin CdS layers reduce open circuit voltage loss. • Difluorochloromethane treatment changes morphology and structure of CdS. [ABSTRACT FROM AUTHOR]

Abstract CdTe thin film solar cells are the most successful thin film photovoltaic devices in terms of production yield, as attested by the remarkable market performance. Typically the junction is made with n-type CdS that, however, absorbs some of the light spectrum due to its band-gap of 2.4 eV. Therefore, in order to exceed 20% efficiency it is crucial to increase the wavelength range convertible by the absorber. One possible alternative buffer that, at the same time, allows a larger transparency and a proper band alignment with CdTe is Magnesium Zinc Oxide (MZO). In this paper, we present low temperature CdTe solar cells in superstrate configuration without CdS, by the introduction of MZO as buffer layer. Efficiencies above 12% have been obtained, with remarkable open circuit voltage and superior values of current density. The transmission and band gap of the different MZO layers have been analysed and presented. Moreover, the optimum type of MZO layer, made with higher oxygen content and with a band gap of 3.72 eV, has been characterized by X-ray diffraction, and its morphology has been studied by atomic force microscopy, whereas the finished cells have been characterized by current-voltage and by external quantum efficiency measurements. Highlights • Low substrate temperature CdTe/MZO solar cells prepared for the first time. • Efficiencies close to 13% have been obtained. • Improved current density with high values of open circuit voltage are achieved. • Best performances obtained by using a Mg 0,23 Zn 0,77 O with a band gap of 3.72 eV. • Magnesium content in the film influenced by O 2 quantity during sputtering. [ABSTRACT FROM AUTHOR]

Abstract We studied the hysteresis and electric field effects on planar CH 3 NH 3 PbI 3 perovskite devices, synthetized from laser-ablated precursors, by means of electrical characterizations at different scan rates and optical measurements. The aim of our investigation is to characterize the phenomena behind perovskite degradation under prolonged applied electric field. Using a perovskite more resistant to electric field induced degradation, we run long time characterizations that were not accomplishable before. Thus, we distinguished all the degradation-involved phenomena. The results point to the presence of ions migrating in the perovskite when the device is biased. Our data showed that ion migration degrades the interfaces with the consequent creation of degradation layers that limit the current injected in the device and the extracted photocurrent. These layers where detected also by means of optical Raman characterization. In order to explain the details of the mechanisms concurring to the observed behaviors, we presented a qualitative model. The observed phenomena exacerbated by the planar structure are even more destructive on standard solution processed perovskites to which the results of this work can be extended. Since, the same degradation dynamics occur on vertical devices, typical on perovskite solar cells, this work provides a useful in-depth analysis of the ionic migration effects. Highlights • Investigation of the I-V curves of perovskite in a planar structure at ultra-low scan rates. • Band diagrams of perovskite processed from laser-ablated precursors by optical characterization. • Ionic migration as a cause of limited current injection and photocurrent extraction. • Raman characterizations as a tool to verify the degradation. • Hysteresis and degradation explained with a band diagram model showing the functions of ions. [ABSTRACT FROM AUTHOR]

This paper reports an overview of the most relevant trapping and degradation mechanisms that limit the performance and lifetime of GaN-based transistors for application in power electronics. Results obtained on state-of-the-art devices are described and discussed throughout the paper, with the aim of providing a clear description of the topic. The first part of the paper deals with the issue of dynamic-R on : after describing a robust test strategy for the analysis of the pulsed characteristics of the devices, we discuss the voltage- and temperature-dependent pulsed I-V characteristics of 650 V-rated transistors, and the physical origin of dynamic R on in these devices. The results demonstrate that through proper buffer optimization it is possible to reach negligible trapping at high voltage. The properties of the traps responsible for dynamic-R on are also discussed in detail in the paper, based on drain-current transient data. A specific discussion is devoted to hot-electron trapping processes, that – under hard switching conditions – may lead to significant modifications in the resistance of the 2DEG. The second part of the paper deals with device degradation: based on a wide set of experimental results, we describe the physical mechanisms responsible for the worsening of the properties of the devices. More specifically, we demonstrate that stress in off-state conditions may result in measurable changes in the pinch-off voltage, mostly consisting in a negative-threshold instability (NBTI). The origin of this shift is discussed in detail; we also demonstrate that in a real-life cascode configuration (where a low, subthreshold leakage current flows through the device in the off-state), NBTI effects are mitigated. Finally, we discuss the stability of the gate-stack, induced by the exposure to positive gate bias. [ABSTRACT FROM AUTHOR]

We investigate the degradation of AlGaN/GaN MIS-HEMTs submitted to gate step-stress experiments, and demonstrate the existence of field- and hot-electron induced processes. When the devices are submitted to gate-step stress with high V DS > 50 V, four different regimes are identified: (i) for V GS < − 10 V, no significant degradation is observed, since the devices are in the off-state; (ii) for − 10 V < V GS < 0 V, hot electrons flow through the channel, as demonstrated by the (measurable) electroluminescence signal. These hot electrons can be trapped within device structure, inducing an increase in the threshold voltage. (iii) for V GS > 0 V, the density of hot electrons is significantly reduced, due to the increased interface scattering and device temperature. As a consequence, EL signal drops to zero, and the electrons trapped during phase (ii) are de-trapped back to the channel, where they are attracted by the high 2DEG potential. (iv) Finally, for V GS > 5 V, a significant increase in threshold voltage is detected. This effect is observed only for high positive voltages, i.e. when a significant leakage current flows through the gate. Such gradual degradation is ascribed to the injection of electrons from the 2DEG to the gate insulator, which is a field-driven effect. These results were obtained by combined electrical and optical characterization carried out at different voltages during the step stress. [ABSTRACT FROM AUTHOR]

In this paper we present for the first time flexible CdTe solar cells deposited on ultra-thin glass using a low temperature process and compared the results to CdTe cells deposited on polyimides. The effects of the different substrates on the morphology and crystal structure of CdTe absorber layers, as well as on the efficiency of solar cells were investigated by means of different characterization techniques. Atomic force microscopy measurements showed that the CdTe layers deposited on different substrates have a similar morphology. XRD analysis was used to study the structure and the orientation of the crystallite of the CdTe layers on the different substrates. Micro-Raman spectroscopy provided evidence of both the TO phonon of CdTe and the A1 phonon of Te, whose peak position is somehow dependent from the substrate material. CdCl 2 treatments change the crystal orientation of the CdTe layers, with the loss of preferential orientation. In the case of the polyimide substrate it has been seen that its transparency decreases after CdCl 2 activation treatment, resulting in a parasitic light absorbance and in lower photo-current values of the devices. Moreover strain of the CdTe surface is observed for cells deposited on polymers. Cells on ultra-thin glass do not show these issues, confirming the glass to be an interesting alternative substrate for flexible CdTe solar cells. [ABSTRACT FROM AUTHOR]

This paper investigates the robustness of normally-off High Electron Mobility Transistors (HEMTs) with p-GaN gate submitted to forward gate bias overstress. By means of combined DC and spectral analysis we demonstrate the following results: (i) the devices demonstrate a time-dependent failure mechanism; (ii) time to failure (TTF) can be described by a Weibull distribution with a shape factor higher than 1, suggesting a wear-out failure; (iii) the devices have an estimated 20-years lifetime for a gate voltage of 7.2 V; (iv) TTF is temperature-dependent, with an activation energy of 0.5 eV; (v) emission microscopy reveals the presence of hot spots, whose emission originates from yellow luminescence and/or hot electron radiation. [ABSTRACT FROM AUTHOR]

GaN-based solar cells with InGaN multiple quantum wells (MQWs) are promising devices for application in space environment, concentrator solar systems, wireless power transmission and multi-junction solar cells. It is therefore important to understand their degradation kinetics when submitted to high-temperature and high-intensity stress. We submitted three samples of GaN-InGaN MQW solar cells with p-AlGaN electron-blocking-layer with different thickness of the p-GaN layer to constant power stress at 310 W/cm2, 175 °C for several hundred hours. The main degradation modes are a reduction of open-circuit voltage, short-circuit current, external quantum efficiency, power conversion efficiency and electroluminescence. In particular, we observed that a thinner p-GaN layer results in a stronger degradation observed on the cell operating parameters. The analysis of the dark I-V characteristics showed an increase in low-forward bias current and the analysis of electroluminescence showed a decrease in the electroluminescene emitted by the (forward biased) cell, as a consequence of stress. This work highlights that the cause of degradation is possibly related to a diffusion mechanism, which results in an increase of defect density in the active region. The impurities involved in the diffusion processes possibly originate from the p-side of the devices, therefore a thicker p-GaN layer reduces the amount of defects reaching the active region. [ABSTRACT FROM AUTHOR]

The role of deep defects and their physical origin in InGaN/GaN LED are still widely investigated and debated, in particular their impact on the electrical and optical characteristics and on the reliability of the device. In this paper we evaluate the electrical and optical behavior of a single quantum well InGaN/GaN 420 nm LED during a medium-term accelerated ageing test. From these measurements, an increase in the sub-turn on current was observed: this process was ascribed to the stress-induced generation of defects in proximity of the active region and thus related to an increase of the correlated trap assisted tunneling. Subsequently we modelled the device electrical characteristics, evidencing the fundamental role of deep defects in determining the shape of the I-V curve in low forward bias. We reproduced with high accuracy the experimental current-voltage curves acquired during the ageing test, demonstrating that the increase in forward leakage can be entirely ascribed to the increase in concentration of a sole defect deep level located near midgap. These results provide a better understanding about the defect formation mechanism, that can be used to model and understand the behavior of the devices during ageing. • SQW InGaN/GaN LED under constant current stress test • Deep defects • Increase in trap assisted tunneling-related current observed • A model capable of emulating the electrical behavior of the devices • Simulations highlight the role of deep levels in the quite early ageing of the device [ABSTRACT FROM AUTHOR]

The aim of this work is to develop an equivalent circuit model for the metal-organic semiconductor-electrolyte structures that are typically used as transducers in biosensor devices. In particular, a perylene derivative material is implemented in the active layer of a gold-semiconductor-electrolyte stack. Our approach is extending the standard range of the bias voltages applied for devices that operate in water. This particular characterisation protocol allows to distinguish and investigate the different mechanisms that occur at the different layers and interfaces: adsorption of ions in the semiconductor; accumulation and charge exchange of carriers at the semiconductor/electrolyte interface; percolation of the ionic species through the organic semiconductor; ion diffusion across the electrolyte; ion adsorption and charge exchange at the platinum interface. We highlight the presence of ion percolation through the organic semiconductor layer, which is described in the equivalent circuit model by means of a de Levie impedance. The presence of percolation has been demonstrated by environmental scanning electron microscopy and profilometry analysis. Although percolation is much more evident at high negative bias values, it is still present even at low bias conditions. The very good agreement between the model and the experimental data makes the model a valid tool for studying the transducing mechanisms between organic films and the physiological environment. [ABSTRACT FROM AUTHOR]

Highlights: [•] Analysis of the robustness of RGB LEDs and LED modules submitted to ESD. [•] Description of the correlation between semiconductor material and ESD failure threshold. [•] Analysis of the dependence on the failure threshold of the individual LEDs in the chain. [Copyright &y& Elsevier]

Abstract: This work presents a detailed analysis of the degradation of Si-based solar cells submitted to reverse-bias stress; the study is based on electrical, electro-optical and thermal measurements, carried out at the different stages of the stress tests. The results show that exposure to reverse bias may induce severe modifications of the cell electro-optical performance: the most relevant failure mechanism is the increase in localized shunt resistance components. The changes in the leakage paths have been investigated both through infrared thermal imaging and SEM measurements. [Copyright &y& Elsevier]

Highlights: [•] Probability distribution functions of GaN buffer breakdown voltage were determined. [•] A time dependent behaviour of vertical breakdown was observed. [•] Vertical breakdown paths were localised by backside infrared microscopy. [•] The strong localisation of the breakdown paths is due to current filamentation. [•] Roles of buffer defects and self-heating effects have been discussed. [Copyright &y& Elsevier]

Abstract: With this paper we present an analysis of the degradation of state-of-the-art high power LEDs. Three different kinds of commercially available samples, from leading manufacturers, were submitted to stress under various current and temperature levels. Based on an accurate estimation of the thermal resistance of the devices, iso-thermal and iso-current stress tests have been carried out, with the aim of separately evaluating the role of current and temperature in determining the degradation of the LEDs. Results indicate that state-of-the-art LEDs can show a significant degradation of their electrical and optical characteristics, when they are operated close to their current/temperature limits. In particular, data reveal the presence of two different degradation mechanisms: (i) the degradation of the blue semiconductor chip, due to the increase in non-radiative recombination, or to the decrease in the acceptor dopant concentration at the p-side of the diodes; (ii) the chemical degradation of the package, with subsequent worsening of its optical properties. Results suggest that even high-performance LEDs can suffer from limited lifetime: thermal management and driving conditions must be carefully optimized with the aim of achieving high reliability for LEDs to be adopted in high efficiency lighting systems. [Copyright &y& Elsevier]

Abstract: The EOS/ESD sensitivity of the main circuit blocks of a complete GaAs multi-stage power amplifier for microwave applications was investigated under HBM, MM and TLP regimes. Hard breakdown failure modes were identified due to passive components failure. The high current injection state of active components was also analyzed. [Copyright &y& Elsevier]

Abstract: In this paper, the degradation of AlGaN/GaN high-electron mobility transistors (HEMTs) is investigated by means of dc stresses performed on fresh devices either on the gate-drain junction only (i.e., with the source terminal floating) or on the gate-source junction only (i.e., with the drain terminal floating). In both cases step-stresses were carried out by increasing V DG and V SG respectively up to 35V: the saturated drain current decreased in both cases, and a significant increase in the output conductance was found for the drain-stressed devices, whereas it was negligible for the source-stressed devices. The reason for these different behaviors was believed to be the creation of acceptor traps in the AlGaN layer underneath the stressed side of the gate junction, their influence being different in the two cases because of the high horizontal electric field at the drain end of the gate during on-state operation. We carried out numerical simulations showing that the presence of a defective region with an acceptor trap concentration underneath the gate-drain or gate-source junction fits our hypothesis. [Copyright &y& Elsevier]

Abstract: With this paper we describe an extensive analysis of the reliability of InGaN-based laser diodes, emitting at 405nm. These devices have excellent characteristics for application in the next-generation optical data storage systems. The analysis aims at describing the degradation process, as well as at investigating the role of current in determining the degradation rate. The results obtained within this paper suggest that the degradation of the laser diodes is correlated to the increase in the non-radiative recombination rate, with subsequent worsening of the optical properties of the devices. Furthermore, our findings support the hypothesis that current is the main driving force for degradation, while temperature and optical power play only a limited role in determining the degradation kinetics. [Copyright &y& Elsevier]

Abstract: The effects of thermal storage on GaN–HEMT devices grown on SiC substrate have been investigated by DC and pulsed electrical measurements, breakdown measurements (by means of a Transmission Line Pulser, TLP), and optical and electron microscopy. After 3000h of thermal storage testing at 300°C, only a limited reduction of the DC drain saturation current and of the transconductance peak was observed (20% and 25% decrease, respectively). However, pulsed measurements on aged devices clearly highlight a dramatic current collapse effect that has been attributed to a creation of surface traps in the gate-to-drain and gate-to-source access region. On-state breakdown characterization carried out on aged devices did not highlight any noticeable changes with respect to the untreated devices similarly to the DC characterization. Failure analyses have demonstrated that a loss of adhesion of the passivation layer was responsible for the observed trap formation. An improved passivation deposition process was therefore developed, including a surface cleaning procedure aimed at preventing passivation detaching. The devices fabricated using this new procedure do not show any enhancement of trapping effects up to 500h of thermal stress at 300°C. [Copyright &y& Elsevier]

Short-term reliability and robustness of 110 nm AlN/GaN HEMTs has been evaluated by means of off-state, semi-on state and on-state step stress tests on devices having different gate-drain distance, L GD. While breakdown voltages and critical voltages scale almost linearly with L GD , failure mode remains almost unchanged in all tested devices, and consists in an increase of gate leakage, accompanied by a positive shift of threshold voltage. In off-state, electroluminescence images detect the presence of localized leakage paths which may act as preferential paths for electron trapping. Degradation does not depend on dissipated power and is preliminary attributed to hot-electron trapping, enhanced by electric fields. [ABSTRACT FROM AUTHOR]

In recent years the efficiency of CdTe based solar cells has been significantly improved, mainly by the increase of the short circuit current value. This has been achieved by removing the CdS window layer and by adding a CdSe x Te 1-x layer, grading the band gap of the CdTe. On the other hand, ultra-thin absorbers allow to reduce the materials impact in terms of availability, cost and environmental impact. In this paper we present and study the fabrication of an ultra-thin CdTe based device with band gap grading. Moreover, we present a novel method to generate CdSe x Te 1-x compounds: by annealing a thin part of the absorber layer in a selenium atmosphere (selenization). This technique allows to narrow the absorber band gap to 1.41 eV, to obtain the desired selenium profile and to considerably increase the external quantum efficiency at long wavelengths. We observe a large increase in the spectral response and an explicit improvement in the short circuit current for CdTe cells with an absorber thickness of 2 μm and without CdS. Current density values of 26 mA/cm2 have been achieved, which are the highest reported for thin CdTe absorbers. [Display omitted] • A new fabrication method for band grading of CdTe is presented. • Growth of CdSe x Te 1-x layer is demonstrated. • FTO/SnO 2 /CdSe x Te 1-x /CdTe cells at low temperature have been fabricated. • Spectral response is extended to a range of 300–900 nm. • The highest current density and high efficiency for thin-CdTe is performed. [ABSTRACT FROM AUTHOR]

The goal of this paper is to investigate the stability of CdTe solar cells exposed to high temperature storage. In particular, we want to investigate the behavior of cells during short-term degradation test (up to 40 h). Several cells, having different thickness of copper in the contacts and of CdTe absorber were investigated. The results, obtained through combined EQE, dark and light IV, and photovoltage decay, indicate that the Cu metal contact plays a role in the degradation of the solar cells, and provide detailed insight on the related processes. • In this paper, we analyze reliability of CdTe solar cells, comparing the performance of various types of cells. • The investigation method used is an accelerated stress, that simulates the real conditions of use of the cells. • We use various measurement methods, including EQE, dark and light current-voltage curve and PVD. • The data collected indicate a degradation, possibly caused by the diffusion of copper in active layers of the device. [ABSTRACT FROM AUTHOR]

In this work, a novel system to investigate the stability of GaN-based HEMT devices is presented and used to investigate hot-electron effects. The developed system is used to study the impact of hard switching on the dynamic on-resistance of such devices. In particular, we were able to obtain (on-wafer level) a very fast turn-ON commutation with dV DS /dt ≈ 10 V/ns (representative of realistic conditions) thanks to the low parasitics at the drain node. As a result, a realistic performance assessment of the dynamic stress of GaN power HEMTs is now available on wafer level, thus shortening the technology development loop. By intentionally tuning the capacitance at the drain node we can accurately control the amount of energy/charge released during each hard switching event, thus being able to evaluate the impact of increasing stress conditions on the devices. The results indicate that even if the hard-switching lasts few nanoseconds, it significantly impacts the dynamic R DSON : we conclude that hot-electron trapping can occur in ns-time scale. • Development of a novel setup to investigate Hard Switching in power GaN HEMT devices; • Very fast turn-on commutations (10 V/ns) at 100 kHz frequency on-wafer level; • The hard switching severity is assessed comparing the output waveforms and switching locus at different stress conditions. • The results indicate that even if the hard-switching lasts few nanoseconds, it significantly impacts the dynamic R_DSON. • We conclude that the hot electron effect is a fast trapping mechanism which can occur in ns time scale. [ABSTRACT FROM AUTHOR]

This work focuses on the positive bias temperature instability of SiC-based MOSFETs under different stress voltages and temperatures. Stress experiments demonstrate that the threshold voltage shift (∆ V th) does not follow a conventional power law for long stress time, but exhibits a saturating log- time dependence attributed to the charge trapping in the pre-existing defects at the SiC/SiO 2 interface or in the SiO 2 layer. The maximum V th shift (∆ V max), which is a function of the total trap density, increases with the stress voltage (V stress) and decreases for temperatures higher than 50 °C. The time constant of the traps (τ 0) also shows an uptrend with V stress with a maximum value of around 50 °C. Moreover, the trap energy distribution (γ) slightly increases with temperature. The recovery analysis shows that an empiric universal relaxation function well describes the data with a dispersion parameter (β) that follows the Arrhenius law. Finally, the V th recovery, after the same V stress , is enhanced with temperature and also depicts a linear behavior on the Arrhenius plot. This indicates that the charge de-trapping process is thermally activated and explains the low degradation observed at high temperatures during the stress phase. • Recoverable threshold voltage degradation under different stress conditions. • The threshold voltage shift shows a saturating log-time dependence attributed to charge trapping in the pre-existing defects. • The charge de-trapping is thermally activated and explains the low degradation at high temperatures during the stress phase. • An empiric universal relaxation function well describes the recovery data. [ABSTRACT FROM AUTHOR]

Lead halide perovskites (LHPs) have been for a decade and still remain the rising stars in current materials science research. After ten years of incessant work, researchers have reached important results in LHP photovoltaics, overcoming the 25% power conversion efficiency threshold and thus closely approaching silicon performance. On the other hand, challenges are now open for finding other useful applications for LHPs, going beyond the prevalent use in low-cost solar cell technologies. To this goal, the multiple possibilities which can be explored rely on the modification of the lattice structure of LHPs, creating libraries of different compounds with different peculiar properties. In this review, we conducted a deep and comprehensive examination of the recent literature reporting on two main strategies for making alterations at the native LHP structure. We defined them, namely, the endogenous and exogenous strategies. The first one accounts for all the compositional engineering methodologies that were applied during the last 10 years for the internal modification of the LHP lattice, while the second one refers to the realization of nanocomposites, in which LHPs and other materials are combined together. The review encompasses historic, theoretical, spectroscopic, electrical and technological contents, in order to provide a comprehensive starting point for defining a new era in LHP research. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the effect of short-term thermal stresses in CdTe thin film solar cells. The CdTe solar cells under test are manufactured with physical vapour deposition on soda lime glass in superstrate configuration. Different characterization techniques were used to study the reliability of the solar cells. In particular, external quantum efficiency (EQE) and electroluminescence (EL) measurement were applied in order to investigate the physical processes responsible for degradation. Through this analysis, we give a broad overview of degradation effects using both electrical and optical measurement and correlating the results. We show that (i) during short-term thermal stresses a soft degradation occurs, (ii) the series resistance of the cells increases and (iii) degradation is preliminarily ascribed to the generation of crystal defects due to the diffusion of copper or oxygen atoms in the CdTe solar cells. [ABSTRACT FROM AUTHOR]

In this work, GaN-on-Si power Metal-Insulator-Semiconductor High Electron Mobility Transistors (MIS-HEMTs) are irradiated through different regimes of cumulative γ -ray irradiation, namely 1, 2, 3, 4, and 5 kGy for the first sample; 1, 3, and 5 kGy for the second sample; 1, 5, and 10 kGy for the third sample; and 1, 10, and 20 kGy for the fourth sample. After each irradiation dose, drain current (I D), threshold voltage (V Th), and gate leakage current (I g) are electrically characterized in all the samples. An improvement in I D with a shift in V Th is observed in all the samples, which saturates after a higher irradiation dose. X-ray photoelectron spectroscopy (XPS) analysis confirms creation of nitrogen vacancies that act as donor and improves the I D. No significant change in I g is observed except for an increase in noise in gate leakage current. Scanning electron microscopy (SEM) shows the Al-based metallization pad degrades due to formation of small cavities. Finally, energy dispersive X-ray (EDX) analysis confirms the formation of Al native oxides due to γ -ray irradiation. [ABSTRACT FROM AUTHOR]