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The electrical properties of dinaphtho [2,3-b:2′ ,3′ -f]thieno[3,2-b]thiophene (DNTT) based organic thin film transistors (DNTT-TFTs) were investigated in detail under dark and various light illumination conditions with different channel lengths. We have exploited the experimental curves current–voltage of our TFT to extract electrical parameters such us mobility, threshold voltage, sub-threshold voltage and trapped density in dark and under illumination. By using an analytical model, we are able to reproduce very accurately the output and transfer characteristics with a joint analysis of the L = 100 μm and L = 500 μm electrical characteristics, the dependence of the contact resistance (Rc) upon the illumination conditions has been extracted. The used model gives a good agreement between the measured current–voltage characteristics of the DNTT-TFTs and those modeled in all measurement conditions (in dark and under illumination).

Organic material deposition by gravure printing is a promising pathway for the realization of large area flexible electronic devices. Nevertheless, in order to achieve high performance it is required to improve the electronic ink printability, operating on the fluid dynamic mechanisms involved during the process. In this work, this issue has been faced working on ink characteristics for a conductive and a dielectric material. The suitable ink features have been defined studying the influence on the printability of the different forces that act in the fluid during the printing process, using an experimental approach. Properly defined ink formulations have been printed, considering different shapes and dimensions of the cells on the gravure cliche to fit the ink features. The printing outcomes have been compared and analysed through the evaluation of several significant fluid dynamic parameters and the rheological characterization of the materials. Finally, exploiting the results of this study, high performance fully printed organic thin film transistors have been realized.

We present a compact model for the DC and small signal AC analysis of Organic Thin Film Transistors (OTFTs). The DC part of the model assumes that the electrical current injected in the OTFT is limited by the presence of a metal/organic semiconductor junction that, at source, acts as a reverse biased Schottky junction. By including this junction, modeled as a reverse biased gated diode at source, the DC model is able to reproduce the scaling of the electrical characteristics even for short channel devices. The small signal AC part of the model uses a transmission line approach in order to compute the impedances of the channel and parasitic regions of the device. The overlap capacitances and the presence of non-ideal metal/organic semiconductor junctions are taken in account as well and the model can be easily adapted to different device geometries. The model is particularly well suited for printed devices, often realized with large process tolerances, since it takes into consideration the presence of parasitic regions and their effect on the AC operation. The model has been validated on printed OTFTs using a pentace-derivative as organic semiconductor with a quite peculiar device layout. It has been fully implemented in Verilog-A programming language.

We studied environmental stability of top contact pentacene TFTs with active layer evaporated at different growth rates. We measured the transfer characteristics in vacuum and in air and after storing the devices in oxygen for several days. Different pentacene growth rates result in different grain size of active layer. This morphology difference influences the hysteresis of transfer characteristics induced by water absorption. On the contrary, aging effects on the transfer characteristics of pentacene O-TFTs, induced by oxygen diffusion into the active layer, are not related to structural characteristics of pentacene film.

(Polytetrafluoroethylene) PTFE-like films, deposited by using CHF3/Ar gas mixtures in a plasma reactor, have been used as encapsulation layers in pentacene thin film transistors. The PTFE-like encapsulation layers allow to carry out photolithographic processes without damaging pentacene film. However, the PTFE-like encapsulation layers are not effective in reducing hysteresis of electrical characteristics when measured in air. On the contrary, the degradation of the device electrical characteristics, induced by oxygen diffusion into pentacene film after storing the devices in air, is almost completely suppressed by the encapsulation with the PTFE-like films.

The presence of high electric fields at the drain junction in polycrystalline silicon (polysilicon) thin film transistors (TFTs), enhances several undesired effects, such as hot-carrier related instabilities and kink effect. In order to reduce the drain electric field, non-self-aligned (NSA) device architecture can be adopted. In this case, dopant activation and active layer crystallization are achieved at the same time by excimer laser annealing, resulting in a substantial lateral dopant diffusion. The gradual doping profile provides not only a reduction of the drain electric field, but also a channel length shortening. Therefore, an effective channel length (L eff ) has to be determined in such devices, in order to successfully design circuit applications. In this work, L eff and parasitic resistance (Rp) modulation effects have been investigated in both n- and p-channel NSA polysilicon TFTs. Three different parameter extraction methods, originally proposed for the crystalline MOSFETs technology, have been used and compared in order to extract L eff and R p , including: the "channel resistance" method; the "paired V g " method; the "shift and ratio" method. These methods indicate a channel length reduction up to 1 μm and a non negligible parasitic resistance effect. The reliability of the results of the three methods are discussed in terms of applicability of the underlying assumptions in the case of polysilicon TFTs and numerical simulations are used to support the analysis.

We have fabricated bottom contact pentacene TFTs on flexible polyimide substrate and silicon substrate using different passivation layers in order to reduce the electrical instability of pentacene devices, induced by water diffusion in the film, as evidenced by electrical measurements under different environments. Experimental data show that parylene passivation layer does not introduce appreciable degradation of device characteristics and allows standard lithographic process, but it is not an effective barrier for water diffusion. The encapsulation of pentacene TFTs with an additional acryl layer does not reduce the device sensitivity to the water, whereas devices encapsulated by a parylene/acryl/aluminum triple layer do not show increase of transfer characteristics hysteresis when measured in air.

The electrical instabilities in p-channel polysilicon TFTs induced by negative bias temperature stress (NBTS) and self-heating have been investigated. From NBTS experiments performed at different temperatures and gate bias, we derived an empirical relationship that provides the T and electric field dependence of the interface state generation. To explain the device instability related to self-heating we considered a spatially non uniform interface state distribution, as a non uniform transverse electric field is present during bias stress. The interface state distribution can be deduced using the empirical relationship, determined from NBTS experiments, and considering the spatial distribution of the oxide electric field, obtained from numerical simulations. Using the so determined interface state distribution it was possible to perfectly reproduce not only the transfer characteristics but also the asymmetry observed in the output characteristics, when source/drain contacts are reverted after bias stress.

In this work, we investigated self-heating related instability in polysilicon thin film transistors (poly-Si TFTs) fabricated on polyimide (PI) substrates. Indeed, when Joule heating becomes relevant, the temperature of the active layer can substantially rise, since the devices are fabricated on thermally insulating substrates. As a result, electrical instability is triggered and attributed to the generation of interface states, due to the Si–H bond breaking, and charge trapping into the gate insulator. In addition, by using 3-dimensional numerical simulations, coupling the thermodynamic and transport models, we analyzed the temperature distribution of the device under operating conditions and found that self-heating is more severe for devices fabricated on plastic substrates.

In this work we present a study of the electrical stability of self-aligned p-channel TFTs fabricated using excimer laser annealing. The electrical stability was tested performing bias stress experiments and accelerated stability tests and we found that the device characteristics were seriously degraded upon application of large negative gate bias. From extensive analysis of the phenomenon through numerical simulations, we found that the device degradation could be perfectly reproduced by positive charge injection into the gate oxide in narrow (300–400 nm) regions at the edges of the gate, near the source and drain contacts. From the present results we conclude that the observed degradation is closely related to the residual damage, induced by ion implantation, present in the gate oxide near the gate edges.

The optical diagnostic of spectroscopic ellipsometry is shown to be an effective tool to investigate the mechanism of excimer laser crystallization (ELC) of silicon thin films. A detailed spectroscopic ellipsometric investigation of the microstructures of polycrystalline Si films obtained on SiO2/Si wafers by ELC of a-Si:H and nc-Si films deposited, respectively, by SiH4 plasma enhanced chemical vapor deposition (PECVD) and SiF4-PECVD is presented. It is shown that ellipsometric spectra of the pseudodielectric function of polysilicon thin films allows to discern the three different ELC regimes of partial melting, super lateral growth and complete melting. Exploiting ellipsometry and atomic force microscopy, it is shown that ELC of nc-Si has very low energy density threshold of 95 mJ/cm2 for complete melting, and that re-crystallization to large grains of ∼ 2 μm can be achieved by multi-shot irradiation at an energy density as low as 260 mJ/cm2 when using nc-Si when compared to 340 mJ/cm2 for the ELC of a-Si films.

We present, for the first time, the application of the asymmetric fingered thin film transistor (AF-TFT) architecture to self-aligned p-channel TFTs for kink effect suppression. In AF-TFT the transistor channel region is split into two zones with different lengths ( L 1 > L 2 ) separated by a floating p + region. A fourth electrode, contacting the floating p + region, allowed us to measure the individual electrical characteristics of the two sub-TFTs. Output characteristics show that substantial kink effect reduction can be achieved when the sub-TFT placed at the drain end of the device has an L 2 ≪ L 1 . The electrical characteristics were analysed by using numerical simulations in the framework of the two-transistor model and we show that kink effect suppression arises from the operation in saturation regime of the source sub-TFT. The electrical characteristics of the fabricated p-channel AF-TFTs show a complete kink effect suppression, making these devices very attractive for current drivers in organic light emitting displays.

A revolutionary approach to the technology design is required for the integration of the laser annealing process in nano-electronic device fabrication. The list of the integration issues includes: the patterning effect, the extreme non-equilibrium kinetics of dopant and defects, the material modification due to the melting-regrowth phenomena (in the melting regime) and the residual damage problem. The intense research effort required surely benefits from an adequate development of dedicated technology computer aided design tools. We present the computational apparatus needed for the simulation of the laser annealing process in Si-based devices. The tools aim at the simulation at a different resolution (from the atomic to the continuum level) of the phenomena occurring inside the specimen during the irradiation. The usage impact of such simulation tools on the process integration is conclusively crucial for a reliable device design and the final optimisation of fabricated MOS transistors.

In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200 degrees C, 250 degrees C, 350 degrees C and 450 degrees C) and annealing times. We found that optimal conditions were obtained at 350 degrees C, with transfer characteristics showing a subthreshold slope of 0.5 V/dec, field effect mobility > 100 cm(2)/Vs and threshold voltage around -3.5 V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350 degrees C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for V,(stress) - V-t = -4 V while bias-stress at V-g = V-t and vertical bar V-g(stress)vertical bar >> vertical bar V-ds(stress)vertical bar did not produce appreciable changes in both transfer and output characteristics.

Integration of excimer laser annealing (ELA) process for power MOSFET devices is currently studied and evaluated within the frame of the IST project FLASH (Fundamentals and applications of laser processing for highly innovative MOS technology), funded by the European Commission. Final goal of the project is to show that ELA can be industrialized in the context of semiconductor device fabrication. In this work, the recent advancements of the FLASH project are described, including the formation of n + /p source junctions in both one and two dimensions. The experimental results are analysed by using a two-dimensional simulation program, specifically developed by the consortium. The simulation tool allowed a deeper insight of the ELA process and has been successfully used to optimise the process parameters. Finally, data on electrical integrity of the test devices are also presented, showing a yield for optimum ELA conditions up to 84%.

The influence of channel doping on the threshold voltage of poly-Si thin film transistors (TFTs) has been investigated using both boron and phosphorus implants. For each dopant type, asymmetric TFT behaviour was seen between enhancement and depletion mode TFTs, with the enhancement mode TFTs always showing a greater shift in threshold voltage for a given dose. From a detailed analysis of the boron-doped samples, using a two-dimensional device simulator, it was demonstrated that the results could be best explained in terms of a non-symmetric density of states, in which the deep trapping state density in the lower half of the band-gap increased with increasing boron concentration. This is the first reported observation in poly-Si of shallow level dopants also introducing deep levels in the majority carrier half band-gap.

In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition. These techniques are suitable for a very low temperature process for TFT fabrication. The output characteristics show a current increase at high drain voltage, (“kink” effect) rather moderate, if compared to self aligned polysilicon TFTs, probably due to the gradual doping profile induced by laser doping process. After bias stress at low gate voltage and high drain voltage condition a strong reduction of kink current has been observed in the output characteristics at high drain voltage, whereas minor changes has been observed in the transfer characteristics. This behaviour is similar to what observed in n-channel Gate Overlapped Thin Film Transistors. In the high gate voltage and high drain voltage bias-stress condition we observed only a rigid shift of the transfer characteristics probably related to charge injection in the gate oxide, while subthreshold slope remains constant.

Short channel effects have been investigated in n-channel polysilicon thin film transistors. Transconductance degradation has been observed when reducing the channel length L and this effect has been explained with the presence of a parasitic resistance related to residual implant damage. Threshold voltage slighlty decreases for channel length around L=1 μm and simulations confirm that the roll-off of the threshold voltage is expected for L

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O2, SiH4 and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (Ew). Higher Ew at room deposition temperature (RT) shows low defects densities ( 10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N2. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 1011 cm−2 eV−1. These results show that a complete low-temperatures process can be achieved for the integration of SiO2 as gate insulator in polysilicon TFTs on plastic substrates.

Excimer laser annealing (ELA) of As-, B- and BF2-implanted Si has been studied by secondary ion mass spectrometry (SIMS), spreading resistance probe (SRP) and transmission electron microscopy (TEM). The implantations have been performed in the energy range from I to 30 keV with doses of 10(15)-10(16) cm(-2). ELA has been carried out with the energy densities in the range of 600-1200 mJ/cm(2) and the number of laser pulses from 1 to 10. It is shown that ELA results in a more uniform dopant distribution over the doped region with a more abrupt profile edge as compared to those after rapid thermal annealing (RTA). Besides, in contrast to RTA, ELA demonstrates a highly confined annealing effect, where the distribution of dopants below the melting region is not affected. SRP measurements demonstrate almost complete activation of the implanted dopants after ELA, and TEM does not reveal extended defects in the ELA-treated samples. The depth of the doped layers, abruptness of the profiles and the total doping dose as a function of ELA energy density and number of laser pulses are investigated. Computer simulations of ELA show a good agreement with the experimental data.

We report on the correlation between structural and electrical properties of pentacene thin film transistors fabricated by the novel supersonic molecular beam epitaxy (SuMBE) technique. We exploited the ability of SuMBE that, through the control on the molecular precursors in the beam, allows improving the quality in terms of structure and morphology of the semi-conducting thin films compared to the more standard OMBE growth. Different growth conditions were explored to find the better range of beam parameters improving the performance of the TFT device whereas the quality of the films grown was studied by atomic force microscopy. We show that the initial kinetic energy of the pentacene molecule strongly affects both the morphology of the films and the electrical properties of the devices that result to be strongly correlated. With our FET devices prepared, on SiO 2 /Si and top Au contact, we achieved the very promising field effect mobility larger than 0.5 cm 2 V −1 s −1 for films grown at room temperature at a pentacene kinetic energy of about 5.5 eV that are characterized by large crystalline grains (>2 μm).

We propose the implementation of graphene-based field effect transistor (FET) as radiation sensor. In the proposed detector, graphene obtained via chemical vapor deposition is integrated into a Si-based field effect device as the gate readout electrode, able to sense any change in the field distribution induced by ionization in the underneath absorber, because of the strong variation in the graphene conductivity close to the charge neutrality point. Different 2-dimensional layered materials can be envisaged in this kind of device.

The analysis of the grain size (GS) vs. energy density of silicon films irradiated with long pulse (LP) (150–200 ns) excimer laser has revealed that the maximum GS achievable is limited to 250–350 nm. In general, maximum GS occurs when the so-called super lateral growth (SLG) mechanism is triggered (almost complete melting) and in short-pulse (30 ns) irradiated films the maximum GS can be well above 1 μm. In order to clarify this discrepancy between the SLG regimes observed with short and LP irradiations, we performed an experiment with a LP (170 ns) excimer laser (HERCULES), having opportunely profiled the energy density to a ‘ramp’ distribution. In this way it was possible to have a continuous energy distribution and by analysing the structural (SEM) and topographical (AFM) properties it was possible to produce an accurate picture of their dependence upon the laser energy density. We were able to identify the SLG regime, with GS up to 1.5 μm and energy window Δ E / E =0.002, pointing out the difficulties in observing SLG in LP irradiations.

Structural properties of thin polycrystalline silicon films, crystallized by single shot excimer laser annealing at different laser energy densities, have been investigated. Formation of disk structures has been observed in a wide range of energy densities, from complete melting down to 180 mJ/cm 2 . These structures have been correlated to the lateral growth of grains starting from the small grains present in the central regions of the disks. We propose a new crystallization scenario for energy densities below the complete melting. In this framework, the recalescence effect plays an important role while the super lateral growth-regime is no longer a particular crystallization condition but simply represents the upper energy density limit of partial melt crystallization regime.

Grain size control in excimer laser crystallization has stimulated a growing activity aiming to locate large silicon grains in the thin-film transistor (TFT) channel. We present a new technique that can be applied to control the lateral growth (LG), by using thickness spatial modulation, and that can be used to the fabrication of high performance polysilicon TFTs. In particular LG can be triggered when thinner regions are completely melted and thicker regions are partially melted. Thicker regions are formed by a two layer structure of doped and undoped material while thinner regions are obtained by removing the doped layer. In this way the thicker regions can be used as source–drain regions of the device while the thinner regions, where large grains are formed, can be used as channel regions. In order to control the LG, different doped and undoped layer thickness have been investigated. The structures have been irradiated at different laser energy densities and we observed that the thicker regions became highly conductive (∼70 Ω/□), due to doping activation and redistribution induced by the melt/regrowth process, while triggering of the LG in the thinner region has been observed within an opportune energy density window. As the LG extension is limited at approximately 1 μm, active channel region ⩽2 μm could be formed. The proposed process is very attractive for polysilicon TFTs as LG-control and doping activation can be simultaneously achieved.

Hot-carrier induced degradation is a main issue in the electrical stability of polysilicon TFTs and drain field relief architectures have been introduced, such as lightly doped drain (LDD) and gate overlapped LDD (GOLDD), to improve the stability. Bias-stress experiments were performed on both LDD and GOLDD structures, biasing the devices above pinch-off at constant V g and different V ds . While the LDD structure presented considerable hot-carrier induced degradation, GOLDD devices were characterised by a very high electrical stability. To explain such a difference in electrical stability, we first analysed the spatial distributions of the electric fields, which are lower in GOLDD structures. In addition, we developed a new model to describe the hot-carrier induced degradation, based on the correlation between hot carrier injection currents and interface state generation. Indeed, hot carrier injection is known to produce interface states and oxide trapped charge, and, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current. The proposed model nicely reproduces the degraded characteristics, thus providing indications on the spatial distribution of the generated interface states.

A novel fabrication process for low-temperature (

Low-frequency noise has been investigated in self-aligned (SA) and gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors (TFTs). We found that, at low Vds, both device structures are characterised by 1/f noise, originating from carrier number fluctuations. However, when the SA devices were operated in the kink regime, an excess noise was observed, in contrast to GOLDD TFTs. This has been explained by attributing the excess noise to supplemental oxide charge fluctuations induced by hot-carrier injection into the gate oxide. By using two-dimensional numerical simulations, we show that the hot-electron emission current in SA polysilicon TFTs is much higher than in the GOLDD structure.

The introduction of excimer laser crystallization (ELC) techniques in the fabrication of polysilicon thin-film transistors (TFTs) has produced a tremendous improvement in the device characteristics. When the Super Lateral Growth (SLG) mechanism is triggered, large (>1 μm) grains are formed and this crystallization regime appears very attractive from the device fabrication point of view. In fact, using SLG-polysilicon active layers high performance (electron field-effect mobility>300 cm 2 /V s) TFTs can be obtained and a detailed analysis of the electrical characteristics of such devices is presented. However, the SLG mechanism has a very narrow energy density window and, consequently, highly uniform beam profiles and pulse-to-pulse stability better than 2% are required. This implies that standard ELC-process is technologically quite critical and several approaches have been proposed to improve the process uniformity. Among these we will discuss three main techniques: (1) the use of opportunely (semi-gaussian) profiled beams; (2) the combined use of Solid Phase Crystallization (SPC) and ELC techniques; (3) control of the lateral growth. In particular, we present a novel technique to control the lateral growth, based on a two-pass ELC-process. The proposed technique can be rather attractive for polysilicon TFT fabrication, allowing a precise grain location control (through the mask geometry) and being characterized by a few (3–5) laser shots process and wide energy density windows.

Hot-carrier effects on both the electrical characteristics and the noise performance in polycrystalline silicon thin film transistors are analysed. The devices were fabricated by using a combined solid phase crystallization (SPC) and excimer laser annealing (ELA) process, combining the beneficial aspects of the two techniques. Hot-carrier degradation results in the formation of both interface states, which have been evaluated through the analysis of the sheet conductance and of oxide traps near the insulator/semiconductor interface, as evidenced by the 1/f noise measurements. Oxide traps are calculated evaluating the flat band voltage spectral density associated with interface charge fluctuations in the damaged part of the interface. A strong correlation between interface state and oxide trap densities has been found, suggesting a common origin for the generation mechanism of the two types of defects.

Polysilicon thin-film transistors (TFTs) are of great interest for their circuit application in the large area microelectronics. A successful circuit design requires an accurate prediction of the circuit performances, which in turn needs a proper modeling of the electrical device characteristics. In this present work the specific aspects of the anomalous current increase in the output characteristics, often called the “kink” effect, are analysed. A new procedure to determine the excess current is presented and we analysed the excess current for different gate voltages, temperatures and device geometries. We show that, from the parameters that can be extracted by analysing a reduced set of experimental data, the excess current can be easily predicted for any bias and temperature condition and also for devices with different geometries. These results can be used to further up-grade the modeling of the electrical characteristics of polysilicon TFTs in circuit simulators.

Hydrogenated amorphous silicon thin-film transistors have been fabricated by using electron-beam lithography to define channel length down to 0.2 μm. In this way it has been possible to evidence, for the first time, short-channel effects on these devices. In this work two short-channel effects occurring in 0.2 μm devices are discussed: degradation of the off-current as the source-drain voltage is increased and avalanche increase of the drain current for high source-drain voltage.

Negative bias stress experiments on a-Si:H/a-SiO 2 Thin Film Transistors show that the instability is predominantly related to charge injection in the gate insulator. We propose that charge injection is occurring in a defected region of the gate insulator adjacent to a-Si:H, caused by the effect of activated hydrogen on a-SiO 2 surface during deposition. To investigate the hydrogen influence, we have studied low-energy (100 eV) hydrogen-ion and Ar-ion bombardment effects on a-SiO 2 using synchrotron radiation photoemission spectroscopies. Comparing the two kind of treatments, we show that hydrogen treatment produces predominantly Si-H defects, which are observed to induce gap states in a-SiO 2 .

In this work the application of a-Si:H thin film transistor (TFT) technology in the field of chemical sensors is presented. In particular, two different types of devices have been fabricated: a) Pd-gate hydrogen sensors; b) K+-ion sensitive FET (ISFET). The obtained results show that a-Si:H TFT can be successfully used as gassensitive and ion-sensitive sensors and can represent a promising technology in this area.

In the present paper are shown the characteristics of devices succesfully employing low temperature plasma deposited a-SiO2 as gate insulator with thickness of 40 and 18 nm. They show a very sharp field effect conductivity onset and an on/off current ratio of about 8 orders of magnitude. Due to the very low insulator thickness it is possible to operate these devices in the range between -2 and 5V with on current of the order of 10−5A.

The phenomenon of space-charge density variation induced by illumination in metal/insulator/amorphous semiconductors structures is experimentally and theoretically investigated.

Electronic quality a-SiO 2 have been deposited by PECVD showing high breakdown fields and low trapping probability down to thickness of 16 nm. The transport properties of this material have been analyzed. The Fowler-Nordheim mechanism has been ruled out due a marked temperature sensitivity of the current around room temperature. On the other hand thermally activated transport, such as Schottky or Frenkel-Poole mechanisms, fit reasonably well the experimental data. However a better fit of the overall data seems to support the Schottky as the main transport mechanism in our materials.

Field effect conductance and mobility have been calculated in superlattice thin film transistors by using a classical model. The results show that, for low interface state densities, both computed quantities increase as the number of period is increased, keeping constant the total semiconductor thickness. This model fits well the data already reported for such devices.