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This paper proposes an adaptive model of modular multilevel converter (MMC) for electromagnetic transient (EMT) simulations. The model is applicable to MMCs with arbitrary numbers of half-bridge and full-bridge submodules. The proposed design includes average value model, arm equivalent model, and detailed equivalent model. It allows smoothly transitioning from one model to another during time-domain simulations depending on the desired accuracy and execution time constraints. Modifications required in conventional MMC models to achieve smooth transitions are presented in the paper. Time-domain initialization methods are developed for each constituting model, including initialization of the appropriate control system blocks. Validity and effectiveness of the proposed adaptive model is demonstrated using EMT simulations of 401-level MMC-HVDC system. [ABSTRACT FROM AUTHOR]

The high di/dt before zero-crossings easily leads to delayed or failed operations for the active current injection mechanical DC circuit breaker, especially for small direct current interruptions. The pre-charging process also makes this type of circuit breaker hard to realize repeat operations economically in the high voltage DC system. This paper proposes a novel DC circuit breaker and its design method that deeply coordinating a superconducting fault current limiter with the active current injection DC circuit breaker. This method significantly reduces di/dt before current zero-crossings and enables repeat operations economically. Besides limiting fault currents, the superconducting fault current limiter also charges the resonance capacitor flexibly in the circuit breaker, realizing the injected reverse current keep a constant proportion to the arbitrary fault current. Validations of the flexible capacitor charge and repeat operations are made by simulation and low voltage experiments. The charging times are within 2.5 ms and the reverse current keeps 1.2 to 1.7 times over the fault current under arbitrary conditions. Di/dt at current zero is reduced by 80% under 30% of rated interruption capacity. Flexible capacitor charge experiments are consistent with the simulation design. The superconducting tapes can recover within 300 ms to support repeat operations. [ABSTRACT FROM AUTHOR]

Hybrid dc circuit breakers (HCBs) are recognized as suitable devices for protecting high-voltage direct-current (HVDC) systems, along with other dc circuit breakers (DCCB). However, compared to mechanical circuit breakers, HCBs exhibit higher conduction losses. Such losses are inevitable under no-fault conditions as current may flow through some of the semiconductor switches. An integrated circuit breaker (ICB) minimizing these losses is presented in this paper, and this is achieved by replacing semiconductor switches by mechanical components in the current path. For completeness, the topology design, operating sequence and a mathematical analysis for component sizing of the device are provided. In addition, an estimation of the conduction losses is quantified. It is estimated that the power losses of an ICB are 2 to 30% of an HCB only. The ICB has been implemented in PSCAD/EMTDC to demonstrate its effectiveness for isolating dc faults, with simulations conducted on a three-terminal HVDC grid. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

Reduced switch active phase converters (APC) are cost-effective solutions for running three-phase loads from single-phase grids. This paper proposes a novel auxiliary-capacitor-based APC (AC-APC) for this application. The combination of the topological location of the auxiliary capacitor and the control of the AC-APC reduces current stress on the semiconductor devices. In this paper, a selection criterion for the optimal auxiliary capacitor value is formulated to reduce the device currents in such a way that the overall efficiency is enhanced. This paper presents a comparative analysis of converter volt-ampere (VA) rating and device power loss for conventional H-bridge active front-end and inverter-based topology, APC, and AC-APC. To evaluate the efficacy of the proposed AC-APC, an experimental study is conducted on the APC and the AC-APC feeding a 3-hp three-phase induction motor. At a full load of $\text{2.5}\,\text{kW}$ and $\text{0.8 } \text{power factor}$ , the measured maximum efficiency of the AC-APC is $2\%$ higher than that of the APC. Analytical evaluation of converter currents and device power loss are in close agreement with experimental observations. [ABSTRACT FROM AUTHOR]

Power management integrated circuits (PMICs) with on-chip compensation are widely used to power multiple loads in mobile devices with increased power density. However, there are two issues for on-chip compensated PMICs. First, on-chip compensation reconfigurability is required to obtain the appropriate response in various passive components. Second, a converter for a processor requires adaptive voltage positioning (AVP) to reduce the output capacitor size. In this paper, a novel reconfigurable on-chip compensated current-mode buck converter with AVP is proposed to solve the aforementioned issues without requiring high-speed and high-resolution analog-to-digital converter (ADC). A reconfigurable accurate load line control scheme and on-chip compensation are proposed to achieve an accurate load line and AVP in various load lines and passive components. The control scheme, small-signal model, and circuit implementation are illustrated in this paper. The proposed buck converter was implemented into an integrated circuit to verify the analysis. [ABSTRACT FROM AUTHOR]

An important aspect of ensuring the power integrity of a power distribution network (PDN) design is to determine the layout, value, package size, and number of decoupling capacitors. To solve the limitation of the vertical connection of the surface-mounting-type capacitor to the power net area fill, a new concept of a capacitor denoted the Z-directed component (ZDC) is proposed in this paper. There are many applications possible with the ZDC with the first implementation as a decoupling capacitor. The ZDC capacitors can be integrated within the printed circuit board (PCB) substrate directly below the package ball and eliminate the integrated circuit (IC) to decoupling capacitor horizontal distance across the power net area fill. Furthermore, the inductance associated with the vertical current paths on the vias from the IC package to the horizontal power net area fill and similarly for the surface-mounted technology decoupling capacitors is eliminated. Since only the inductance of the ZDC capacitor itself remains, there is the possibility of using far fewer capacitors to achieve a high-frequency target impedance specification. The ZDC is a promising technology that gives the PCB designer the opportunity to integrate low equivalent series inductance decoupling capacitors much closer to the noise source than traditional surface-mount capacitors. In addition, in this paper, a high-order model is introduced for the ZDC capacitor to better understand the high-frequency characteristics of the component and is verified with measurements. [ABSTRACT FROM AUTHOR]

The  power distribution network (PDN) of a high-speed printed circuit board requires a high-performance power supply. The total equivalent inductance above the top ground plane is an important part of PDN design and is regarded as Labove. In this paper, an inductance library for different structures of capacitor connections and capacitor sizes has been built, which is essential for PDN design. computer simulation technology (CST) and partial element equivalent circuit method are applied to obtain the shorted pattern design curves at various design data. The shorted pattern design curve means the total equivalent inductance varies with the distance between pad and ground plane. In addition, an approximate shorted model is established for a decoupling capacitor-mounted model, which will be convenient for us to get the inductance of Labove. In this paper, the design curve provides an intuitive guideline in designing PDN and facilitates the industry to choose what they want with consideration of the inductance, space, via numbers, etc. [ABSTRACT FROM AUTHOR]

Double wye shunt capacitor banks (SCB) are commonly used for reactive power support in high voltage transmission systems. Neutral current unbalance method is often used for protecting double wye SCBs against internal faults. One of the limitations of existing neutral current based unbalance methods is that they fail to detect simultaneous faults (same fault starting time or faults happening between two consecutive protection passes). This paper proposes a novel method for internal fault location in ungrounded double wye fused/fuseless SCBs. The proposed method uses compensated negative sequence and neutral currents to locate the internal faults. The advantage of the proposed method is that it can locate simultaneous faults happening in any of the two legs of SCB. The proposed method can also calculate the number of faulty elements. The performance of the proposed algorithm has been validated using both hardware experiments and software simulations. A laboratory scale prototype of ungrounded double wye SCB has been developed to test the performance of the proposed method. Software simulations have been done using PSCAD software. Results show that the proposed algorithm can locate both single and simultaneous faults even during system voltage unbalances. The proposed algorithm performs satisfactorily during load switching scenarios. [ABSTRACT FROM AUTHOR]

The protection and current flow regulation of high-voltage direct-current (HVDC) grids requires the deployment of additional semiconductor-based equipment including dc circuit breakers (DCCBs) and current flow controllers (CFCs). However, the inclusion of multiple devices could significantly increase the total cost of an HVDC system. To potentially reduce costs, this paper presents an innovative multi-function integrated DCCB (MF-ICB). The proposed device exhibits a reduced number of semiconductor switches and can fully block dc faults at different locations while regulating dc currents. The configuration of the integrated solution and its operating principle are assessed, with its performance being examined in PSCAD/EMTDC using a three-terminal HVDC grid. Simulation results demonstrate the capability and effectiveness of the MF-ICB to regulate grid current and isolate dc faults. [ABSTRACT FROM AUTHOR]

This paper introduces a new nonlinear voltage-mode controller for a PWM dc-dc buck converter operating in continuous conduction mode. The sliding-mode control technique is used to derive a simplified equivalent control law based on the averaged dc-dc buck converter dynamics. As opposed to the reported design approaches, the proposed control scheme only requires the output voltage in the feedback loop without the need to the capacitor current. Thus, the analogue implementation cost is reduced and the drawback of adding a capacitor current sensor to the power converter is eliminated. The control equation is realized in a simple analogue circuit using few op-amps and resistors, which is suitable for industrial applications. The system modeling and control design procedure along with the derivation of the existence and stability conditions are presented. The control system performance is analyzed using MATLAB and SaberRD simulations. Furthermore, a simple analogue prototype of the simplified nonlinear voltage-mode controlled dc-dc buck converter is developed on a PCB. The simulation and experimental results show that the controller maintains a constant switching frequency, exhibits fast transient response, and provides good tracking performance under large disturbances. [ABSTRACT FROM AUTHOR]

This paper proposes a DC/DC current flow controller (CFC) for meshed high voltage direct current (HVDC) grids. The CFC has the advantage of a simplified structure that allows us to use the minimum number of switches when unidirectional current flows through the DC lines are expected. An extended CFC topology that is able to operate with all possible current flows is also presented. Then, the operating principle of the CFC is discussed and its structure is compared with a dual H-bridge analyzing advantages and disadvantages. This paper also details the applied modulation strategy and the control methodology. Finally, a five-terminal meshed HVDC grid is used to validate the CFC by means of simulations. [ABSTRACT FROM PUBLISHER]

This paper presents circuit design methodologies to enhance the electromagnetic immunity of an output-capacitor-free low-dropout (LDO) regulator. To evaluate the noise performance of an LDO regulator in the small-signal domain, power-supply rejection (PSR) is used. We optimize a bandgap reference circuit for optimum dc PSR, and propose a capacitor cancelation technique circuit for bandwidth compensation, and a low-noise biasing circuit for immunity enhancement in the bias circuit. For large-signal, transient performance enhancement, we suggest using a unity-gain amplifier to minimize the voltage difference of the differential inputs of the error amplifier, and an auxiliary N-channel metal oxide semiconductor (NMOS) pass transistor was used to maintain a stable gate voltage in the pass transistor. The effectiveness of the design methodologies proposed in this paper is verified using circuit simulations using an LDO regulator designed by 0.18-$\mu$m CMOS process. When sine and pulse signals are applied to the input, the worst dc offset variations were enhanced from 36% to 16% and from 31.7% to 9.7%, respectively, as compared with those of the conventional LDO. We evaluated the noise performance versus the conducted electromagnetic interference generated by the dc–dc converter; the noise reduction level was significantly improved. [ABSTRACT FROM PUBLISHER]

This paper proposes a wide-range zero-voltage-switching (ZVS) active-clamped current-fed push–pull converter for fuel cell application. The presented converter achieves ZVS for all of the primary switches and ZCS for secondary diodes from rated load to 10% full load over the wide input voltage variation, improving the overall efficiency. The ZVS of switches is realized by the energy stored in the transformer leakage inductance aided by the secondary parallel inductor. An additional active clamping circuit suppresses the voltage spike as well as assists in realizing ZVS of switches. Low-voltage-rated switches with low on-state resistance can be used. Moreover, the voltage-doubler rectifier is adopted to release the reverse-recovery problem of rectifier diodes and reduce turns ratio of the high-frequency transformer. Detailed steady-state operation, analysis, design, control, comparative study, and experimental results are discussed in depth in this paper. Finally, a 200-W prototype has been built in the laboratory to verify the effectiveness of the proposed converter. [ABSTRACT FROM PUBLISHER]

This paper describes a silicon carbide pulse width modulation (PWM) signal generator in the 1.2 μm HiTSiC CMOS process developed by Raytheon Systems Ltd. The design features a 6-b binary input, which allows for setting a system's duty cycle. The results presented in this paper utilize a field programmable gate array board in the test setup to dynamically set the duty cycle by controlling each bit. A control current is also available to give the user added flexibility for tuning the duty cycle. Experimental results show the duty cycle range of the PWM generator to be between 4.7% and 95.2% at 400 °C. Sustained operation of the circuit is demonstrated over a period of 50 h at 300 °C. Finally, the PWM generator is evaluated in the operation of a boost converter. [ABSTRACT FROM PUBLISHER]

Conventional single-phase power-factor-correction (PFC) rectifiers with active power decoupling capability typically require more than three active switches in their circuits. By exploring the concept of power-buffer cell, a new single-stage PFC rectifier with two active switches, one inductor and one small power-buffering capacitor is reported in this paper. The proposed converter can achieve high-power factor, wide output voltage range, and power decoupling function without using electrolytic capacitor. Additionally, an automatic power decoupling control scheme that is simple and easy to implement is proposed in this paper. The operating principle, control method, and design considerations of the proposed rectifier are also provided. A 100-W prototype with ac input voltage of 110 Vrms and a regulated dc output voltage ranging from 30 to 100 V has been successfully designed and practically tested. The experimental results show that with only a 15 μF power-buffering film capacitor, the proposed converter can achieve an input power factor of over 0.98, peak efficiency of 93.9%, and output voltage ripple of less than 3%, at 100-W output power. [ABSTRACT FROM PUBLISHER]

The capacitor energizing transient as a kind of typical disturbance is used in the studies of power quality, condition monitoring, and other fields, and all studies heavily rely on transient characteristics. However, most characteristics are established based on the three-phase capacitor synchronous energizing (SE), and the effect of asynchronous energizing (AE) is neglected, which may affect the relevant studies. In this paper, the main characterizations of the capacitor AE transient, such as the oscillation frequency, time constant, and transient magnitude are analyzed considering the operation modes of the system and capacitor neutral points. The effect of the three-phase circuit asymmetry on the characterizations is investigated. The downstream voltage magnification phenomena in not only positive-sequence circuit but also zero-sequence circuit caused by the capacitor AE are also revealed. The theoretical analysis, computer simulation and lab experiment results have verified the effectiveness of the characteristics. [ABSTRACT FROM AUTHOR]

In this paper, we propose a 3-level double conversion uninterruptible power supply with a new cooperative and dynamically weighted model predictive control technique. A 3-level dc–dc converter is used to improve the dc bus balance and the overall response of the uninterruptible power supply (UPS). A new cooperative model predictive control principle is proposed to enhance the response of multiconverter systems. New controllers are proposed for all converters of the UPS, based on the dynamically weighted model predictive control technique and using the presented cooperative principle. A new power management technique is also proposed for the UPS. The proposed 3-level UPS system presents improved dynamic response and steady-state performance in distinct operating points, when compared to the conventional system. Experimental results demonstrate the advantages of each proposed novelty. [ABSTRACT FROM AUTHOR]

In real applications, it is usually desirable to have a regulated dc output voltage from a wireless power transfer (WPT) system. This voltage regulation is especially necessary because of possible variation in coupling coil relative position and thus a changing mutual inductance. For WPT systems working at megahertz (MHz), Class E rectifiers are known to be advantageous, thanks to their simple configuration and soft-switching operation. In this paper, we propose a new Class-E-based active rectifier. This rectifier is capable to simultaneously perform high-efficiency rectification and output voltage regulation, but without the need to have an additional regulating circuit. Analytical derivations and analysis are provided to explain the operation principle in detail. Guidance is also developed for a balanced design of parameters, which compromises among different criteria. Final experiments validate the analytical analysis and dc output voltage regulation via the active rectifier. With the duty cycle control of the rectifier, a constant output voltage (10 V) can be maintained under a varying mutual inductance coefficient and with more than 92% rectifying efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a simplified hierarchical energy balance control method for a modular multilevel matrix converter (M3C) operating as a frequency changer (50–50/3 Hz) for low-frequency ac transmission system. The proposed method employs an independent energy balance control for each subconverter of the M3C with only injecting the output frequency circulating current, aiming at balancing the energy among the three arms of the subconverter. Then, the modulation technique is redesigned to balance the energy among n submodules within each arm. The proposed method simplifies the computational complexity of the M3C by considering the subconverter independently, enabling an easy and efficient way to control the M3C. The feasibility of the proposed method is evaluated with normal and dynamic operation, which includes step changes in the output frequency and voltage. The performance and effectiveness of the proposed control strategy is demonstrated by extensive simulation studies and experimentally validated using a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]

Matrix-based high-frequency linked (MBHFL) bidirectional dc–ac converters are getting much interest in grid-tied applications due to their high efficiency and the compacted footprint. This paper proposes a new PWM switching technique of the MBHFL dc–ac converters based on phase shift angle considering compensation of the LC filter current at the grid side in order to realize accurate unity power factor and to reduce the total harmonic distortion (THD) of the grid current waveform. The proposed technique estimates the phase shift angle error between the grid voltage and current waveforms due to the capacitor injected current that reduces the power factor at the grid side. It considers two operational modes based on the patterns of three-phase grid voltage and current waveforms. Therefore, it provides the matrix converter switches with different duties according to the pattern of the detected grid voltage and the reference grid current to compensate the phase shift angle error. Also, grid LC filter design and the system controllable limit of the matrix converter output voltage are presented. In addition, the PWM switching technique of the H-bridge circuit is modified to realize safe operation of the converter during step changes at the grid voltage. The effectiveness of the proposed PWM switching technique and its related mathematical model have been investigated experimentally using laboratory prototype based 200 V, 2 kW. [ABSTRACT FROM AUTHOR]

Cascaded H-bridge (CHB) is a promising topology for medium-voltage high-power applications. CHB consists of low-power H-bridge modules in each phase, and these modules are connected in a cascade manner to achieve multilevel operation. However, CHB requires a phase-shifting transformer with multiple secondary windings to generate an isolated dc source for each module, and this requirement increases the overall system cost. In this paper, a series connection of low-power modules is employed to realize a new power converter called a series-connected multilevel converter. Each phase of the proposed topology requires a single isolated dc source. Hence, the required number of secondary windings is considerably reduced. This approach also minimizes the complexity and cost of the overall system. The operation of the proposed topology is presented by using three-level neutral point clamped modules in each phase. Model predictive control (MPC) is employed to control the dc-bus capacitor voltage and output currents of the proposed topology. A discrete-time mathematical model of the proposed topology is also developed to predict the future behavior of control variables. The performance of the proposed topology with MPC is verified through MATLAB simulations and a scaled-down laboratory prototype. [ABSTRACT FROM AUTHOR]

In this paper, a nonisolated two-channel light-emitting diode (LED) driver with automatic current balance and zero-voltage switching (ZVS) is presented. In this LED driver, a dc-blocking capacitor is connected with one side of the coupled inductor. Therefore, based on the ampere–second balance, a current source is generated with the average value of the positive current identical to the absolute average value of the negative current. Accordingly, the LED currents can be balanced naturally without extra active components or current sharing transformer. Consequently, the circuit components can keep at a low count. In addition, the proposed LED driver can achieve ZVS turn-on. Thus, the switching loss can be decreased. Above all, the proposed two-channel LED driver can be extended to a multichannel LED driver. In this paper, detailed theoretical analyses and experimental results are provided to verify the feasibility and effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

Model-predictive current control (MPCC) is a promising candidate for modular multilevel converter (MMC) control due to its advantages of direct modeling and fast dynamic response. The conventional MPCC, which obtains the optimal control input by evaluating a cost function for all the possible switching states, may make the MPCC impractical due to the exponentially increasing computation burden with the increasing number of submodules (SMs). On the other hand, the MPCC experiences high load current and circulating current tracking errors, since only one switching state is selected and applied during one control period. To address these issues, this paper proposes an MPCC with phase-shifted pulsewidth modulation (PS-PWM) for improving the steady-state control performance. The arm voltages are considered as a whole to implement the proposed MPCC. The optimal duty cycle is obtained based on the load and circulating current tracking error minimization and applied using the PS-PWM. As a result, the computation burden is unrelated to the number of SMs by avoiding the exhaustive evaluation process for all the possible switching states. A better steady-state performance with smaller tracking errors is achieved with the similar switching frequency, and the tedious tuning process of the weighting factor is eliminated. Experimental results are presented to demonstrate the effectiveness of the proposed MPCC. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dynamic ramp valley control in a current-mode adaptive on-time controller for the on-chip buck converter. It improves the system stability and reduces the output voltage under the load-dump. The proposed novel dynamic ramp valley control uses a sample and hold circuit, a comparator, and a ramp valley control to avoid the generation of an erroneous pulse signal while regulating the output voltage under the load-dump. Finally, a buck converter with 12 to 19 V input voltage range and 1.05 V output voltage with the novel dynamic ramp valley control is implemented in an integrated circuit. Based on the hardware experimental results, the output voltage under the load-dump with and without the proposed dynamic ramp valley control is 156 and 224 mV, respectively. Thus, the output voltage with the proposed dynamic ramp valley control is lower by 68 mV than that without the proposed dynamic ramp valley control, avoiding the potential damage of the output load, moreover, this performance has been verified with the SIMPLIS simulation and hardware experimental results. [ABSTRACT FROM AUTHOR]

This paper presents an area and power efficient interpolation scheme using variable current control (VCC) for 10-bit data drivers in mobile active-matrix LCDs. The VCC interpolation can be embedded in buffer amplifiers as sub-digital-to-analog converters (DACs), reducing the DAC area without requiring additional power and conversion time. Moreover, interpolation errors due to transistor nonlinearity can be compensated through delicate current ratio control, optimizing both accuracy and area efficiency of the high-resolution data driver. The prototype 10-bit data driver with a 6-bit resistor DAC and a 4-bit interpolation sub-DAC occupies the chip area of 460 ${\mu }{\text{m}}\,\,{\times }$ 14 ${\mu }{\text{m}}$ per channel, which is 10.7% smaller than the conventional 8-bit data driver. The data driver consumes static current of 1 ${\mu }\text{A}$ /channel without dissipating additional power for interpolation. The measured integral nonlinearity and differential nonlinearity are 0.4 LSB and 0.7 LSB, respectively. The proposed scheme has competitive performance in terms of driving accuracy, chip size shrinkage, and static power consumption for high-resolution data drivers. [ABSTRACT FROM AUTHOR]

LEDs have finally emerged as the dominant lighting technology. As such, the lighting industry values power converters that have high efficiency, unity power factor, minimal flicker, dimming, low cost, and a small form factor. This paper presents an integrated circuit (IC) LED driver that is designed to achieve these goals. It introduces multilevel converters with sigma–delta modulation to the power IC space. The driver features a pair of sigma–delta-controlled multilevel converters. The first is a multilevel rectifier responsible for power factor correction and dimming. The second is a bidirectional multilevel inverter used to cancel ac power ripple from the dc bus. The system also contains an output stage that powers the LEDs with dc and provides for galvanic isolation. The IC LED driver has been simulated and prototyped on a silicon fabrication process. Its functional performance indicates that integrated multilevel converters are a viable topology for lighting or other similar applications. [ABSTRACT FROM AUTHOR]

In this paper, the plane-pair partial element equivalent circuit method coupled with the field equivalence principle is developed and applied to calculate the radiated fields of multilayer power planes. The proposed method can be used to solve near-field and far-field radiation problems for multilayer parallel-plane structures with decoupling capacitors. The proposed method is validated by full-wave simulation and experiment. In addition, the proposed method achieves ten times higher computational efficiency than the full-wave simulation. [ABSTRACT FROM AUTHOR]

Traditional control strategy for a power decoupling circuit typically involves a dedicate ripple power control loop, which makes it hard to achieve satisfied transient performance. Meanwhile, traditional single-phase ac–dc converters achieve active power decoupling function with extra power switches, which inevitably increased the cost of the system. In this paper, a controller based on automatic power decoupling concept is proposed for a dependent power decoupling circuit with no extra switches. Compared with the existing methods, the system controlled by the proposed controller has superior transient performance with simplified controller's structure. The controller parameter's design procedures will also be illustrated step by step with the help of the bode diagram. In comparison with traditional control methods, simulations and experiments verify the feasibility of the proposed control methods on the dependent power decoupling circuit. [ABSTRACT FROM AUTHOR]

This paper presents a novel concept for realizing an RF power limiter for protecting superconductor digital receivers. A lumped-element niobium (Nb)-based filter is used as a protection circuit. It consists of lumped-element resonators formed using spiral inductors and metal–insulator–metal capacitors integrated on a multilayer Nb process. The circuit operates as a filter at low-power levels and as a reflector at high-power levels. The lumped-element filter circuit is studied in detail to explain the performance of the filter at high-power levels. It is concluded that some of the lumped-element inductors switch from being inductors when operating at low-power levels to being capacitors when operating at high-power levels. When the lumped-element inductors switch to capacitors, the filter circuit that consists of LC resonators switches to a circuit that consists of capacitors, causing the input power to be reflected back. Both the theoretical and experimental results are presented to verify this phenomenon. In addition to applications in RF power limiters, the concept can be employed to realize transmit/receive (T/R) switches in order to isolate the (T/R) circuit from the receive circuit. [ABSTRACT FROM AUTHOR]

In this paper, new techniques are presented to improve the performance of the optimal switching vector model predictive control. A well-defined analytic technique is proposed for the real-time adjustment of dynamic weighting factors, as well as a new objective function formulation. These techniques provide a dynamic controller behavior, automatically adapted to distinct operating points. This ensures better steady-state performance in different conditions while improving simultaneously the dynamic response. The proposed controller presents a lower computational load than the conventional formulation and its design requires less extensive testing. General guidelines are presented to guide the user in the controller design. Simulation and experimental results are presented, demonstrating the advantages and superior performance of the proposed controller. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a bidirectional distributed amplifier (BDDA) in a 0.18- $\boldsymbol \mu \text{m}$ CMOS process. The performance of the BDDA is theoretically analyzed, and the optimum number of gain stages ($n_{\text {opt}}$), maximum achievable power gain ($G_{P}$), and circuit bandwidth are formulated. In addition, a new formula for proper choice of the number of DA stages (i.e., $n$) is offered where dc-power consumption of the circuit ($P_{\text {dc}}$) is also considered. This formula optimizes $G_{P}/P_{\text {dc}}$ , and it is preferred over the conventional $n_{\text {opt}}$ formula. To validate the theoretical analyses, a 2–12-GHz BDDA with high output 1-dB compression point of +16 dBm and small-signal gain of 10 dB is fabricated. The BDDA chip occupies 1.89-mm2 die area, and its average measured noise figure and $P_{\text {dc}}$ are 6.8 dB and 0.38 W in the high-power mode and 6.5 dB and 0.13 W in the low-power mode, respectively. [ABSTRACT FROM AUTHOR]

It is difficult for a single converter to handle the high voltages involved in dc–dc conversion with a high-voltage input bus. Input-series–output-parallel (ISOP) technology can be used to solve this problem. In this paper, an input voltage sharing control scheme based on peak current (IVSPC) control to guarantee power balance between the modules of the ISOP system is studied. Owing to the peak current control, the output voltage of the system has a good ability to suppress input bus perturbations, and it exhibits good dynamic characteristics even when the input voltage changes significantly with a high slope. The IVSPC control method has two kinds of loops: a common output voltage regulation (OVR) loop and individual input voltage sharing (IVS) loops. The OVR loop provides the same current reference component for all modules, whereas the IVS loops provide different components. The peak current reference signal for each module is the sum of the reference components from the OVR and IVS loops. The performance of the IVSPC control scheme is verified using an ISOP-connected prototype consisting of two flyback converters. [ABSTRACT FROM AUTHOR]

This paper presents two electromagnetic interference (EMI) resisting current mirror topologies that use a linearization technique to filter out the EMI without producing any offset at the output. A proposed current mirror illustrating the linearization concept is implemented in standard $\text{0.18}\;\mu \text{m}$ mixed-mode CMOS technology. Measurement results show that for a frequency range of 10 kHz–10 MHz, the EMI-induced offset current produced by the proposed current mirror is negligible as compared to the traditional current mirror. [ABSTRACT FROM AUTHOR]

To damp the LCL-filter resonance in a grid-connected inverter, the feedback of capacitor current is usually adopted, and it can be replaced by the feedback of capacitor voltage as a low-cost solution, if an accurate digital differentiator can be made. The best way for realizing such a differentiator has so far proved to be an indirect nonideal generalized integrator (GI). As a simple alternative, this paper proposes two digital differentiators, which are directly developed in the discrete domain. They are a first-order differentiator based on backward Euler plus digital lead compensator and a second-order differentiator based on Tustin plus digital notch filter. The basic idea of the proposed methods is to correct their frequency responses to match the ideal differentiator with embedded digital filters. It is shown that the proposed differentiators exhibit the same derivative performance as the nonideal-GI differentiator, and they are more attractive for digital implementations due to their direct discrete natures, compact expressions, and easy algebraic manipulations. In particular, the proposed first-order differentiator is most competitive for its general representation and simplest implementation. Finally, a 12-kW prototype is built, and experiments are performed to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper presents a dc capacitor voltage balancing control method for the star-connected cascaded H-bridge pulsewidth modulation converter in the static synchronous compensator applications. With the zero-sequence voltage injection as a basis for dc capacitors voltage balancing, this paper investigates the detailed power flow of the converter as a whole and within individual modules under unbalanced grid voltages and then proposes a method to control the reactive power output and the dc capacitors voltage by precisely managing the power flow. This approach enhances the low-voltage ride-through capability, which is very critical as the penetration of distributed energy resources grows rapidly. The proposed control method is verified by a scaled-down prototype in the laboratory. [ABSTRACT FROM PUBLISHER]

In analog designs, the most widely adopted layout practice to improve matching is the symmetrical common-centroid placement. However, this arrangement cannot be obtained in general. In this paper, it is shown that there are asymmetrical placements with a common centroid which are also immune to process gradients and suitable for designs where a symmetrical layout is not possible. In addition, this paper proposes an automated method, based on a standard simulated annealing framework, to arrange fully-integrated capacitors in a layout to improve their matching. [ABSTRACT FROM PUBLISHER]

Many publications have been presented on the modulation and control of the modular multilevel converter, some of which are based on phase-shifted carrier modulation. This paper presents an analysis of how the switching frequency affects the capacitor voltages, circulating currents, and alternating voltages using phase-shifted carrier modulation. It is found that switching frequencies that are integer multiples of the fundamental frequency should be avoided as they can cause the capacitor voltages to diverge. Suitable switching frequencies are derived for which the arm and line quantities will be periodic with symmetric operating conditions in the upper and lower arms. Thus, the practical outcome of this paper is a detailed description of how the switching frequency should be chosen in order to achieve advantageous operating conditions. The theoretical results from the analysis are validated by both simulations and experimental results. [ABSTRACT FROM AUTHOR]