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In recent years, very high frequency (VHF) converter has attracted much attention. However, with rich parasitic parameters and complex resonance links, there are some great difficulties to the modeling of such systems. Taking the on-off controlled VHF resonant boost converter as an example, this paper presents an accurate modeling and analysis method that considers multiple parasitic parameters. First, the closed-loop VHF converter system is divided into a main network and a parasitic oscillation network. Then, based on the operation analysis, an equivalent circuit model characterized by a time-varying input voltage source and two variable duty-cycle controlled switches is proposed. It worth noting that both the time-varying input and the controlled switches take into account the influences of the parameters. Furthermore, the periodic approximate analytical solution of the output voltage in the on stage is obtained by using the equivalent small parameter method to the proposed circuit model. And then combining the solution of the parasitic oscillation network and on-off state switching conditions, the steady-state waveform of output voltage can be obtained quickly. Finally, a prototype with operating frequency of 21.44 MHz is built to verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes an adaptive model of modular multilevel converter (MMC) for electromagnetic transient (EMT) simulations. The model is applicable to MMCs with arbitrary numbers of half-bridge and full-bridge submodules. The proposed design includes average value model, arm equivalent model, and detailed equivalent model. It allows smoothly transitioning from one model to another during time-domain simulations depending on the desired accuracy and execution time constraints. Modifications required in conventional MMC models to achieve smooth transitions are presented in the paper. Time-domain initialization methods are developed for each constituting model, including initialization of the appropriate control system blocks. Validity and effectiveness of the proposed adaptive model is demonstrated using EMT simulations of 401-level MMC-HVDC system. [ABSTRACT FROM AUTHOR]

With the increasing penetration of renewable energies in modern power grids, large amounts of voltage source converters (VSCs) have been installed, resulting in many new transient issues. Electromagnetic transient (EMT) simulation plays an essential role in investigating and solving the issues. However, simulation efficiency plunges when object grids contain multiple VSCs, because each switching event incurs modification or re-decomposition of the network matrix in traditional EMT programs, which is very time-consuming. Thus, this paper proposes a VSC model represented by pulse voltage-current source pairs. Accordingly, a unidirectional loosely-coupled solving algorithm is designed. Synthetically, the authors propose a novel EMT simulation approach adaptive to systems with multiple VSCs. The proposed approach keeps the computational network invariable while sufficiently considers detailed switching events, thereby significantly improving the simulation efficiency of the EMTP program without precision loss. [ABSTRACT FROM AUTHOR]

This paper presents a new approach aiming at simulating the steady-state response of dc–dc switching power converters. The proposed method uses the main concept behind the harmonic balance (HB) to compute the amplitudes of the harmonic content in the steady-state waveform. The proposed approach extends the basic HB to enable its efficient implementation to the power converter circuits, through developing equivalent frequency-domain-based stamps for ideal switching elements. The new technique is formulated to yield, along with the amplitudes of the harmonics, the switching times in the ideal switching elements, resulting in the convergence of the Newton method being obtained within few iterations. A major advantage in the proposed method is that it enables removing the control circuitry, which reduces the size of the circuit and significantly contributes to the efficiency of the method. Experimental results show significant speedup over commercial SPICE-based simulators. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for integrated planning of real-life medium-voltage networks based on the utility planning concepts. The research is motivated by the need to develop a methodology that would line-up with utility day-to-day businesses and could be applied in real-life. Its core is a two-stage optimization process, where the first stage solves the static investment optimization and the second stage considers operational problem. A probabilistic decision tree approach is proposed for the solution of the entire problem to consider uncertainties in the planning period. The overall formulation is given first, which is followed by details of the investment model and outlines of the proposed operation planning. The novelty of the investment problem, which determines optimal network reinforcements, is explicit modeling of network security constraints of radially operated networks, whilst considering different operating regimes. Additional novel features include modeling of real-life supply restoration rules through network reconfiguration and optimal placement of new switching devices, as well as consideration of “customer flows” on the network. Connection of new distributed generation and demand centers and construction of circuits on new corridors are also included. Two investment models are formulated as mixed-integer nonlinear optimization problems, tested on several MV networks and compared with established methods. The proposed operational problem is solved in two stages, quality-of-supply and operation cost optimization. Computational aspects are also presented. [ABSTRACT FROM PUBLISHER]

High endurance, high speed, scalability, low voltage, and CMOS-compatibility are the ideal attributes of memories that any integrated circuit designer dreams about. Adding non-volatility to all these features makes the magnetic tunnel junctions (MTJs) an ultimate candidate to efficiently build a hybrid MTJ/CMOS technology. Two-terminal MTJs based on spin-transfer torque (STT) switching have been intensively investigated in literature with a variety of model proposals. Despite the attractive potential of the STT devices, the issue of the common writing/reading path decreases their reliability dramatically. A three-terminal MTJ based on the spin-orbit torque (SOT) approach represents a pioneering way to triumph over current two-terminal MTJs by separating the reading and the writing paths. In this paper, we introduce the first compact model, which describes the SOT-MTJ device based on recently fabricated samples. The model has been developed in Verilog-A language, implemented on Cadence Virtuoso platform and validated with Spectre simulator. For optimized simulation accuracy, many experimental parameters are included in this model. Simulations prove the capability of the model to be efficiently used to design hybrid MTJ/CMOS circuits. Innovative logic circuits based on the SOT-MTJ device, modeled in this paper, are already in progress. [ABSTRACT FROM PUBLISHER]

Existing low-power test generation procedures use a single number to represent the power dissipation in a circuit or subcircuit. As a result, the specific signal transitions they create may deviate substantially from those possible during functional operation (and those the circuit is designed for). Functional broadside tests create functional operation conditions during their two functional capture cycles. Therefore, the specific signal transitions that occur during their second, fast functional capture cycles can occur during functional operation. This paper defines and studies the patterns of signal transitions under the second, fast functional capture cycles of functional broadside tests. These patterns can be used for evaluating the deviations from functional power dissipation created by low-power test sets that consist of arbitrary (functional and nonfunctional) broadside tests. They can also be used for guiding the generation of low-power test sets. The paper presents experimental results for both applications. [ABSTRACT FROM AUTHOR]

This paper surveys and discusses the state-of-the-art of integrated switched-capacitor and inductive power converters. After introducing applications that drive the need for integrated switching power converters, implementation issues to be addressed for integrated switched-capacitor and inductive converters are given, as well as design examples. At the end of this paper, a comprehensive set of integrated power converters are compared in terms of the main specifications and performance metrics, thereby allowing a categorization and providing application-oriented design guidelines. [ABSTRACT FROM AUTHOR]

The boost converter with a voltage multiplier cell allows the static gain extension by means of the switching capacitor technique, reducing the duty cycle needed to achieve the same voltage gain when compared to the conventional boost converter. However, the modeling of this converter is complex and requires the use of advanced techniques due to the resonant inductor. Thus, this paper aims to present a reduced-order model of this converter without the resonant energy exchange between the capacitors, so that the state-space averaging technique can be applied assuming small ripple in the state variables. In addition, this paper presents the design of a control system for the boost converter with a voltage multiplier cell. The adopted strategy employs an inner loop to control the input current and an outer loop for the output voltage regulation. Extensive analysis based on simulations and an experimental prototype demonstrate that the proposed modeling, although simplified, is sufficient for an adequate control system design, ensuring good voltage regulation, and fast transient responses. [ABSTRACT FROM PUBLISHER]

By the logical statements and linear inequalities, a new modeling method named bi-switching status modeling (BSM) method is presented to model the dc–dc converters in this paper. Compared with other modeling methods, such as the state-space averaging method and the mixed logical dynamical (MLD) method, first, the BSM method can describe continuous conduction mode and discontinuous conduction mode operations of the dc–dc converters as a unified bi-switching status model. Second, the BSM method is more precise than the state-space averaging method because there is no approximate assumption. Third, the constrains of the operating modes in the BSM method can be simplified as a consolidated inequality, which means that the model obtained by the BSM method is more concise than that obtained by the MLD method. Simulation and available experiments of a buck converter verify the effectiveness of the proposed BSM method. [ABSTRACT FROM PUBLISHER]

This paper addresses the generation of accurate and efficient macromodels of high-speed input/output buffers. The proposed modeling approach extends the state-of-the-art methods that are currently available, yielding to a modular and scalable tool for model generation. The modeling procedure applies to both single-ended and differential devices, possibly exhibiting a rich dynamical behavior due to large supply fluctuations or internal voltage regulators. The models are defined by the combination of static surfaces described via compact tensor approximations and linear dynamical state-space relations generated using a robust time-domain vector fitting algorithm. A simple and effective solution is adopted to account for the overclocking operation of output buffer models as well. The feasibility and strength of the proposed method are demonstrated using real devices and complex application test cases for signal and power integrity cosimulations. [ABSTRACT FROM PUBLISHER]

Positive leader current spikes were observed in long air gap discharge. However, there has been no explanation on this phenomenon so far, and some leader advancement models can only produce the current without spikes. Therefore, it is necessary to figure out this phenomenon in order to deepen the understanding of leader discharge. In this paper, experiments of leader development were carried out in a 10 m rod-plane gap under positive switching impulse. The discharge current and high speed photographs of discharge process were recorded synchronously. Then the high speed photographs during the period when the leader current fluctuated were carefully analyzed. The experimental results showed that the leader current spikes were with leader branching. Finally, the effect of branching on the spikes of positive current was explained qualitatively and a hypothesis on leader branching was proposed. [ABSTRACT FROM AUTHOR]

Frequently considered one of the promising solutions for grid connection of the photovoltaic (PV) power generation system, module-integrated converters have been the focus of numerous papers. Most of the proposed approaches thus far have relied on the use of series string of the dc-dc converter to create a high-voltage string connected to the dc-ac inverter. The boost converter is better in this application. However, under inhomogeneous irradiation, the power generated by each PV module and the output dc voltage of each boost become unbalanced so that the output currents of each boost are balanced and equal to the string current. In this case, the boost converter cannot always deliver all the power from a mixture of shaded panels and those delivering full power. In this paper, a nondissipative string current diverter is proposed to overcome this problem. One important feature of the proposed circuit herein is the ability to effectively decouple each converter from the rest of the string, making it insensitive to change in the string current. Hence, it is possible to obtain the maximum power from the PV module with the maximum power point tracking algorithm implemented on each dc-dc converter and to do so at the optimum efficiency. The simulation and experimental results verify that the proposed topology exhibits notable performances despite inhomogeneous irradiation. On the other hand, the string current diverter circuit is very easy to control and does not operate without inhomogeneous irradiation, so the topology efficiency is improved for any type of irradiation. [ABSTRACT FROM AUTHOR]

Recent advances in lithium-ion battery modeling suggest unequal but controlled and carefully timed charging of individual cells by reduce degradation. This paper compares anode-side film formation for a standard equalization scheme versus unequal charging through switches that are controlled by deterministic dynamic programming (DDP) and DDP-inspired heuristic algorithms. A static map for film growth rate is derived from a first-principles battery model adopted from the electrochemical engineering literature. Using this map, we consider two cells that are connected in parallel via relay switches. The key results are the following: 1) optimal unequal and delayed charging indeed reduces film buildup, and 2) a near-optimal state feedback controller can be designed from the DDP solution and film growth rate convexity properties. The simulation results indicate that the heuristic state feedback controller achieves near optimal performance relative to the DDP solution, with significant reduction in film growth compared to charging both cells equally, for several film growth models. Moreover, the algorithms achieve similar film reduction values on the full electrochemical model. These results correlate with the convexity properties of the film growth map. Hence, this paper demonstrates that unequal charging may indeed reduce film growth, given certain convexity properties exist, lending promise to the concept for improving battery pack life. [ABSTRACT FROM PUBLISHER]

This paper suggests a pedagogical approach to teaching the subject of average modeling of PWM switch-mode power electronics systems through simulation by general-purpose electronic circuit simulators. The paper discusses the derivation of PSPICE/ORCAD-compatible average models of the switch-mode power stages, their software implementation, and fast time-domain, frequency-domain, and stability analysis simulation techniques suitable for virtual study of complex switch-mode feedback systems. The proposed approach is demonstrated by a simulation example. The methodology is oriented toward Electrical Engineering students at the undergraduate level, enrolled in courses such as “Power Electronics,” “Industrial Electronics,” or the like. The paper can be helpful to instructors of a “Virtual Power Electronics Laboratory” course wanting to conduct a software experiment on dynamics of switch-mode power converter systems. Engineers and scientists approaching the task of simulation of switch-mode systems can also find the suggested technique useful. [ABSTRACT FROM AUTHOR]

In this paper, a direct ac–dc power electronic converter topology is proposed for efficient and optimum energy harvesting from low-voltage microgenerators. The converter utilizes the bidirectional current-conduction capability of MOSFETs to avoid the use of a front-end bridge rectifier. It is operated in discontinuous conduction mode and offers a resistive load to the microgenerator. Detailed analysis and modeling of the converter is presented. In such low-power applications, the power consumption of gate drive and control circuits should be minimal. In this paper, they are specifically designed to consume very low power. A suitable startup circuit and auxiliary dc supply circuit is proposed for the implementation of the converter. A low-voltage microgenerator is used to verify the performance and operation of the converter and the gate drive circuits. [ABSTRACT FROM AUTHOR]

Switched-capacitor (SC) converters were initially introduced for low-power applications and monolithic integration. In recent years, SC converter has found high-power applications. However, voltage regulation remains an issue. This paper addresses regulation challenges for high-power SC converters, based on charge-balance transient-calculation (CT) modeling method and peak current stress estimation. With the help of CT model, due to its accuracy and comprehensive relationship, circuit and control parameters’ impacts on regulation become straightforward and concerns on components stresses can be addressed quantitatively. The suitability of CT method for regulation analysis is confirmed by comparison with traditional modeling methods. The CT method is used in a 1-kW 3X two-switch boosting switched-capacitor converter (TBSC) circuit for steady-state analysis and current stress estimation. The soft rising input current and nature interleaving properties of 3X TBSC make it well suited for high-power application. Finally, the small-signal model of the 3X TBSC is developed and a closed-loop operation is achieved under 1 kW power rating. [ABSTRACT FROM AUTHOR]

This paper revisits the switched flow graph (SFG) technique. A general and unified equivalent SFG model of a three-terminal switcher encountered in regular and tapped inductor converters operating in the continuous conduction mode is proposed. The model can be applied to most PWM topologies and facilitates construction of a complete flow graph of a given converter. The approach can be helpful in theoretical analysis and derivation of analytical expressions of converter's small-signal transfer functions. The suggested methodology extends the previously proposed SFG analysis technique and alleviates the principal difficulties involved. Furthermore, the approach is straightforward and expeditious. Application guidelines and examples are presented and compared to simulation and earlier theoretical results. [ABSTRACT FROM PUBLISHER]

Most investigations of all spin logic (ASL) have been based on the monodomain approximation of magnetization switching. The sensitive and stochastic nature of spin transfer torque (STT) switching creates pressing requirements for analyzing ASL from a micromagnetic perspective also. Hence, in this paper, ASL is studied from a micromagnetic perspective by developing a simulation framework that can capture diffusive spin transport. The spin transport model is calibrated from the existing experimental results on nonlocal spin valve measurements. Then, using this framework, STT switching is studied for input–output nanomagnets with in-plane and perpendicular magnetic anisotropy for ASL devices (ASLDs). Precisely defined architecture and design constraints for such input–output nanomagnets are presented. Further, a previously proposed switching mechanism by driving the nanomagnet into a metastable state is also incorporated into micromagnetic framework. Using the aforementioned mechanism, the critical current required for STT switching can be reduced to as low as 20 $\mu $ A. Moreover, the graphene channel ASLD using tunnel contact at the injector is demonstrated for copy and invert logic operations. [ABSTRACT FROM AUTHOR]

A family of “Two-Switch Boosting Switched-Capacitor Converters (TBSC)” is introduced, which distinguishes itself from the prior arts by symmetrically interleaved operation, reduced output ripple, low yet even voltage stress on components, and systematic expandability. Along with the topologies, a modeling method is formulated, which provokes the converter regulation method through duty cycle and frequency adjustment. In addition, the paper also provides guidance for circuit components and parameter selection. A 1-kW 3X TBSC was built to demonstrate the converter feasibility, regulation capability via duty cycle and frequency, which achieved a peak efficiency of 97.5% at the rated power. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

A dual-active-bridge-based single-stage ac/dc converter may find a wide range of emerging applications such as interfacing plug-in hybrid vehicles with the ac grid, interconnection of dc grid, etc. This type of converter can be used due to unique features such as 1) high-frequency isolation resulting in a) high power density and b) safety and voltage matching; 2) bidirectional power flow; 3) soft switching leading to higher efficiency. In this paper, a modulation strategy has been proposed that results in 1) open-loop power factor correction; 2) zero current switching in the ac-side converter for all load conditions; 3) linear power relationship for easy control implementation; and 4) Zero voltage switching in the load side converter. The converter with the proposed control has been analyzed. Simulation and experimental results on a 1-KW prototype confirm the advantages. [ABSTRACT FROM AUTHOR]

High-frequency-link (HFL) power conversion systems (PCSs) are attracting more and more attentions in academia and industry for high power density, reduced weight, and low noise without compromising efficiency, cost, and reliability. In HFL PCSs, dual-active-bridge (DAB) isolated bidirectional dc-dc converter (IBDC) serves as the core circuit. This paper gives an overview of DAB-IBDC for HFL PCSs. First, the research necessity and development history are introduced. Second, the research subjects about basic characterization, control strategy, soft-switching solution and variant, as well as hardware design and optimization are reviewed and analyzed. On this basis, several typical application schemes of DAB-IBDC for HPL PCSs are presented in a worldwide scope. Finally, design recommendations and future trends are presented. As the core circuit of HFL PCSs, DAB-IBDC has wide prospects. The large-scale practical application of DAB-IBDC for HFL PCSs is expected with the recent advances in solid-state semiconductors, magnetic and capacitive materials, and microelectronic technologies. [ABSTRACT FROM AUTHOR]

An efficient converter topology for extracting maximum power from a photovoltaic module is presented in this paper. The proposed topology is implemented on a stand-alone battery charging system. A reversed buck–boost converter enabling parallel power processing (PPP) with a power switch referenced to the common return is the core of the charging system. Small-signal analysis of the proposed charging system is carried out to facilitate the design of a compensator for maximum power point (MPP) tracking. The simulation and experimental results confirm the validity of the model and verify the high efficient operation while tracking the MPP. The use of the PPP with split loads is also presented which would improve the converter size, efficiency, and step-down duty ratio. [ABSTRACT FROM PUBLISHER]

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I>Ico) and Neel-Brown model (I<0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication. [ABSTRACT FROM AUTHOR]

This paper presents simplified nonlinear averaged large-signal and linear small-signal models of the three basic dc–dc converter topologies, boost, buck, and noninverting buck–boost, respectively, operating in peak current-mode control. Models have been derived for the continuous and discontinuous conduction mode. The modeling methodology used is the equivalent current injected method. The derived models have been compared to the existing full-order large-signal nonlinear models and have been found to exhibit simulation time reduction by a few magnitudes in complex distributed power systems, such as today’s popular microgrids. The models developed have been experimentally verified on a custom-built 120-W boost converter prototype, showing great accuracy in steady state and in dynamical behavior in all operating points, as determined by the output resistance. [ABSTRACT FROM PUBLISHER]

Reducing feature sizes and power supply voltage allows integrating more processing units (PUs) on multiprocessor system on chip (MPSoC) to satisfy the increasing demands of applications. However, it also makes MPSoC more susceptible to various reliability threats, such as high temperature and power/ground (P/G) noise. As the scale and complexity of MPSoC continuously increase, monitoring and mitigating reliability threats at runtime could offer better performance, scalability, and flexibility for MPSoC designs. In this paper, we propose a systematic approach, on-chip sensor network (SENoC), to collaboratively predict, detect, report, and alleviate runtime threats in MPSoC. SENoC not only detects reliability threats and shares related information among PUs, but also plans and coordinates the reactions of related PUs in MPSoC. SENoC is used to alleviate the impacts of simultaneous switching noise in MPSoC's P/G network during power gating. Based on the detailed noise behaviors under different scenarios derived by our circuit-level MPSoC P/G noise simulation and analysis platform, simulation results show that SENoC helps to achieve on average 26.2 percent performance improvement compared with the traditional stop-go method with 1.4 percent area overhead in an 8*8-core MPSoC in 45 nm. An architecture-level cycle-accurate simulator based on SystemC is implemented to study the performance of the proposed SENoC. By applying sophisticated scheduling techniques to optimize the total system performance, a higher performance improvement of 43.5 percent is achieved for a set of real-life applications. [ABSTRACT FROM PUBLISHER]

In this paper, a new method is proposed to model the simultaneous switching noise (SSN) using time-domain impedance function, which is based on the rational function in time domain. The time-domain impedance function of a power delivery network (PDN) is calculated by approximating the impedance frequency response of a PDN with a rational function, and the SSN is calculated based on switching current characteristics, which is verified by advanced design system, Hspice and measurements. Based on time-domain impedance function, the SSN suppression is also investigated, and it is found that the SSN produced by periodic switching current can be suppressed through adjusting the periods of time-domain impedance function and switching current, and a principle for random switching current is also given to prevent the occurrence of the worst case of SSN in circuit design. [ABSTRACT FROM AUTHOR]

Power supply noise (PSN) has become a critical issue during high-quality at-speed testing. Discrepancies between the circuit's switching activity during functional and test mode can cause overtesting and lead to yield loss. Alternatively, reduced PSN effects around critical paths can result in undertesting the chip, causing test escapes. To achieve a high-quality at-speed test, it is necessary to solve these problems simultaneously. Our previous work introduced a noise index model (NIM), which can be used to predict the mismatch between expected and real path delays. This paper quantitatively investigates and compares NIM values for critical paths during functional and test mode. We then propose a test pattern modification method that harnesses the NIM. The method fills a subset of the don't care bits in partially specified test vectors such that the worst observed functional NIM for the targeted critical path is replicated during test mode. [ABSTRACT FROM PUBLISHER]

The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current–voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior. [ABSTRACT FROM PUBLISHER]

This paper provides the comprehensive development procedures and mathematical model of an adjustable speed drive (ASD) for steady-state solutions, transient trajectories, and local stability based on a Floquet multiplier theory. A complete representation of the ASD is employed, which includes the dynamic equation of the dc link capacitor and the detailed models of the diode rectifier and of the pulse width modulated inverter. The power electronic switches are efficiently represented through smooth functions that allow a larger integration step to be used without the loss of precision in the solution. An efficient technique in the time domain for the computation of the periodic steady-state solution of electric systems, including ASDs based on a discrete-exponential-expansion matrix and the Poincaré map, is used. The obtained results are validated against the solutions obtained with an implementation using the Power System Blockset of Simulink and against the response obtained by the measurements from a 1.5-kVA ASD experimental setup system. [ABSTRACT FROM AUTHOR]

This paper investigates the trade-off between speed and accuracy of a Josephson comparator by numerical simulations. The accuracy is quantified by the width of the gray zone whereas the speed is determined by the switching time of the comparator cell. In contrast to previous studies, both performance parameters are simultaneously evaluated. It turns out that there is an inherent compromise between speed and accuracy that is robust against modifications of circuit parameters. Eventually, a new comparator topology is proposed to improve the accuracy while maintaining a reasonable switching speed. [ABSTRACT FROM AUTHOR]

This paper presents a V-band 2-bit switched-line phase shifter using dc-contact single-pole four-throw (SP4T) RF microelectromechanical systems (RF-MEMS) switches for 60-GHz applications. The design and measurements of the SP4T RF-MEMS switches and the phase shifter are presented. The phase shifter demonstrates an average insertion loss of 2.5 dB in the 55–65-GHz band with a return loss better than 12 dB for each state. The phase error for each state of the switched-line phase shifter is less than 1° at 60 GHz. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the di/dt capability and the turn-on action of conventional thyristors (including common thyristor and GTO) under short pulse conditions. Although the common thyristor is proven to be not adequate for pulse application, the GTO behaves excellently and it exhibits the potential of being operated in the case of much higher di/dt and pulse current than its rated values. Multi-cell PSpice simulation model of GTO was developed to evaluate influence factors of current distribution in thousands units of the GTO. It was found that forward transport time (TF) of excess carriers flowing through base region in each unit mainly determines the current distribution. If some unit has smaller TF, it will bear larger current compared with others in the turn-on process and thus has the risk of overheating. The use of magnetic switch in series with GTO can greatly reduce the power dissipation in the process and guarantee the GTO?s safe operation. Our tests have originally resulted in a maximum di/dt of 6 kA/μs for a 10-μs half-sine wave current pulse of 17.3 kA amplitude by using a GTO, whose rated RMS on-state current is 1500 A and di/dt capability is 800 A/μs. The measurements show that turn-on losses and conduction losses are less than 0.5 J. [ABSTRACT FROM AUTHOR]