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As this Special Section goes to publication, semiconductor manufacturing in the United Status, and globally, continues to expand at a seemingly torrid pace. Assisted by government funding and driven in part by artificial intelligence workloads that gobble up increasing amounts of data center computing capacity, Intel and TSMC fabs are going up in Arizona, TI and Samsung fabs are coming to Texas, and Micron has big plans in New York. Unfortunately, just like those flying cars we were once promised, AI has not yet eliminated the need for the skilled trades and engineers required to build and successfully operate a fab. As a result, workforce development has become an important part of the increasingly complex semiconductor manufacturing process: Where are the thousands of engineers the semiconductor industry needs to staff these new fabs going to come from? How can we make more students excited about science and engineering? While the Guest Editors don’t have all the answers, we are happy that ASMC contributes to the solution by actively supporting student presentations and posters and annually recognizing the best student paper of the conference. And, maybe some day, the artificial intelligence systems that semiconductor manufacturing has enabled will give us those Star Wars or Star Trek robots that can build fabs and make chips too. [ABSTRACT FROM AUTHOR]

The 2022 ASMC, our 33rd, returned to Saratoga Springs, NY as an in-person conference after 2 years as a virtual conference. While we are all grateful for the digital world’s enhancements that allowed this conference to be held remotely, attendees were happy to return to an in-person event where networking is much easier. [ABSTRACT FROM AUTHOR]

This paper studies simultaneous scheduling of production and material transfer that arises in the semiconductor photolithography area. In particular, the right reticle and right job both need to be present to process the job. Jobs are transferred by a material handling system that employees a fleet of vehicles. Reticles serving as an auxiliary resource are also transferred from one place to another by a different set of vehicles. This intricate scheduling challenge, encompassing jobs, reticles, machines, and two distinct sets of vehicles, is explored here for the first time. The paper introduces a multi-stage methodology that involves relaxation, a constructive heuristic, constraint programming, and a warm-start approach to address this complex problem. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing processing can be jeopardized due to process fluctuations, and the degradation of equipment parts can significantly influence process variation. Timely diagnosing equipment faults causing process variations is desired in current high-end product manufacturing. This paper proposes a diagnostic method for the SiH4 gas flow rate drift using N2 vibrational transition in oxide deposition. In this research, optical emission spectroscopy (OES) and quadrupole mass spectrometer (QMS) are employed as condition monitoring sensors serving as a reference model to compare the diagnostic performance for gas flow rate drift. The study observes that the OES model exhibits much higher performance for minor diagnoses of less than 5% drift. The diagnostic model performance can be enhanced by incorporating plasma condition and gas indicators compared to when these indicators are used individually. This suggests that when conducting diagnostics for equipment and processes, it is crucial to consider indirect indicators like plasma indicators along with direct indicators such as gas radical density. The comprehensive use of both types of indicators enhances the diagnostic performance, providing a more accurate assessment of the conditions and potential problem in semiconductor manufacturing. [ABSTRACT FROM AUTHOR]

The increasing availability of data, advances in computational and storage capacities of IT systems, and algorithmic advances in Artificial Intelligence (AI), especially Machine Learning (ML) combine to enable significant improvements in the efficiency, operations and throughput of manufacturing systems at the production level. The semiconductor industry is one of the most data-intensive industries and has seen increased use of AI-based technologies over the last few years. In order to develop effective AI-based technologies in the semiconductor manufacturing industry several issues have to be taken into account, including scalability, heterogeneity of data, and the need for interpretability. [ABSTRACT FROM AUTHOR]

This is a panel paper that discusses the use of Artificial Intelligence (AI) technologies to address production and supply chain level problems in semiconductor manufacturing. We have gathered a group of expert semiconductor researchers and practitioners from around the world who have developed AI solutions for various semiconductor problems. This paper aims to provide their answers to an initial set of questions and provide an overview of the AI developments and empirical studies to make suggestions for future directions in this arena. [ABSTRACT FROM AUTHOR]

This paper presents an empirically grounded model, which links organizational learning to pattern-specific fixed costs in integrated device manufacturing. The approach described in this paper helps fab managers make fundamental strategic decisions concerning product design and product mix by engaging in scenario planning. Four critical aspects of managing pattern-specific fixed cost are analyzed in detail—sensitivity to time, design cost, and production volume; platform designs; process postponement solutions; and design penalties. The model suggests that designers and fabrication facilities must collaborate extensively on the design and realizations of product platforms for state-of-the-art integrated circuit products to remain economically viable. [ABSTRACT FROM AUTHOR]

This paper proposes a linear regression model for scalar-valued responses and two-way functional (bivariate) predictors. Our motivation stems from the quality evaluation of products based on optical emission spectroscopy data from virtual metrology of semiconductor manufacturing. We focus on multivariate cases where the smoothness and shapes of the data vary significantly across variables. We propose a two-step solution to this problem, consisting of decomposition and prediction. First, we decompose the two-way functional data into pairs of component functions using functional singular value decomposition. Next, we build functional linear models for the decomposed functional variables and obtain the final predictor by averaging the models. Results from numerical studies, including simulation studies and real data analysis, demonstrate the promising empirical properties of the proposed approach, especially when the number of predictors is large. [ABSTRACT FROM AUTHOR]

This paper addresses the quality control of the photolithography process in the semiconductor industry. Overlay errors in the process seriously affect the wafer yield, and cause the wafer to be forced to rework and affect the production efficiency of the equipment. We examine the current state of its process control, develop a novel overlay predict model, and verify the prediction results. This study proposes a Global Attention Generative Adversarial Networks (GAGAN) model to precisely predict the overlay error for the feed-forward data of the front layer, which is used as the important information and process parameters for the advanced process control of the current layer. Experiment results on a semiconductor shop-floor confirms that our proposed method achieves high predictive performance while maintaining extensibility and visual quality. [ABSTRACT FROM AUTHOR]

The ten papers in this special section are enhanced versions of some of the best papers from the 2012 SEMI Advanced Semiconductor Manufacturing Conference. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing has been extensively exploiting machine-learning (ML) to process equipment sensory data (ESD) for near-real time anomaly detection (AD). ESD characteristics are highly diversified and data lengths vary among processing steps and cycles. Cleansing ESD with minimum distortion (CMD) to fit the fixed-length input requirement by ML-based AD is critical to AD effectiveness and is challenging. This paper presents a novel CMD method of four innovations: i) statistical mode-based equalization of step data lengths for the least number of step data length changes, ii) importance indicator value (IIV) of a data sample based on its relative difference with the subsequent sample, and iii) step data segmentation into groups based on samples of significant IIVs and the least-entropy-group-to-cleanse-first rule, and iv) cleansing the least IIV sample(s) in the selected group for step data length equalization. CMD application to ESD demonstrates its characteristics preservation property. Simulation experiments are on an integration of data cleansing with an unsupervised ML-based AD system, STALAD. Comparisons with two benchmark methods over AD scenarios of small-scale drifts and shifts show that CMD not only is superior in facilitating accurate detection by STALAD but also helps detect anomaly much earlier than using the two benchmarks. [ABSTRACT FROM AUTHOR]

This paper studies the problem of scheduling machines in the photolithography area of a semiconductor manufacturing facility. The scheduling problem is characterized as an unrelated parallel machine scheduling problem with machine eligibilities, sequence- and machine-dependent setup times, auxiliary resources and transfer times for the auxiliary resources. Each job requires two auxiliary resources: a reticle and a pod. Reticles are handled in pods and a pod contains multiple reticles. Both reticles and pods are used on multiple machines and a transfer time is required if transferred from one machine to another. A novel constraint programming (CP) approach is proposed and is benchmarked against a mixed-integer programming (MIP) method. The results of the study, consisting of a real-world case study at a global semiconductor manufacturer, demonstrate that the CP approach significantly outperforms the MIP method and produces high-quality solutions for multiple real-world instances, although optimality cannot be guaranteed. [ABSTRACT FROM AUTHOR]

Since its beginning in 1992 in Japan, International Symposium on Semiconductor Manufacturing (ISSM) has provided unique opportunities to share the best practices of semiconductor manufacturing technologies for professionals. At the symposiums, semiconductor manufacturing professionals discussed the technologies developed to meet the worldwide requirements for advanced manufacturing. It is becoming crucial to re-examine semiconductor manufacturing in terms of fundamental principles to improve the performance of semiconductor devices. Moreover, utilizing artificial intelligence and machine learning technologies to improve semiconductor manufacturing have become a new challenge. These manufacturing technology challenges are showing the need for drastic revolutionary concept and stronger collaborative efforts to find solutions to the precompetitive challenges. [ABSTRACT FROM AUTHOR]

A variety of processes in the semiconductor industry require heating of the silicon wafer to the desired temperature. This process is widely referred to as rapid thermal processing. However, the contactless measurement of the surface temperature of the wafer is still a major challenge, especially in the case of rotating wafers. Measurements using infrared cameras are not suitable due to the fact that silicon is transparent in this wavelength range. Special sensors based on the principle of pyrometry are available, but such sensors can only measure the surface temperature at one single point. This paper presents an observer approach that estimates the wafer’s surface temperature by using the temperature measurement of only one pyrometer. The approach is based on a mathematical model capturing the dynamical behavior of the wafer’s temperature. It relies mainly on the quasi-linear heat equation. Real world experiments demonstrate the achieved accuracy of the proposed approach. [ABSTRACT FROM AUTHOR]

Historically, much attention has been given to the unit processes and the integration of those unit processes to improve product yield. Less attention has been given to the wafer mini environment, either during processing or post processing. This paper contains a detailed discussion on how particles and airborne molecular contaminants (AMCs) from the wafer mini environment interact and produce undesired effects on the wafer which in turn cause devices to fail. Sources of wafer environmental contamination are the processes themselves, ambient environment, outgassing from wafers, and front open unified pod (FOUP) contamination. Establishing a strategy that reduces contamination inside the FOUP mini environment will decrease defect variability and thus increase yield. In manufacturing ecosystem, changing the FOUP or moving the wafers faster or purging with nitrogen to reduce the impact from mini environment is not always an option. Alternative to having a stop gap, it is desired to understand the AMCs and thus exploring sustainable solutions to minimize them below certain thresholds that would cause impact on wafer. NH3-based contamination, extensively discussed in this paper, is observed to cause wafer defects. Thus, explicit knowledge of AMC type is critical, as the most optimized methodology to control various AMCs might not always be the same. Three primary variables that greatly impact this strategy are FOUP contamination mitigation, FOUP material, FOUP metrology, and cleaning method. [ABSTRACT FROM AUTHOR]

Identifying the patterns of defective chips in wafer bin maps (WBMs) in semiconductor manufacturing processes is crucial because different defect patterns correspond to different root causes of process failures. Recently, mixed-type defect patterns (i.e., multiple defect patterns in a single wafer) have become increasingly common owing to the increased complexity of semiconductor manufacturing processes. Previous methods for classifying mixed-type defect patterns in WBMs focused on outputting only the class labels of the defect patterns and not their locations, although location information of the defect patterns is useful for tracking the root causes of failure and improving processes. Moreover, most previous methods used only labeled WBM data, although a larger quantity of unlabeled WBM data are more accessible because of the costly process of label annotation. Therefore, in this paper, we propose a semi-supervised learning method for classifying mixed-type defect patterns and detecting their locations simultaneously using both labeled and unlabeled WBM data. The proposed method extends a recent unsupervised object detection method called Attend-Infer-Repeat in a semi-supervised manner to perform object detection and classification simultaneously. The performance of the proposed method is verified using WBM datasets of different sizes. The results demonstrate the effectiveness of the proposed method for classification and location detection. [ABSTRACT FROM AUTHOR]

Design Hotspots are features on a silicon chip, which are susceptible to pattern failures. While multiple methods like DRC, ORC, and in-line defect inspection are used to identify these hotspots, in-line monitoring of these Design Hotspots has remained a challenge. Existing methods of hotspot inspection, which include API and EBI are not suited for large scale inspection due to system limitations and throughput limitations, respectively. NanoPoint inspection, which is a recent advance in BBP inspection, has enabled in-line inspection of Design Hotspots at very high throughput. In addition, new monitoring strategies are needed to monitor the hotspots inline. In this paper, a methodology for in-line inspection and monitoring of Design Hotspots using NanoPoint BBP inspection is presented. [ABSTRACT FROM AUTHOR]

Semiconductor manufacturing consists of multiple sequential processes. In addition, even in a single process, a wafer must pass several steps. Accordingly, a dataset generated in semiconductor manufacturing has sequential information. Thus, the sequential information between steps and processes must be considered when predicting a target variable such as a yield or defect status. This paper proposes a method that utilizes the concept of residual learning to capture sequential information. Specifically, we propose to learn several modules that use data gathered starting from different steps and obtain a final decision by combining all modules’ decisions. In each module including multiple models, the first model is trained to predict the target variable using the data from the earliest step, and the remaining models are trained to predict the residuals that cannot be explained by the models for the previous steps based on the concept of residual learning. We conducted extensive experiments using two real-world semiconductor manufacturing datasets and found that even though each module’s performance was not good, the final decision obtained by combining all the modules’ decisions achieved a significant performance improvement. As a result, the proposed method significantly outperformed the baseline models. [ABSTRACT FROM AUTHOR]

The papers in this special section were presented at the 2013 Advanced Semiconductor Conference (ASMC). [ABSTRACT FROM AUTHOR]

We study a parallel batch-scheduling problem that involves the constraints of different job release times, non-identical job sizes, and incompatible job families, is addressed. Mixed integer programming and constraint programming (CP) models are proposed and tested on a set of common problem instances from a paper in the literature. Then, we compare the performance of the models with that of a variable neighborhood search (VNS) heuristic from the same paper. Computational results show that CP outperforms VNS with respect to solution quality and run time by 3.4%–6.8% and 47%–91%, respectively. When compared to optimal solutions, the results demonstrate CP is capable of generating a near optimal solution in a short amount of time. [ABSTRACT FROM AUTHOR]

Equipment at the end of functional life poses several challenges for manufacturing operations and long-term asset sustainability. This is even critical for semiconductor manufacturing where equipment upgrades are capital intensive with a longer return horizon. This demands an objective and quantifiable approach to manage and monitor the end-of-life health of the manufacturing systems. The paper presents a practical three-level approach that brings together engineering, operational, and supply chain factors under a single indicator. A visualization heatmap correlates equipment health to manufacturing impact for engineering and commercial decision-making. The approach is simple yet proven to be effective in fab environments. The proposed analysis applies in formulating system priorities, upgrade strategies, and capital expenditures. Brief guidance on health improvement strategies, application to new fab, and cost-based evaluation are presented for practical use. [ABSTRACT FROM AUTHOR]

In this paper, a cost-effective, easy-install and fast measurement and analysis method to obtain seismic response of semiconductor manufacturing equipments was developed and its validity was discussed. In the developed method, micro-vibration measurement experiments are first carried out to obtain transfer functions and coherence functions from the floor to arbitrary part of equipment. Using obtained transfer function, seismic response of the arbitrary part of equipment is analyzed with seismic floor response input. In this paper, the developed method was applied to a vertical furnace and a lithography system and their transfer functions were experimentally obtained. It has been confirmed that with additional excitation on the floor near the equipment is effective to improve the accuracy of obtained transfer functions. The validity of developed analysis method was confirmed by the good agreement between the analytical result and the experimental result obtained with a shaking table. The developed method is to be useful to estimate seismic damage of various types of semiconductor manufacturing equipment as well as to take seismic countermeasures. [ABSTRACT FROM AUTHOR]

As guest editors for the special section on the 2017 International Conference on Compound Semiconductor Manufacturing Technology (CS-MANTECH), we are pleased to present IEEE Transactions on Semiconductor Manufacturing readers with a selection of papers based on work presented at this year’s conference. The CS-MANTECH conference provides a technical forum for presenting advances in compound semiconductor devices and associated manufacturing technologies. The high performance of devices based on compound semiconductors has long made them the material of choice in RF, microwave, and millimeter-wave systems. While advances continue to be made in these traditional applications, compound semiconductors are increasingly finding their way into power systems via SiC and GaN device technologies, and are also increasingly integrated with silicon-based technologies to provide enhanced system-level performance and functionality. In addition, narrow-gap III-Vs are being explored as alternative-channel materials for aggressively-scaled logic. [ABSTRACT FROM AUTHOR]

Beyond the widely-studied scheduling of wafers within cluster tools, a novel and important perspective is raised in this paper to tackle an upper-level optimization problem in real-world production, i.e., the assignment of hybrid types of wafer lots to a set of cluster tools with parallel modules to minimize the maximum completion time for the lots. The main difficulty in addressing such a problem is that the objective, i.e., the maximum completion time, cannot be calculated explicitly beforehand. To make this problem tractable, the associated maximal overlap among tools is utilized to heuristically evaluate the objective for the problem. Besides, since the cluster tools for processing are identical, we further tackle this problem as a clustering issue. Accordingly, a clustering algorithm based on greedy searching is proposed to allocate wafer lots into cluster tools while minimizing the maximal overlap. To elucidate our method and its significance in real-world production, the wet bench tool in wet cleaning process is taken as a case study. We compare the proposed algorithm with the empirical method in fabs and several intelligent optimization algorithms, and the experimental results verify the effectiveness of our proposed method in terms of improved efficiency. [ABSTRACT FROM AUTHOR]

In semiconductor manufacturing processes, yield analysis aims to increase the yield by determining and managing the causes of low yield. The variable data collected from semiconductor manufacturing processes, in which hundreds of unit processes are implemented according to specific conditions and sequences, are interdependent, and the variables related to previous processes influence the variables in subsequent processes. Therefore, the order of processes should be considered when building a model that searches for the causes of low yield. However, there have been few studies in this area. This paper proposes a low-yield root cause search method considering the order of processes using a long short-term memory with attention mechanism (LSTM-AM) model. Specifically, the LSTM-AM model is applied to data classified according to the process structure of semiconductor products, and the causes of low yield are determined considering the order of processes by extracting attention weights. Experiments are conducted to verify the suitability of the proposed method using real yield data from a semiconductor company. The experimental results confirm that the proposed method outperforms the existing low yield root cause search methods in terms of low yield prediction. [ABSTRACT FROM AUTHOR]

Data-driven Fault Detection and Classification approaches are becoming increasingly important in semiconductor manufacturing and in other industries aiming at implementing the Zero-defect paradigm. Two of the main challenges in developing such solutions are: (i) the complexity of sensor data, that typically presents themselves in the form of time-series, requiring the employment of time-consuming and possibly sub-optimal feature extraction approaches; (ii) the fact that faults/defects may be caused by more than a single process, but in many cases they are generated by a cascade of processes. In this paper, we tackle the first issue, by considering a two-stage case study consisting of a deposition process and a rapid thermal process. The proposed approach is based on convolutional deep autoencoders employed to perform feature extraction from time-series sensor data in frontend production equipment. We will show on the reported case study, how the proposed approach outperfoms key numbers-based approaches typically used in the industry. To allow reproducibility of the reported results and to foster research in the field, we publicly share the data used in this work. [ABSTRACT FROM AUTHOR]

Almost one year ago, we sent selected authors who had presented at the SEMI Advanced Semiconductor Manufacturing Conference 2015 the following letter. [ABSTRACT FROM AUTHOR]

The layout of a semiconductor manufacturing facility can play a significant role in reducing operating costs and improving productivity. This paper introduces the double-bay layout problem that is encountered in semiconductor fabrication. This new problem not only considers the assignment and relative ordering of machines in two bays but also determines the exact location of each machine, and incorporates two objectives of minimizing material handling cost and layout area. A hybrid methodology combining a multi-objective genetic algorithm with linear programming is proposed to solve this problem. The genetic algorithm effectively identifies the set of non-dominated machine sequences, while the linear program uses the relative assignments obtained by the genetic algorithm to determine optimal absolute machine locations. Experimental results indicate that the proposed hybrid methodology finds Pareto-optimal solutions for small-scale problems and high-quality solutions for problems of practical size. [ABSTRACT FROM AUTHOR]

The big picture for the semiconductor industry shows slowing but still positive sales growth, a push back of the transition to 450 mm wafers to perhaps the next decade, and potential commercial implementation of EUV for some layers of some sub-10 nm nodes by 2019–2020.1–3 Per Gartner, current revenue growth is driven by smartphones, solid-state drives, and DRAM.1 A new semiconductor sector, wearables (smartwatches, smart glasses, Bluetooth headsets, etc.) is also driving some revenue growth but on a smaller scale. Critical to this revenue growth is the ability to deliver ever more powerful semiconductor technologies at a competitive cost. [ABSTRACT FROM AUTHOR]

The past year has brought many reminders that we live in an increasingly digital world. Technology shapes and enhances our lives each day on several fronts. •

Shopping from the comfort of our homes.

In this paper, an analysis of gate–source and gate–drain scaling effects in MESFETs fabricated on hydrogen-terminated single-crystal diamond films is reported. The experimental results show that a decrease in gate–source spacing can improve the device performance by increasing the device output current density and its transconductance. On the contrary, the gate–drain distance produces less pronounced effects on device performance. Breakdown voltage, knee voltage, and threshold voltage variations due to changes in gate–source and drain–source distances have also been investigated. The obtained results can be used as a design guideline for the layout optimization of H-terminated diamond-based MESFETs. [ABSTRACT FROM AUTHOR]

In this paper, we focus on yield analysis task where engineers identify the cause of failure from wafer failure map patterns and manufacturing histories. We organize yield analysis task into the following three stages, namely, failure map pattern monitoring, failure cause identification, and failure recurrence monitoring, and incorporate machine learning and data mining technologies into each stage to support engineers’ work. The important point is that big data analysis enables comprehensive and long-term monitoring automation. We make use of fast and scalable methods of clustering and pattern mining and realize daily comprehensive monitoring with massive manufacturing data. We also apply deep learning, which has been an innovative core technology of machine learning in recent years, to classification of wafer failure map patterns, and explore its performance in detail. Finally, these machine learning and data mining techniques are integrated into an automated monitoring system with interfaces familiar to engineers to attain large yield enhancement. [ABSTRACT FROM AUTHOR]

A qualitative empirical study of 29 semiconductor manufacturer and supplier firms investigates the challenges associated with implementing lean practices that require broadly based collaboration across firms. The study's primary contribution is a model of the semiconductor manufacturing ecosystem, which shows how chipmakers, suppliers of enabling technologies, subsystem suppliers, and their respective competitors interact to develop the right technologies at the right time. The study finds that the biggest challenge to industry-wide collaboration is managing knowledge flows between users and suppliers in a manner that allows all parties to collaborate without losing competitive advantage. The paper also presents insights into how inter-organizational knowledge is created synchronously in the semiconductor industry. Finally, the paper makes suggestions as to how interfirm knowledge can be managed. [ABSTRACT FROM AUTHOR]

Virtual metrology (VM) has been successfully applied to semiconductor manufacturing as an efficient way of achieving wafer-to-wafer quality control. VM involves the estimation of metrology variables of wafer inspection using a prediction model trained with process parameters and measurements prior to the actual implementation of metrology. VM modeling should incorporate a number of process parameters and measurements collected from each piece of process equipment, which results in a greater number of input variables. Therefore, it is necessary to resolve the problem of high dimensionality through feature selection. A suitable feature selection method for VM modeling should effectively address the high dimensionality by lowering the computational cost, while also achieving high prediction accuracy as an essential requirement for the practical deployment of VM. In this paper, a feature selection method based on random forward search is proposed for efficient VM modeling. This method selects relevant variables sequentially from disjoint random subsets of candidate variables by incorporating randomness. Our preliminary experimental results obtained with real-world semiconductor manufacturing data demonstrate that the proposed feature selection method achieves comparable prediction accuracy yet has the advantages of being computationally more efficient, thus merits further investigation. [ABSTRACT FROM AUTHOR]

E-beam inspection has become one of the most important tools for rapid yield ramp in the semiconductor industry, due to its ability to detect a wide range of defects in-line soon after their formation. This role expansion is due to the increasing difficulty in detecting defects in-line with other traditional methods as well as the continuing evolution of e-beam capability. In the last five years, the role of e-beam inspection has expanded from detection of electrically active, buried defects using voltage contrast inspection to also detection of many challenging physical defect types as well as systematic patterning defects. This paper reports on the impact of an important recent improvement in e-beam inspection tool capability, the availability of dramatically higher landing energies, and the benefits this improvement provides. These include detection of buried defects, a sharper image for detection of surface physical defects, minimization of wafer charge enabling much longer inspections, and material contrast. These advantages are illustrated through a number of examples. High landing energy can damage certain wafer surfaces and these concerns are also discussed. Overall, high landing energy is a powerful new tool in the e-beam inspection tool box which should be aggressively adopted. [ABSTRACT FROM AUTHOR]

We report the observation of narrow tilted lobes in the far-field emission pattern of leaky oxide-confined vertical-cavity surface-emitting lasers (VCSELs). The VCSEL cavity is surrounded by two selectively oxidized aperture layers, which are intentionally designed to produce a high lateral leakage of the high-order transverse modes of the vertical cavity. The device operates in the fundamental transverse mode at oxide aperture diameters below 5~\mu \textm and currents up to 4 and 5 mA. At higher currents or larger aperture diameters, an additional high-order transverse optical mode evolves. This mode is revealed by the appearance of a shorter wavelength emission line in the electroluminescence spectra of the device, resulting in multi-mode lasing and in the related changes in the near- and far-field patterns. In the far-field pattern, the evolution of the high-order mode is revealed by the evolution of the two overlapping emission lobes at moderate (~5°) tilt angles with respect to the normal to the surface and by the appearance of a multi-spot or a ring pattern in the CCD camera images. Most importantly, the appearance of this high-order transverse mode is accompanied by an observation of much narrower lobes in the far-field pattern observed at significantly larger tilt angles (~35°). The tilt angle and the narrow angular width of these emission lobes in the far-field spectrum are in agreement with those calculated in the 3-D cold cavity modeling of the optical modes of the device. These narrow tilted lobes revealed in this paper are the fingerprints of the leakage effect in specially designed oxide-confined VCSELs with their intensity being proportional to the optical power leaving the aperture region in the direction parallel to the surface and propagating into the oxidized region. The effect can be applied for engineering of single-mode VCSELs, coherently-coupled 2-D VCSEL arrays, laterally integrated VCSEL-photodetector chips, and VCSELs integrated to slow light waveguides, for coupled optical gates for optical computers and other types of photonic integrated circuits. [ABSTRACT FROM AUTHOR]

The introduction of 3-D structures and new materials for advanced logic devices at extremely fine feature size presents challenges for within-wafer and wafer-to-wafer thickness uniformity control that is critical for yield and performance. For conventional chemical mechanical polishing technology, the typical thin film uniformity across the whole wafer may not meet the desired variation target of 2–3 nm 3 \sigma at some critical levels. Furthermore, wafer-to-wafer uniformity variation requires a wafer by wafer approach to uniformity correction. In this paper, a novel etch planarization technology is presented that combines a conventional production-proven etch process that is temperature sensitive with an inductively coupled plasma reactor equipped with a novel electrostatic chuck that provides die level thermal control. Improved process control enables cost effective uniformity improvements in excess of 85%. [ABSTRACT FROM AUTHOR]

Development of touch display driver IC (TDDI) has enabled slimmer smartphone design by virtue of the integration of touch controller and display driver ICs (DDIs) into a single chip. TDDI plays an important role in touch integrated display panels. Compared to conventional DDI, TDDI requires more bonding pads for touch applications, thus increasing the usage of gold. The requirement to keep costs down forces manufacturers to look for ways to reduce the usage of gold. In order to reduce the usage of gold, gold bumping processes with asymmetric tolerances are considered, in which deviations from the target are less tolerable in lower specification limits than in upper specification limits. In addition, due to economies of scale considerations, gold bumping processes involving multiple manufacturing lines are commonly considered in Taiwan. However, no yield index has been developed for multiple-line gold bumping processes with asymmetric tolerances. In this paper, we propose a new yield index C^\prime \prime M{pk} and derive an approximate distribution of $\hat {{C}}^{{\prime \prime M}}_{ {pk}} $ . In addition, the lower confidence bounds and critical values are provided for the multiple-line gold bumping processes with asymmetric tolerances. For illustration purposes, a real-world application in a gold bumping factory which is located in the Science-Based Industrial Park in Hsinchu, Taiwan, is presented. [ABSTRACT FROM AUTHOR]

In this paper, we introduce our developed clean-localized system for a cleanroom-free semiconductor manufacturing where a wafer is air-tightly transferred between the carrier and the machine via a load port and process in a clean chamber. The system has been applied to “minimal fab” specially designed to process a half-inch wafer for low-cost and low-volume device productions. To confirm the localized clean-performance of our system, we have measured the clean levels in process chamber of a machine and the wafer transfer system. Both are resulting in ISO class 4, while the clean level of the circumstance is in ISO class 9. In order to estimate the system performance in the issue of electronic device properties, we fabricate a traditional MOSFET using minimal fab for the entire process. The measured density of interface states ( Dit ) of the MOSFET was 7.7 \times 10^10 cm ^-2 and the off-leak current was 4 \times 10^-12 A. These are sufficiently low to confirm the acceptable particle contamination level of the system which has less impact on the device characteristics. Due to a compact size of the minimal machine, the wafer transfer distance between processes is minimized. The process efficiency of the minimal fab in terms of wafer transfer time and wafer waiting time is also studied. [ABSTRACT FROM AUTHOR]

This paper provides an overview of new approaches for assessing and addressing requirements for carrier logistics in semiconductor manufacturing and discusses solutions for optimizing the efficiency of capital equipment installed in the fab. An exploration of crucial influencing factors (both on the material handling as well as on the equipment side) will be followed by a discussion of different approaches to the challenges and an assessment of the impact of the proposed improvements. This paper also demonstrates how effective equipment throughput can be improved by the proposed methods. [ABSTRACT FROM AUTHOR]

This paper proposes optimization methods of re-entrant hybrid flows with multiple queue time constraints in batch processes of semiconductor manufacturing. A smoothing flow concept and a dispatching rule for the re-entrant flows called “re-entrant flow smoothing” [REFS(X)] and a loading rule for the processes with multiple queue time constraints called “synchronized control of kanban and buffer sizes” (SCKB) were developed and evaluated. These optimization methods aimed to both maximize the throughput ratio of quality products and minimize the lead time of work-in-process. A three-view modeling to combine the objective functions was created to respond to an actual problem scale. For a manufacturing process consisting of five flows and four re-entrant flows with seven queue time constraints, SCKB–REFS(X) improved the throughput ratio of the quality products by 20.0% compared with first-come first-served (FCFS)–conditional time in 40 days. The mean lead time was also shortened by 60.1% because SCKB–REFS(X) could reduce the setup rate by 83.1% and improve the overall equipment effectiveness by 41.9%, though the performance of minimum inventory variability scheduler application rules is almost the same as that of basic FCFS. REFS–SCKB(X) computed the problem in 4 s or less. [ABSTRACT FROM AUTHOR]

Virtual metrology (VM) is crucial for improving process capability and production yield during semiconductor manufacturing processes. However, the performance of VM deteriorates owing to the variable operating regime and the nonlinear characteristics of the process. Herein, Variational inference Gaussian mixture model (VIGMM) and extreme learning machine (ELM) are combined to solve these issues. First, variational inference is conducted on a Gaussian mixture model to determine the number of Gaussian components automatically and the corresponding operating regimes are identified. Subsequently, an extreme learning machine is developed for each operating regime to investigate the nonlinear relationship between process inputs and outputs. Finally, VM is implemented using the corresponding local ELM, which is determined based on the responsibility of the Gaussian components. The feasibility and effectiveness of the proposed methods are validated based on a numerical case and the plasma sputtering process for fabricating thin-film transistor liquid-crystal displays. The proposed VIGMM-ELM can serve as a VM algorithm for manufacturing processes with multiple stages. [ABSTRACT FROM AUTHOR]

Cyclic scheduling and operation of a residency time-constrained single-arm cluster tool with failure-prone process modules are highly challenging. In some cases, when a failure occurs, there still exists a feasible cyclic schedule for the performance-degraded tool. In other cases, such a schedule no longer exists. For the latter, it is highly desired to respond to a process module failure properly such that the tool can continue working and the wafers in the tool can be completed in a feasible way. This work is the first one to study this important issue. The idea is to apply Petri nets to describe the dynamic behavior of a single-arm cluster tool. With the developed Petri net model, this paper formulates failure response policies to control the cluster tool such that it can keep working without violating any residency time constraint. The failure response policies are implemented via efficient real-time control laws. Illustrative examples are presented to show their usage. [ABSTRACT FROM AUTHOR]

Today, the majority of semiconductor fabrication plants (fabs) conduct equipment preventive maintenance based on statistically-derived time-or wafer-count-based intervals. While these practices have had relative success in managing equipment availability and product yield, the cost, both in time and materials, remains high. Condition-based maintenance has been successfully adopted in several industries, where costs associated with equipment downtime range from potential loss of life to unacceptable affects to companies' bottom lines. In this paper, we present a method for the monitoring of complex systems in the presence of multiple operating regimes. In addition, the new representation of degradation processes will be used to define an optimization procedure that facilitates concurrent maintenance and operational decision-making in a manufacturing system. This decision-making procedure metaheuristically maximizes a customizable cost function that reflects the benefits of production uptime, and the losses incurred due to deficient quality and downtime. The new degradation monitoring method is illustrated through the monitoring of a deposition tool operating over a prolonged period of time in a major fab, while the operational decision-making is demonstrated using simulated operation of a generic cluster tool. [ABSTRACT FROM AUTHOR]

In this paper, we report about platform and architecture that real-time analysis of big data are possible, and structured IT infrastructure that they are optimally combined. We developed a distributed architecture which the data conversion and the abnormality determination are multi-blocked. Furthermore, by selecting a distributed storage database (DB), we succeeded in constructing IT infrastructure capable of high-speed processing at a large number of manufacturing sites. In the new IT infrastructure, we achieved resource leveling of the application server and improvement of data processing time. It is expected that data file stagnation and delay of DB registration can be resolved. [ABSTRACT FROM AUTHOR]

Semiconductor industry is both technology and energy intensive. There is a critical need to develop effective ways for energy saving to support smart and green production. This paper aims to develop data mining approach based on neural networks to exploit the value of production data and derive improvement directions for energy saving. In particular, the power consumption per wafer processed step (kilowatt hour per move, kwh/move) of individual production tool sets can be estimated, in which the relationships between kwh/move and 19 individual input factors, including “lot size,” “process time,” “uptime,” “usable machine,” “Q-time constrain,” and “sampling rate” are derived. An empirical study was conducted in a leading wafer fab and the results have shown practical viability of the proposed approach to discover effective opportunities for saving 17.21% power consumption by production tool sets. [ABSTRACT FROM AUTHOR]

Since its start in 1992 in Japan, the International Symposium on Semiconductor Manufacturing (ISSM) has provided unique opportunities to share the best practices of semiconductor manufacturing technologies for professionals worldwide. At the symposium, professionals assemble to discuss the technologies developed to meet worldwide requirements for advanced semiconductor manufacturing. It is crucial to re-examine semiconductor manufacturing in terms of fundamental principles to improve the performance of devices. In addition, manufacturing technologies that preserve the Earth’s environment will require new concepts and stronger collaborative efforts to find precompetitive solutions to the challenges posed. [ABSTRACT FROM AUTHOR]

This paper describes a real-time transfer control method to produce a high throughput for linear tools of semiconductor manufacturing equipment. We developed a transfer control method for various process times with two steps during operation of the equipment. The first step uses a local search to find a transfer sequence producing a high throughput in advance for various process times, and the second step switches between transfer sequences during the operation of the equipment by referring to a decision tree made from the results of the first step. The method calculates the transfer sequence in a time period from recognizing the process time to the start of transferring the wafer and improves the throughput of linear tools in more than 60% of the tested process time combinations. In the most improved case, the throughput improved by 53%. [ABSTRACT FROM AUTHOR]

In this paper we discuss the detection, investigation and remediation of a silicon pitting defect in gate oxide patterning processes. The pitting defect is detected by optical inspection after an oxide wet etch operation. The cause of the physical defect is discovered as the result of Non-Visual Defect (NVD) inspection at process steps prior to the wet etch. A particular type of NVD, electric charge on a photoresist film, is detected at a process step immediately prior to the wet etch. A positive charge exceeding a specific level is highly correlated with the pitting defect, which only occurred on silicon that is doped to create an excess of free holes (p-type silicon). The manufacturing process is modified to reduce the level of process-induced charge, which also reduces the occurrence of pitting defects. A similar pitting defect is subsequently detected on a second manufacturing line at a different technology node. In this case, our investigation reveals that high negative charge on photoresist resulted in pitting only on silicon that is doped to create an excess of electrons (n-type silicon). Finite element modeling is used to identify a possible explanation for the charge-induced pitting defect. [ABSTRACT FROM AUTHOR]

As guest editors for the special section on the 2016 International Conference on Compound Semiconductor Manufacturing Technology (CS MANTECH), we are pleased to present the readership of IEEE Transactions on Semiconductor Manufacturing with a selection of papers developed from presentations made at this year’s conference. While semiconductor wafer volume is dominated by technologies based on silicon, compound semiconductor devices and integrated circuits are important for a range of applications and markets. Compound semiconductors have traditionally found use in technological areas demanding maximum performance, often for high speed or high frequency applications. Examples include high-speed wired, fiber, and point-to-point communications infrastructure, defense-related sensing and communications, and high-efficiency RF power amplifiers in consumer mobile wireless applications. However, recent trends have been eroding these traditional distinctions, with emerging applications such as power control and commercial wireless infrastructure being increasingly addressed using GaN and related materials, while ultra-low-power analog–and even future CMOS nodes for logic–embracing narrow-band gap III-V materials. [ABSTRACT FROM AUTHOR]