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Duty cycle corrector (DCC) using a bang-bang duty cycle detector (BBDCD) correct a 1-3.2 GHz clock duty cycle. Because the accuracy of BBDCD determines the output clock duty cycle, to mitigate the offset of the BBDCD, an average codes method is used. The operating frequency is determined according to capacitance in the BBDCD for a wide frequency. A duty cycle adjuster (DCA) based on a 2-input NAND gate makes a clock with pulse width from the rising edge of the input clock to the falling edge of the digitally controlled delay line (DCDL) output. The IC is designed in CMOS 28nm process. The maximum duty cycle error of the DCC is 1.5 % at 3.2 GHz. The DCC consumes 1.92 mW at the maximum input frequency. The peak-to-peak jitter of the output clock is 12 ps.

This paper presents an adaptive dropout voltage regulator based on a constant on-time buck converter that improves the light load efficiency. By regulating the gate voltage of the pass transistor of the low dropout regulator (LDO), the dropout voltage is automatically minimized depending on the load current, increasing the end-to-end power conversion efficiency at the light load condition by 11.3%. The proposed direct-charging scheme and simple undershoot detector reduce the droop and improve the efficiency of the LDO. The reference pre-compensation technique is proposed to improve the ripple performance by compensating the reference voltage based on the on-time pulses. The proposed voltage regulator was fabricated by a 0.18-wm CMOS process and occupies 0.2874 mm2.

This paper proposes a hybrid DC-DC converter with a new power switch structure and its operating principles. Its main application is a power management IC that supplies compact mobile devices with a low-profile chip inductor, whose DC resistance is relatively high. In step-down mode, DC current flowing through the inductor is reduced by introducing a flying capacitor that assists load current at a certain phase. In step-up mode, average inductor current is smaller than the load current because of power-input power-output equation. A three-phase mode is also added to fill output voltage gap between step-up and step-down modes. By reducing inductor conduction loss, this work shows better power conversion efficiency than a conventional buck converter at heavy load. Using 180 nm general purpose process, the proposed converter takes 2.5 V input and supplies output in between 1.4 V and 5 V. Load current ranges in between 0.3 A and 1.5 A with peak power conversion efficiency of 92.87%.

This paper presents a 10-b 1 MS/s SAR ADC with a proposed triple-charge-sharing technique to reduce switching energy. The proposed technique uses an additional reservoir capacitor, which has 10% of total CDAC size, to recycle 56% of switching energy. The energy-saving efficiency of this technique is most noticeable in MSBs, so the number of the MSBs to apply the technique has been optimized. The prototype of the proposed SAR ADC is implemented in a 28 nm CMOS technology at 1 V supply voltage. Logic power is minimized with 0.4 V supply voltage. The proposed SAR ADC consumes 2.02 J.l W and achieves ENOB of 9.15, equivalent to a Walden FoM of 3.55 fJ/conversion-step.

A bidirectional high-voltage (HV) dual-input (DI) buck converter and a fully integrated maximum power point (MPP) tracker for a triboelectric (TE) energy-harvesting (EH) system are proposed. The proposed MPP tracker carries out the fractional open-circuit voltage (FOCV) method without any external resistor for voltage down conversion. The proposed buck converter regulates two high DC voltages from a triboelectric nanogenerator (TENG) up to 70 V with a single shared inductor. By reducing the capacitance at the switching node, the power conversion efficiency is improved, and the maximum end-to-end efficiency is 70.72%, which is 21.15% higher than prior work.

Bandwidths of memory interfaces have been increased tremendously to enable high-data throughput while maintaining single-ended signaling and the supply voltage of I/O has been scaled down. Due to the increasing interface bandwidth the required area and power consumption has increased as well, resulting in higher I/O circuit design costs [3]. A high-loss channel causes ISI, which in turn limits the maximum data rate. Therefore, complex equalizers are needed for compensation, resulting in additional power dissipation and area overhead. As the data sampling rate increases, the deterministic and random noises degrade the data sampling margin and further limit the bandwidth. To lessen the negative impact of high channel loss and to reduce the forwarded clock frequency, multi-level signaling, such as PAM-4, can be used, as shown in Fig. 23.3.1 [2]. While the voltage sense margin for PAM-4 is theoretically $\frac{1}{3}$ of NRZ, in practice it is smaller due to simultaneous switching noise (SSN), crosstalk, and random noise in single-ended signaling. Eventually, the reduced voltage sense margin degrades the SNR, which causes a reduction in the BER. On the other hand, PAM-3’s voltage sense margin is ${\textstyle \frac {1}{2}}$ of NRZ’s. Duo-binary signaling is commonly used for PAM-3 signaling [1]. However, the pin efficiency and the forwarded clock frequency for duo-binary signaling is the same as for NRZ. In this paper, a 3b/2UI PAM-3 single-ended memory interface is proposed, with a pin efficiency of 150% and a reduced clock frequency, compared to NRZ signaling. To address PAM-3 equalizer inefficiencies a tri-level decision feedback equalizer (DFE) is implemented in the receiver (RX).

Many Internet of Things (IoT) devices have special and demanding design requirements, including limited energy, size, storage and processing capabilities. In addition, many IoT devices may be deployed in public places, making them vulnerable to physical attacks and replication attacks. Therefore, IoT devices are required to provide a solid security against duplication and counterfeiting even with these restrictions. To solve this problem, we propose a low-power physical unclonable function (PUF) for IoTs. The proposed low-power PUF at 0.5 V supply voltage (in near-threshold voltage region) achieves an energy efficiency of 36.7 pJ/b by lowering the bias voltage extremely and operates stably from −20°C to 60°C. In this paper, PUF for low-power IoTs is implemented in a 28-nm CMOS process and occupies 10801μm2 area.

As a newly emerging energy source, a triboelectric nanogenerator (TENG) was introduced in 2012, and various types of energy harvesters and active sensors based on the TENG have since been developed. Although research in the material-engineering field is actively conducted, there is not much research on TENG energy-harvesting circuits in the integrated-circuits field. From the viewpoint of material engineering, much research focuses on the applications and the analysis of instantaneous power. However, topics such as rms maximum power point (MPP), spice modeling, and impedance matching are more important from the circuit designer's viewpoint. This paper presents a TENG energy-harvesting circuit designed as a high-voltage (HV) dual-input (DI) buck converter with MPP tracking (MPPT) based on the proposed MPP analysis for the TENG.

Low-power operation is essential for emerging fields in the circuit design such as Internet of Things(IoT) and Biomedical applications. Since the supply voltage is a major factor that affects the total power consumption, design in Near-Threshold Voltage(NTV) region which is known to have the advantages of both power-saving and well-performance can be an effective way to overcome the constraints. This paper presents an ADPLL(All-Digital Phase-Locked Loop) operating in NTV region. Bootstrapped ring oscillator(BTRO) is used for the PVT tolerance of the Digitally Controlled Oscillator(DCO) and Low-Dropout Regulator(LDO) is adopted for the optimal control of the supply voltage. This ADPLL operates at 480MHz with a power consumption of 152uW under a supply voltage of 0.55V.

An energy efficient State-of-Charge (SOC) indication algorithm and integrated system for small IoT batteries are introduced in this paper. The system is implemented in a 180-nm CMOS technology. Based on a key finding that small Li-ion batteries exhibit a linear dependence between battery voltage and load current, we propose an instantaneous linear extrapolation (ILE) algorithm and circuit allowing on-demand estimation of SOC. Power consumption is 42nW and maximum SOC indication error is 1.7%.

A point-to-point interface with a clock embedded scheme (CES) in Fig. 29.5.1 is generally adopted in an intra-panel interface due to the poor signal integrity of the multi-drop topology, data and clock channel skews and EMI emission from the forwarded clock signal channels. Clock recovery in RX without a reference clock channel is usually carried out using one of two type of data encoding schemes, embedded clock with dummy clock bits [1–2,5] or ensured transition density with data encoding such as 8B10B encoding [3]. However, these two schemes reduce the effective bandwidth because they require over 20% overhead in the data stream. Although highly efficient signaling schemes have been introduced recently in the literature [4] to cope with the physical limitations of the process and channel, it is difficult to adopt these multi-level signaling schemes in intra-panel interfaces where there is a highly resistive channel of Chip-On-Glass and a ground bouncing problem [5] due to different voltage domains (1V and 8V–30V) for serial link and source drivers. This paper introduces a braid clock signaling (BCS) scheme which has the following advantages: 1) clock information without redundant bits; 2) NRZ signal levels for high voltage margin; and 3) low EMI emission with a random data dependent encoding and a spread transition scheme.

Digital LDO (low-dropout) which has 0.45V V out and a good PSR characteristic is presented for NTV operation block. It consists of comparator, counter, power switch array, and proposed adaptive VSS driver. The proposed power MOSFET driver is composed with one inverter and two additional transistors and it leads 14dB PSR improvement for overall frequency range. Minimum resolution is 1mV at 400kHz and the peak current efficiency is 99%.

This paper presents an Rx only equalization (ROE) technique that eliminates all Tx equalizations to reduce power dissipation, circuit complexity, and cost. The proposed Rx consists of a CTLE, a 1-tap speculative FIR and 2-tap direct IIR DFE. A simpler Tx architecture owing to the ROE facilitates a wide bandwidth and energy efficient dual-mode (differential and single-ended) Tx operation. The proposed Tx consists of dual-mode 2∶1 serializer/pre-drivers and main drivers. The transceiver was fabricated in a 65 nm CMOS technology. The Rx achieves BER < 10−12 over a −22 dB loss PCB channel at 32 Gb/s with 0.62 pJ/b energy efficiency, and occupies 0.024 mm2. The Tx has only 0.77 pJ/b and 0.40 pJ/b energy efficiency at 32 Gb/s in differential mode, and 32 Gb/s/pin in single-ended mode, respectively, and occupies only 0.002 mm2.

This paper presents a new energy-efficient ring oscillator collapse-based comparator, which is demonstrated in a 15-bit SAR ADC. The comparator automatically adjusts comparison energy according to its input difference without any control, eliminating unnecessary energy spent on coarse comparisons. The employed SAR ADC supplements a 10-bit differential main CDAC with a 5-bit common-mode CDAC. This offers an additional 5 bits of resolution with common mode to differential gain tuning that improves linearity by reducing the effect of switch parasitic capacitance. A test chip fabricated in 40nm CMOS shows 74.12 dB SNDR and 173.4 dB FOMs. The comparator consumes 104 nW with the full ADC consuming 1.17 µW.

Graphics and high-performance computing systems demand high bandwidth. In graphics systems, the resolution of handheld and desktop systems keeps increasing and emerging visual reality systems will push requirements even higher. High performance computing is benefitting from GPU-acceleration as long as the bandwidth requirements of the GPU are fulfilled.

This paper presents several circuit design techniques for multimedia wireline interfaces. A 7.5 Gb/s transceiver with pre-emphasis and bandwidth (BW)-shifting techniques are introduced. By applying dynamic calibration technique for pre-emphasis, the measured transmitter eye-opening is improved by 24 %. BW shifting clock generator achieves the jitter reduction of 43%. In addition, a wide input range comparator for 11.2 Gb/s low-voltage-differential-swing (LVDS) multi-channel receiver is also introduced. The comparator achieves 81.9 % of the received data RMS jitter reduction for the LVDS receiver.

Memory continues to be a critical element in the full range of VLSI applications from big data to mobile applications to wearable devices. Recent trends, including process technology scaling limits, new memory applications, and evolving high-performance and low-power requirements, have driven the development of emerging memories. As both discrete and embedded memory scaling becomes ever more challenging, there is a widespread effort to look for alternative memory technologies to replace the entrenched SRAM, DRAM, or Flash. This forum brings together systems designers to discuss memory needs for future applications and memory designers to describe the latest developments in emerging and next generation memories. The first three speakers summarize memory requirements from a system perspective to cover a broad range of applications, including servers, data-centric computing, clients, notebooks, tablets, watches, glasses, and thermostats. The fourth speaker describes general design challenges for emerging memory in embedded systems to bridge to the second half of the program, which considers specific memory technologies. Two speakers will then present the challenges and solutions for Flash and DRAM scaling while the last two speakers will highlight the latest developments in MRAM and RRAM.

The demand for high-bandwidth memories is increasing with an increase in the need for high-performance systems. Wide-I/O memory and GDDR5 are two types of high-bandwidth memories. GDDR5 is more compatible than wide I/O for contemporary systems, such as graphics cards and game consoles. The datarate of GDDR5 has reached 7Gb/s/pin. However, the power consumption and cost have increased owing to high-performance-oriented designs, die penalties, and additional test costs. DDR4 is an alternative low-cost memory with high performance in the range of 2.4 to 3.2Gb/s/pin [1]. However it is difficult for DDR4 DRAM to raise the 3.2Gb/s/pin bin portion to lower the cost. In DRAMs, the standby power and self-refresh power are more important than the operating power because DRAMs are mainly in the standby or self-refresh mode in systems. As the operating speed increases, the data window is narrowed, and the jitter increases. Therefore, a duty-cycle corrector (DCC) is employed to increase the data window when the external clock duty cycle is distorted in GDDR5 [2]. The bang-bang jitter caused by the DCC is inevitable even if the external clock duty ratio is exactly 50%. Sometimes the DCC may distort the data window because of an internal DCC offset. This paper presents a GDDR5M (mainstream) memory for graphics cards and a small-outline dual-inline memory module (SO-DIMM). The standby power is managed by the auto-sync mode. Additionally, the architecture of GDDR5M is similar to that of DDR4, and not GDDR5. The error-adaptive DCC can remove the initial duty-cycle offset automatically and remove the bang-bang jitter when the duty cycle of the external clock is not distorted.

System power consumption will drive the architecture of future computing systems. From cloud-connected smart phones to the first exaFLOP supercomputers, systems that are the best at managing and minimizing power consumption will hold a key competitive advantage. At the same time, wireline communication bandwidth requirements within these systems will continue to grow exponentially, driving per-lane data rates beyond 25Gb/s and aggregate bandwidth past 1Tb/s while demanding dramatically improved energy efficiency. The objective of this Forum is to provide an overview of ultra-efficient parallel and serial interfaces, advanced memory applications, dense and high-speed optical communication, and platform-driven wired I/O for mobile. The Forum begins with two talks describing how innovative packaging and form factors along with co-design of I/O circuits and interconnects can improve the power/performance tradeoff by more than an order of magnitude. The next two talks address how memory I/O is adapting to meet the aggressive bandwidth and power requirements for systems ranging from cell phones to supercomputers. The next talk explores how to design serial I/O specifically for mobile products, including low-power equalization and clocking and low-latency standby states. The following talk also focuses on energy-efficient clocking and equalization, but explores analog and digital design options for very high-speed link standards. The final two talks highlight recent advances in both discrete and integrated optical transceivers and the power, performance, density and cost benefits for optical in high-performance computing systems.

This paper presents a boost converter with the maximum power point tracking (MPPT) technique for thermoelectric energy harvesting (EH) applications. The technique realizes variation tolerance by adjusting the switching frequency fSW of the converter. A finely controlled zero-current switching (ZCS) scheme together with the accurate MPPT technique enhances the overall efficiency (η) of the converter because of an optimal turn-on time generated by a one-shot pulse generator that is proposed. Moreover, the ZCS technique can deal with low and high temperature differences applied to the thermoelectric generator. Experimentally, the converter implemented in a 0.35 um BCDMOS process had a peak of 72% at the input voltage VIN of 500mV while supplying a 5.62V output.

This paper describes a time-limited power distribution control (TPDC) technique that can be used for single-inductor multiple-output (SIMO) DC-DC converter with many unbalanced loads. Furthermore, the true all-comparator control technique that raises no stability or complexity issues is proposed. This all-comparator technique for SIMO converters is realized only with a single shared hysteresis comparator at a constant switching frequency of 800 kHz. The maximum efficiency reaches 92%. The fabricated chip with 8-channel outputs occupies 2.4×2.1 mm2 in a 0.35-um CMOS process.

In this paper, we propose a robust transceiver design for MIMO interfering broadcast channels taking imperfect channel knowledge at each base station into consideration. By considering the worst-case transceiver design which maximizes the minimum signal-to-interference-plus-noise ratio (SINR), the proposed design can provide better sum rate and worst user rate performance compared to the conventional schemes. From simulation results, we show the resilience of the proposed design against imperfect channel knowledge.

This paper presents a low-voltage high-efficiency voltage doubler for thermoelectric energy harvesting. A negative charge pump is used to reduce on-resistance of PMOSFET load switches. Additional circuitry for achieving high efficiency just requires small chip-area and low-cost. The voltage doubler is implemented in 0.13-μm 1.2V CMOS process. The proposed doubler improves the low-voltage power efficiency by 17%, compared to conventional voltage doublers. Moreover, the proposed doubler can support wider load range. The maximum power efficiency reaches 52% at the input voltage of 0.2V.

DRAM speed already reaches 7Gb/s/pin for GDDR interface [1,4]. As the bit rate increases, jitter of PLL, data-sampling margin, crosstalk and intersymbol interference (ISI) needs considerable management [1,3,5]. Moreover, as the supply voltage decreases, the self-generated internal noise of DRAM increases due to low efficiency of the internal voltage generator, especially the VPP voltage generator [2]. In general, the sensitivity of PLL to supply noise gives rise to large jitter accumulation. If the supply noise frequency is close to the PLL bandwidth, more jitter peaking occurs. Therefore, the PLL bandwidth is an important parameter to achieve low jitter performance [3]. Crosstalk becomes a crucial issue for over 7Gb/s GDDR interface [1]. However, the complexity of the transmitter and the CIO, capacitance of I/O, increase due to additional equalizers and pre- and de-emphasis drivers. For a compact transmitter, a low-overhead boosted transmitter is developed [4]. This paper presents an adaptive-bandwidth PLL in response to the supply and channel noises, a fast pre-charged data sampler without an additional decision-feedback equalizer (DFE), a crosstalk-induced-jitter-reduction technique and a compact transmitter with pre- and de-emphasis.

This paper presents a regulated charge pump (CP) with an integrated optimum power point tracking (OPPT) algorithm designed for indoor solar energy harvesting. The proposed OPPT circuit does not require a current sensor that consumes power proportionally to the load. The solar cell voltage is regulated at the optimum power point; the CP output is regulated according to the target voltage. The controller of the OPPT circuit and CP dissipates only 450nW, so the proposed technique is appropriate for indoor solar energy harvesting applications under dim lighting conditions.

A 7.5Gb/s referenceless transceiver for the ultra-high definition television is designed in a 0.13μm CMOS process. By applying the dynamic pre-emphasis calibration and the bandwidth scanning clock generators, measured eye opening and jitter of the clock are enhanced by 39.6% and 40%, respectively. Also the data-width comparison based adaptive equalizer with self-adjusting reference voltage is proposed.

A time-to-digital converter (TDC)-based skew compensation technique is proposed to minimize timing skew between main and pre-emphasis signals of high-speed current mode output driver. Skew between signals of main and pre-emphasis branches of output driver increases jitter. The proposed technique measures and compensates the timing skew to reduce the jitter in the output data. With the compensation technique, maximum jitter reduction achieved is as high as 49%. The power overhead for the compensation block is only 7% of the total power consumption. The output driver with the proposed compensation technique is designed using 110 nm CMOS process technology.

An adaptive equalizer that operates at 5.4Gb/s with unit pulse charging technique is introduced in this paper. The proposed method has a simple architecture with compensating the channel adaptively. The common mode detection of the equalizer filter output with the resister ladder that can generate the reference voltages depending on the common level of the output of the filter is presented as well. The eye opening of the equalizer at 5.4Gb/s is 0.61UI with a 2m DisplayPort cable, and the BER is less than 10−12 at the same conditions. The power consumption is 17.64mW, and our equalizer occupies a core area of 0.069mm2 using 0.13µm CMOS process.

A spread-spectrum clock generator (SSCG) is a cost-effective solution to reduce EMI, which has become a serious problem in high-speed systems. In applications such as serial links, display drivers and consumer electronics, SSCG is essential or strongly recommended. Control options such as frequency deviation (δ) and modulation frequency (f m ) help to satisfy these demands. Furthermore, efficient modulation-profile generation is critical for achieving further EMI reduction and lowering fabrication cost. PLL-based SSCGs are reported in [1–3]. The ΔΣ modulator (ΔΣM) controls the division ratio [1,2] and the phase information of phase detector (PD) [3] to generate a spread-spectrum clock. The self-referenced clock generator uses a capacitor array to generate a spread-spectrum clock [7]. However, they do not have a way to control δ and f m . Dual-loop direct VCO modulation [4] and digital period synthesizer with delay-line [5] are able to control δ and f m . However, [4] requires an additional VCO, which increases the power consumption by 2×, and [5] suffers from a large deterministic jitter through the delay-line and logic circuits. A triangular profile is commonly used in many SSCGs [1,3,4]. Though the implementation of a triangular profile is very simple, its performance is poor. The chaotic PAM modulation in [2] requires complex analog circuits. Recently, a piecewise-linear profile with SRAM was presented in [5]. However, the additional memory consumes a large amount of power and occupies a large area. This paper presents a frequency-locked loop (FLL) based SSCG with frequency-to-voltage converter (FVC) [6], that saves area and provides multiple δ with low bandwidth variation. A memoryless Newton-Raphson modulation profile with multiple f m is also described.

A compact soft-start technique, with an internal circuitry, is presented for the start-up of current mode DC-DC converters for biomedical applications. Examples of medical applications in DC-DC converters include bio-patch, wireless medical sensor node, RFID applications and medical instruments that must have a high stability. To achieve this, a soft-start circuit is proposed to prevent inrush current and output voltage overshoot, during the start-up of the current mode DC-DC converters. The output of the error amplifier is controlled by a stair-case waveform signal generator during the start-up period. The proposed soft-start circuit is fully integrated on chip for portable and wireless medical devices, so that the external components are not required, leading to a reduction in the PCB space and cost. The new soft-start circuit which is digitally-controlled unlike conventional ones was fabricated in a CMOS 0.35-µm process and occupies an active area of 0.19 mm2 with a 3.3 V supply voltage.

An all digital time amplifier (TA) is proposed in 0.13 μm CMOS process. The TA is based on quantization scheme; hence it guarantees large input range. An interpolation scheme is employed to achieve more than 2 times reduction in gain variation of the TA over the input range. The all digital TA is portable to other process technology with smaller design effort. The TA shows a gain variation of less than 5% and consumes a power of 14 mW.

A multi-port serial link with a wide-range CDR using digital Vernier phase shifting and dual mode control is presented. The proposed Vernier phase shifter generates fine-resolution phase steps and provides unlimited phase rotating. With the dual mode control, the proposed CDR extends the operating range from 250Mbps to 5Gbps. The proposed CDR provides 13.34ps phase steps at 5Gbps and achieves a BER of less than 10−12 for the range of 250Mbps to 5Gbps. Fabricated in a 0.13-μm CMOS process, the proposed CDR dissipates 19.2mW at 5Gbps from a 1.2-V supply.

This paper provides a tutorial review of spread spectrum clock generators (SSCG). After explaining the various EMI reduction techniques, SSCGs which reduce EMI with frequency modulation are presented. The frequency modulation method and its implementation are also introduced. A low-cost SSCG design method that does not sacrifice EMI reduction is presented. The paper concludes with future trends of SSCGs.

A 7.7mW/1.0ns/1.35V digital delay locked loop has been proposed in this paper. The dual-DLL architecture with racing operation is adopted to achieve low power operation and low jitter, which is primarily caused by the length of the delay line. The merged dual coarse delay line (MDCDL) is employed for low power and high frequency operation. This DLL utilizes an OR-AND DCC for wide duty cycle correction capability. The proposed DLL for DDR3 SDRAM is fabricated by a 54nm DRAM process technology. Experimental results show that ±10% duty error of external clock can be corrected in less than 400 cycles locking time with 1.0GHz operation frequency at 1.35V.

This paper presents a cost effective fine-pitch flip chip solution to meet the increasing demand for the high performance small form factor packages. Tape Automated Bonding (TAB)-BGA package utilizes thermo-compression to bond a flip chip onto a film based substrate instead of reflow soldering. This approach allows for fine-pitch connection that can save significant substrate area, which can be especially cost effective for some package designs that can reduce the conductive layer count from 2 to 1 [1]. For second level interconnects, typical BGA approach was taken for easy adoption. Successfully implementing TAB-BGA has several technical challenges. Applying underfill under the fine-pitch flip chip without creating voids can be difficult. One way to overcome this challenge is by using no filler underfill and overmold type flip chip; however, that can potentially lead to high water absorption rate and delamination issues. Furthermore, board level reliability, especially temperature cycle, can have high failure rate for this type of single layer package structure [2]. To overcome these challenges, flexible PI film based substrate has been used to reduce the residual stress within the package. In addition, Epoxy Molding Compound (EMC) with low modulus at high temperature and solder resist stress buffer layer have been applied to improve the package and board level reliability.

The proposed on-die termination (ODT) calibration method is implemented by using a 0.18um CMOS technology. The proposed ODT can detect the impedance variations of each ODT/OCD independently with the help of the proposed local PVT variation sensor and can decrease the impedance mismatch error lower than 1% by calibration of global on-chip variation with small area overhead. The measured eye diagram area at 2Gbps is widened by 26% when the ODT is on. The random data rate used for testing the eye diagram is 2Gbps. The global impedance mismatch error is within 1% under the supply voltage variation from 1.7V to 1.9V. The ODT and its calibration circuit occupy 0.003mm2 and 0.015mm2, respectively. The power consumption of the calibration circuit is 10mW at 2Gbps.