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The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND technology requires addressing several common issues: 1) As the number of WL stack layers increases, the cell-string current is reduced due to the increased resistance in a cell string, 2) Deterioration of cell-to-cell interference, due to the reduction of cell pitch, 3) Support of higher IO bandwidth for faster data transfer speed [1]. Another challenge of this work was to minimize the die size because the peripheral circuit area is comparable to that of the cell array. Hence, we integrated the peripheral circuits below the cell array as introduced in [2]. Also, to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area.

A 1.2 V, 1.8 Gb/s/pin 16Tb-NAND flash memory multi-chip package incorporating with 16-dies of 1-Tb NAND flash memory and the 3rd generation F-Chip is proposed. The proposed F-Chip is developed to meet the performance requirements of high capacity storage devices that adopts PCIe Gen 4 host interface for faster data throughput. It is implemented with Toggle 4.0 standard on dual bi-directional transceiver architecture to achieve maximum valid data window on SSD channels. Also, it facilitates training between F-chip and NAND using on chip DLL and BIST to achieve sufficient signal integrity on in-package channel for 1.8Gb/s/pin. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

3D NAND flash memory has enhanced its areal density by more than 50% per year by virtue of the aggressive development of 3D WL stacking technology for the recent three consecutive years [1]–[3]. Also storage market still requires more bits for diverse digital applications. [4]

Data storage is one of the hottest discussion topics in today’s connected world. The amount of data growth is expected to be exponential, while budget and space remain constricted. Since the transformation of storage device from planar NAND to 3D V-NAND [1], the areal density of semiconductor storage devices has continuously evolved and has surpassed the density of magnetic hard drives. By providing the largest storage capacity in the smallest footprint, 3D V-NAND has been leading the data center revolution in recent years. However, 3D-technology scaling faces several technical challenges [2]. (1) As the number of WL stacks increases the channel-hole etch process becomes a limit, since the total WL-mold height increases. (2) Interference between cells increases since the distance between WLs becomes smaller. (3) Faster data transfer speeds are required to support higher IO bandwidth.

Since the first demonstration of a production quality three-dimensional (3D) stacked-word-line NAND Flash memory [1], the 3b/cell 3D NAND Flash memory has seen areal density increases of more than 50% per year due to the aggressive development of 3D-wordline-stacking technology. This trend has been consistent for the last three consecutive years [2-4], however the storage market still requires higher density for diverse digital applications. A 4b/cell technology is one promising solution to increase bit density [5]. In this paper, we propose a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput. The chip achieves a 5.63Gb/mm2 areal density, which is a 41.5% improvement as compared to a 3b/cell NAND Flash memory in the same 3D-NAND technology [4].

A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.

NAND flash memory is widely used as a cost-effective storage with high performance [1–2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640µs program time and a 800MB/s I/O rate is achieved.

NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the accelerating performance growth of SSDs due to the host bandwidth limit. A PCI Express (PCIe) has emerged to close the limit because it can deliver 1GB/s throughput per lane and can be scaled to multi-lane to improve bandwidth [1]. Accordingly, the SSD performance bottleneck has moved from the host interface to the NAND flash interface. In a memory system, a die-stacking technology in a NAND flash multi-chip package (MCP) effectively increases capacity and throughput performance in terms of PCB complexities and power consumption compared to a method increasing the number of channels. However, the multi-drop bus topology on NAND interfaces severely affects I/O speed degradations due to channel reflections and inter-symbol interference (ISI) resulting from large capacitive loadings [2]. The undeniable paradox between larger storage capacity and higher I/O bandwidth has become a key challenge to reach enterprise-class SSDs. To overcome this issue, this paper presents a frequency-boosting interface chip (F-Chip) to boost I/O speeds while meeting capacity requirements. A 2Tb NAND flash MCP with 1GB/s toggle DDR interface is accomplished by incorporating the F-Chip into the NAND MCP including a 16-die stacked 128Gb NAND flash [3].

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

In this work, we present a 3D 128Gb 2bit/cell vertical-AND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications. Also, extended endurance of 35K is achieved with 36MB/s of write throughput for data center and enterprise SSD applications. And 2nd generation of 3D V-NAND opens up a whole new world at SSD endurance, density and battery life for portables.

This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write cycle and reduced signal paths. Furthermore, two-MAT-cell-array architecture is used for 2times read/write operations. Various techniques are used to suppress noisy effects such as common source line (CSL) noise and floating-gate-coupling noise

An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.

A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at

A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.

A 1.8 V 2 Gb NAND flash memory is fabricated in a 90 nm process resulting in a 141 mm/sup 2/ die and a 0.044 /spl mu/m/sup 2/ effective cell. To achieve the high level of integration, critical layers are patterned with KF photolithography and phase-shift masks with proximity correction.

A new lateral dual channel emitter switched thyristor employing segmented p-base, entitled the lateral SB-DCEST, is proposed in order to eliminate the snap-back and to decrease the forward voltage drop. The forward I-V characteristics of the fabricated lateral SB-DCEST show that the snap-back problem is almost eliminated and a lower forward voltage drop by 1 V is obtained when compared with the conventional lateral DCEST due to the enhanced thyristor operation.

The high temperature characteristics of a BRT (Base Resistance controlled Thyristor) and a DCEST (Dual-Channel Emitter Switched Thyristor) were measured and compared. At the current density of 200 A/cm/sup 2/, the forward voltage drop of the BRT is 1.50 V at 25/spl deg/C, 1.45 V at 75/spl deg/C and 1.41 V at 125/spl deg/C, while that of the DCEST is 2.67 V at 25/spl deg/C, 2.79 V at 75/spl deg/C and 3.27 V at 125/spl deg/C. The BRT had the lower forward voltage drop than the DCEST and the DCEST had a negative feedback of the temperature. Both devices were fabricated using an IGBT-like process sequences and their forward I-V characteristics were measured under the ambient temperature range from 25/spl deg/C to 125/spl deg/C.

The SOI separated shorted-anode LIGBT (SSA-LIGBT) has been investigated by experiments and numerical device simulations. In order to suppresses the negative differential resistance regime which is the inherent drawback of the shorted anode LIGBT (SA-LIGBT), the SSA-LIGBT increases the pinch resistance by employing the highly resistive n-drift region as an electron conduction path. The SSA-LIGBT shows a remarkably decreased on-state voltage drop when compared with the conventional SA-LIGBT and shows a one-order faster turn-off time than that of the LIGBT.