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Time dependent dielectric breakdown (TDDB) reliability is studied on interfacial layer (IL)/high-K gate stack of Gate-All-Around Nanosheet (GAA-NS) N- and P-type Field Effect Transistors (FETs) with volume-less multiple threshold voltage (multi-Vt) integration scheme enabled by the dual dipoles (n-dipole and p-dipole). We report for the first time Key TDDB Modeling parameters: voltage acceleration exponent (VAE), Weibull slope ( $\beta$ ), and activation energy (E a ) and show robust TDDB reliability in multi-Vt NS transistors enabled by different dipoles.

Ultra-fast (Iuus delay) measured threshold voltage shift (ΔV T ) due to Negative Bias Temperature Instability (NBTI) in Gate All Around Stacked Nano-Sheet (GAA-SNS) Field Effect Transistors (FETs) having various length (L) and width (W) are analyzed. An enhanced, fully physical BTI Analysis Tool (BAT) is used to model the measured ΔVT stress-recovery kinetics at multiple stress bias (V GSTR ) and temperature (T), with only four process dependent parameters. The impact of L and W scaling on ΔVT magnitude and its Voltage Acceleration Factor (VAF) is explained by considering variation in mechanical stress.

The design of navigation observers able to simultaneously estimate the position, linear velocity and orientation of a vehicle in a three-dimensional space is crucial in many robotics and aerospace applications. This problem was mainly dealt with using the extended Kalman filter and its variants which proved to be instrumental in many practical applications. Although practically efficient, the lack of strong stability guarantees of these algorithms motivated the emergence of a new class of geometric navigation observers relying on Riemannian geometry tools, leading to provable strong stability properties. The objective of this brief tutorial is to provide an overview of the existing estimation schemes, as well as some recently developed geometric nonlinear observers, for autonomous navigation systems relying on inertial measurement unit (IMU) and landmark measurements., 8 pages, accepted by the IEEE 59th Conference on Decision and Control (CDC 2020)

Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si 1-x Ge x channel have been fabricated to explore their electrical benefits. The Si 1-x Ge x NS channel structure with high crystalline quality and 1GPa compressive stress has been realized for the first time. Systematic study has been performed to understand the effect of epitaxial Si 1-x Ge x thickness, Ge fraction, and Si cap thickness on the Si 1-x Ge x NS channel device characteristics. It is found that the compressively strained Si 1-x Ge x NS channel provides a 100% uplift in peak hole mobility with a corresponding channel resistance reduction of 40% while maintaining an excellent subthreshold slope of below 70 mV/dec.

We investigate multiphonon-electron coupling enhanced defect generation process and breakdown (BD) in middle-of-line (MOL) spacer dielectrics (Si 3 N 4 , SiBCN, and SiOCN). Rather than traditional Poole-Frenkel process, we report inelastic multiphonon assisted tunneling plays a key role in conduction process in these defective dielectrics in both initial and post-stress electron conduction. More importantly, we demonstrate defect generation process follows a universal process independent of thickness among these seemingly very different dielectrics. We show multiphonon-electron coupling is responsible for the enhanced defect generation rate due to high-energy electrons at the anode, thus triggering to specie-release induced BD.

In order to implement high precision PSF reconstruction and centroid positioning accuracy of star sensors, the reconstruction accuracy evaluation method of ePSF model is studied. Firstly, the reconstruction accuracy evaluation method of ePSF model is introduced, and propose the model error and ePSF correlation coefficient as evaluation indicators. Then, the variation of model error and ePSF correlation coefficient in the reconstruction process and the correlation with centroid accuracy are analyzed through simulation. Finally, an experiment is designed to analyze the application of the reconstruction accuracy evaluation method of ePSF model and the correlation between the reconstruction accuracy evaluation indicator and centroid accuracy. It could be conclude that the model error and ePSF correlation coefficient are effective as the evaluation indicators of reconstruction accuracy and accurately reflect the change of centroid accuracy from the simulation and experimental results.

We report an improved air spacer that is successfully co-integrated on FinFET transistors with Self-Aligned Contacts (SAC) and Contacts Over Active Gate (COAG). The new integration scheme enables air spacer formation agnostic to the underlying transistor architecture, thus paving the way for a seamless adoption of air spacer in FinFET and Gate-All-Around (GAA) technologies. A reduction in effective capacitance $(C_{\mathrm{eff}})$ by 15% is experimentally demonstrated. The power/performance benefits achieved by the new air spacer exceeds the benefits of scaling FinFET from 7nm node to 5nm node.

We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.

For stacked Nanosheet gate-all-around transistors, a new failure mode between the gate and epitaxial source/drain (PC-Epi) is introduced in the Middle-Of-Line (MOL) intermetal dielectrics (IMD) because of a unique module called inner spacer. In this work, we demonstrate a novel integration scheme for evaluating the inner spacer reliability by completely oxidizing the Si channel. The inner spacer TDDB reliability is also shown to be robust, which is essential to support the continuous aggressive device scaling.

An ultrafast (10ps delay) characterization method is used to measure threshold voltage shift (ΔV T ) owing to Bias Temperature Instability (BTI) and Hot Carrier Degradation (HCD) stress in N and P channel Gate All Around (GAA) NSFETs. ΔV T time kinetics at various gate bias (V G ) and temperature (T) for BTI and at various VG and drain bias (V D ) for HCD is analyzed. Contribution from Self Heat Effect (SHE) induced BTI to overall HCD is estimated under full V G /V D space and pure HCD contribution is determined.

This paper considers the problem of attitude, position and linear velocity estimation for rigid body systems, relying on an inertial measurement unit (IMU) and a stereo vision system. We provide a generic stability result for a class of nonlinear time-varying systems evolving on SO(3)×Rn, which is used for the development of two nonlinear observers, guaranteeing almost global asymptotic stability and local exponential stability, for autonomous systems evolving in a 3-dimensional space. The first observer considers stereo bearing measurements of a single landmark, while the second one uses stereo bearing measurements of multiple landmarks. Two numerical examples are provided to illustrate the performance of the proposed observers.

In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

This paper presents a new hybrid feedback design strategy for the attitude tracking problem on SO(3) guaranteeing global asymptotic stability. The proposed hybrid controller is derived from a modified potential function on SO(3)×ℝ involving a virtual state variable with hybrid flow and jump dynamics. We propose a new resetting mechanism that keeps the state away from the undesired critical points while, at the same time, guaranteeing a decrease of the potential function. A systematic design of the instrumental potential function is provided. Numerical results are presented to illustrate the performance of the proposed hybrid controller.

In this work, we investigate the statistical evolution from nano-conducting path generation to the switching-filament formation in ReRAM devices. We demonstrate the Gumbel statistics, a maxima-value distribution for switching-filament conductance as opposed to the minima-value Weibull model. In contrast to Poisson distribution for nano-path generation, we show the underlying spatial statistics is controlled by a binomial distribution as a result of filament-formation. The reorganization and conglomeration of interacting nano-paths or individual vacancies eventually leads to area-dependent single-filament formation, consistent with the Gumbel statistics. Our methodology provides the foundation for RRAM scaling as well as an essential tool for the development of RRAM technology.

For a linear system with multiple controllers, the problem of stabilization is addressed by means of bumpless transfer input and periodic switching. The main idea is to design open-loop input signals that compensate the discontinuities caused by controller switching. With periodic switching laws, the system state is proved to be bounded and convergent. A computational procedure is proposed for calculating the compensator. A numerical example is shown to verify the effectiveness of the proposal scheme.

Breakdown and bias temperature instability for n/pFETs are studied on a wide composition of SiGe channels on different strain relaxation buffers. This study represents the first in-depth look at AC/DC PBTI trends of low Ge% SiGe nFinFETs. Dielectric breakdown is shown to be largely independent of channel composition over the region studied. Finally, we calculate the end-of-life performance benefit compared to Si, demonstrating the potential benefit of CMOS SiGe as a technology element.

In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which reduces parasitic capacitance, leakage and performance variation. In addition, we demonstrate that CT-in-RMG is a promising alternative integration process that can enable scaling for future logic technology nodes. Device, circuit and reliability results are shown to compare this novel CT-in-RMG process to the conventional gate cut method.

In this paper, we report the bias temperature instability (BTI) reliability in stacked gate-all-around (GAA) nanosheet (NS) devices. We show that, in addition to its superior intrinsic performance over FinFET and stacked nanowire (NW), stacked NS can also provide NBTI reliability benefit, owing to domination of (100) surface conduction and mitigation of field enhancement effect in ultra-scaled GAA structure.

The impact of channel Germanium content (Ge%) and gate stack Nitrogen content (N%), on bulk trap generation $(\Delta \text{V}_{\text{oT}})$ time kinetics is studied by using DC and AC stress at different voltage $(\text{V}_{\text{GSTR}})$ and temperature (T) in RMG HKMG Si and SiGe p-FinFETs. It is shown that $\Delta \text{V}_{\text{OT}}$ magnitude is dependent on frequency $(f)$ , which can make the resulting threshold voltage shift $(\Delta \text{V}_{\text{T}})$ dependent on $f$ for some stress conditions. The $f$ dependence of $\Delta \text{V}_{\text{OT}}$ and $\Delta \text{V}_{\text{T}}$ becomes stronger at higher Ge% and weaker at higher N%. The $\Delta \text{V}_{\text{T}}$ time kinetics is modeled for DC and AC stress under different stress conditions (V GSTR , T and $f)$ and for different processes (Ge%, N%).

Time dependent dielectric breakdown (TDDB) properties of cobalt and ruthenium interconnects were investigated in 36 nm pitch dual damascene test vehicles. We demonstrate that cobalt and ruthenium interconnects with significantly scaled barrier/adhesion layers can achieve comparable TDDB reliability to the Cu standard. This study suggests the properties of low-k dielectrics will gate the maximum supported electric field Emax for these material systems.

This paper considers the Simultaneous Localization and Mapping (SLAM) problem for a rigid body evolving in 3D space. We propose a nonlinear geometric observer, designed on the matrix Lie group SE 1+ n (3), using group velocity and landmark measurements. The proposed observer is also extended to handle unknown biases in the linear and angular velocity. Simulation results are presented to illustrate the effectiveness of the proposed observer.

This paper considers the problem of orientation, position and linear velocity estimation for a rigid body navigating in 3D space. We propose a globally exponentially stable (GES) nonlinear hybrid observer, designed on the matrix Lie group SE 2 (3), relying on an inertial measurement unit (IMU) and landmark measurements. A rigorous stability analysis has been provided based on the framework of hybrid dynamical systems. Simulation results are presented to illustrate the performance of the proposed hybrid observer.

For the first time, high electron mobility in tensile-strained SiGe channel nFinFETs outperforming Si is reported to explore the feasibility of high performance SiGe CMOS. To examine the electron mobility behaviors in SiGe channel, a series of tensile-strained SiGe nFinFETs are fabricated on various strain relaxed buffer layers by taking into account the minimum threading dislocation density and strain engineering. For SiGe $(\text{Ge} > 20\%)$ nFinFETs, we identify the existence of additional electron trapping site close to the conduction band edge in IL/HK, leading to the abnormal Vt shift, PBTI degradation, and low electron mobility. We also fabricated short-channel SiGe nFinFETs, which exhibit excellent cut-off behavior and electrostatics (SS ∼65mV/dec and DIBL ∼18mV at $\mathrm{V}_{\text{DD}}=0.7\mathrm{V}$ ). In addition, the dynamic performance of tensile-strained SiGe CMOS against Si CMOS is evaluated by TCAD simulation based on experimental data.

We demonstrated more than 3 pairs of threshold voltage (Vt) devices by volume-less multiple Vt (multi-Vt) scheme plus dual work function metals (WFM) without performance and reliability degradation on 20nm gate length FinFET CMOS devices. Vt shifts over 200 mV were achieved for both nFET and pFET. The volume-less nature of this multi-Vt scheme relieves replacement metal gate (RMG) challenges and opens the path to offer multi-Vt solution for future highly scaled technologies.

This paper addresses novel approaches at material and integration fronts for gate applications. Material wise, new n work function metal (WFM) material is explored to address the need for reducing gate resistance and maintaining proper Vt at 20A or less WFM thickness. Integration wise, next generation dipole is tested with various process sequences to address the need in lowering overall thermal budget at the gate level for advanced architectures, such as scaled FinFET and Nanosheets.

The characteristics of Stacked Nanosheet are investigated, focusing on channel geometry. For the first time, “narrow sheet effect” on carrier transport is observed. By comparing measured electron $(\mu_{e})$ and hole $(\mu_{h})$ mobilities, and the n-type/p-type opposite transconductance ( $gm$ ) trends versus sheet width ( $Wsheet$ ), we show that the mobility dependency on $Wsheet$ is attributed to reduced (100) plane conduction contribution as $Wsheet$ shrinks.

Leakage in Si/SiGe CMOS FinFET is examined. Si cap passivation effectively improves SiGe pFET Dit, subthreshold slope, and mobility, which improves pFET DC performance by 20%. SiGe GIDL is higher than Si by a factor of 9, though GIDL is limited to 50pA/um. SiGe GIDL reduction knobs to meet Si counterpart are demonstrated. The results open the door to the next stage of Si/SiGe CMOS FinFET such as low power and low leakage applications.

In this work, we present an experimental method to obtain the location of the pinch-off point in a MOSFET biased in saturation. The proposed methodology, applicable to nanoscale devices, enables lateral profiling of hot-carrier-induced defects directly from measured data without the need of extensive computer simulation or complicated analytical modeling.

In this paper, we report multi-threshold-voltage (multi-Vt) options for stacked Nanosheet gate-all-around (GAA) transistors. V t can be modulated through workfunction metal (WFM) thickness as well as the inter-nanosheet spacing (T sus ), the combination of which may be leveraged to increase the number of undoped V t offerings within a CMOS device menu relative to a FinFET CMOS device menu, which fundamentally does not have T sus as a V t tuning option. Hence we propose our multi-V t scheme by taking advantage of the unique structure of stacked GAA transistor.

This paper deals with the design of globally asymptotically stable invariant observers on the Special Euclidian group SE(3). First, we propose a generic hybrid estimation scheme (depending on a generic potential function) evolving on SE(3) χ R6 for pose (orientation and position) and velocity-bias estimation. Thereafter, the proposed observer is formulated explicitly in terms of inertial vectors and landmark measurements. Interestingly, the proposed globally asymptotically stable estimator, leads to decoupled translational and rotational error dynamics (in the velocity bias-free case), which is an important feature in practical applications with noisy measurements and disturbances.

NBTI in Replacement Metal Gate (RMG) High-K Metal Gate (HKMG) SiGe p-FinFETs is modeled. Time kinetics for DC and AC stress and recovery, temperature (T) dependence of voltage acceleration factor (VAF), and impact of Ge% and N% are quantified. Benchmarking is done with Si p-FinFETs, and process (Ge%, N%) dependence is explained by TCAD and band structure calculations.