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Motivated by the potential of bimodal aerial and surface locomotion as an energy saving strategy for small flying robots, we investigate the effects of a flat overhang surface in the vicinity of a spinning propeller. We employ the classical momentum theory and the blade element method to describe the “ceiling effects” in regards to the generated thrust, power, and rotational speed of the propeller in terms of a normalized distance between the ceiling and the propeller. Validating experiments were performed on a benchtop setup, and the results are in agreement with the proposed models. The presence of a ceiling was found to reduce the power consumption by more than a factor of three for the same thrust force. Overall, our findings show promise, paving the way for the use of perching maneuvers by small rotorcraft to extend their missions.

A CSE (charge storage efficiency) model is proposed to explain the origin of ISPP slope degradation for various charge-trapping NAND Flash devices. Experimentally it is often observed that the programming window is generally degraded as device dimension scales [1], suggesting a strong size effect. Through our model analysis, it is clarified that for a given amount of trapped electron density in the nitride, the programmed Vt shift is gradually reduced with scaled device dimension owing to the increased fringe field effect. The fringe-field effect can be viewed as the increase of effective top-oxide capacitance, leading to the reduced weighting factor of charge storage. We therefore define a CSE value (

We demonstrate a novel vertical channel 3D NAND Flash architecture — SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array decoding method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ∼10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.

Poly-Si thin-film transistor (TFT) is the key building element for high-density 3D NAND Flash memory. Random grain boundary (GB) location and interface traps (Dit) density have been shown as the major root cause of variability [1]. However, with CNL pinned at midgap our previous model cannot adequately address experimental results - especially the cause of very low Vt TFT devices. In this work we point out that to accurately model the TFT device, CNL should not be restricted at the mid-gap only, as in the conventional assumption for Si/SiO2 interface trap, but should be randomly distributed inside the bandgap for GB trap. This makes donor-type Dit active besides the acceptor-type Dit. Simulation including the random CNL can well explain the very low-Vt devices and gives better TFT variability model. Furthermore, GB trap CNL plays an important role in governing the device subthreshold behavior during PE cycling for 3D NAND Flash.

In SONOS 3D NAND, if the string select transistor (SST) and the ground select transistor (GST) use memory cell's trapping dielectric as their gate dielectrics, they could suffer abnormal Vt shift due to unwanted charge injection during programming/erasing (P/E). To solve this, we remove the blocking oxide and the trapping nitride, and use the BE-SONOS' ONO tunneling dielectric and an additional LPCVD oxide as the gate dielectric of SST and GST. The nitride in the ONO tunnel dielectric is thin (

For the first time the programming sequence induced array back-pattern effect is studied in a fully integrated split-page 3D vertical gate (VG) NAND Flash test chip. It is found that when programming of WL's starts from the source side it shows a wider programmed Vt (PV) distribution. It is clarified that when many WL's are programmed in the NAND string, the array loading resistance greatly increases, leading to the Vth shift for the earlier-programmed cells which is called the back-pattern effect. Our model indicates that the major mechanism comes from the decreased virtual drain potential of the selected WL when drain-side other WL's are programmed. In order to overcome the back-pattern effect, we propose a “by-page” programming method, where every page is programmed from drain (BL) side toward source side. It shows great improvements in PV distribution.

This work proposes a novel dual-channel 3D NAND Flash that exhibits both n-channel and p-channel NAND characteristics. The NAND is junction-free without dopant inside the array. Unlike the conventional 3D NAND, the drain side near SSL is N+ doped junction, while source side near GSL is P+ junction. A positive pass-gate read voltage (Vpass, r) induces n-type virtual source/drain for the center WL's, giving an n-channel behavior. On the other hand, a negative Vpass, r induces p-type virtual source/drain, giving the p-channel behavior. Both n- and p-channel reads produce excellent Id-Vg characteristics with very small leakage current. The advantage of this device is that the carrier source of both +FN programming and -FN erasing can be readily provided by either N+ drain or P+ source, respectively, without waiting for the GIDL generated minority carrier for the floating-body 3D NAND. This gives a much faster +/- FN speed than conventional 3D NAND. Moreover, both +FN and -FN can find suitable inhibit method, enabling a novel bit-alterable Flash memory. We have successfully compared, for the first time, two sensing methods (n- and p-channel read) and identified the trapped charge in the space between WL's. This not only provides characterization of charge lateral profile but also a new opportunity to create another storage node (in WL space) inside the array.

A 3D NAND test chip is fabricated to study hot-electron assisted programming. By modifying the local self-boosting method, channel potential is locally boosted, resulting in a large lateral electric field and in turn producing band-to-band tunneling generated hot-electron injection around the selected WL. The hot-electron assisted programming can greatly reduce the maximum programming bias and improve the programming speed. However, hot-electron programming also causes new program disturb modes, and the programming speed depends on the WL location. These are studied in detail.

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BL's (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform C BL 's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

Flash memory endurance is limited by the tunnel oxide degradation after repeated P/E stressing in strong electric field. Thermal annealing should be able to repair the oxide damage but such theory cannot be tested in real time since completed device cannot endure high temperature > 400°C and long baking time is impractical for real time operation. In this work, we propose and demonstrate a novel self-healing Flash, where a locally high temperature (>800°C), short time (ms) annealing is generated by a built-in heater. By modifying the word line (WL) from a single-ended to a double-ended structure, the WL can carry a current to generate Joule heating; and the proximity of the gate can readily heat the tunnel oxide of the Flash device, annealing out the damage caused by P/E cycling. We discover that a BE-SONOS charge-trapping NAND Flash device can be quickly annealed within a few milliseconds. With this novel technique, we demonstrate a record-high endurance of >100M (108) P/E cycles with excellent post-100M-cycle retention. Interestingly, the WL heater can be used to achieve faster erasing although normally FN tunneling should be temperature-independent. At the extreme temperature achieved in our heating-while-erasing experiments electron de-trapping from the charge trapping nitride, accompanying hole FN tunneling, also occurs, resulting in faster erasing. Finally, a novel design architecture for implementing the self-healing Flash memory is proposed.

The variability of the poly silicon thin film transistor (TFT) in 3D NAND Flash is a major concern. In this work, we have fabricated and characterized a 37.5nm half pitch 3D Vertical Gate (VG) NAND Flash, and successfully modeled the random grain boundary effect using TCAD simulation. In our model, the grain boundary creates interface states, resulting in large local band bending and a surface potential barrier. The gate-induced grain barrier lowering (GIGBL) and drain-induced grain barrier lowering (DIGBL) effects are the major physical mechanisms that affect the subthreshold behavior. By means of modeling, the impact of bit line (BL) and word line (WL) critical dimensions (CD) of the double-gate TFT device is studied extensively, where we find that narrower BL and larger WL CD's are the most critical parameters that provide tight Vt distribution and good memory window. For the first time, we have discovered an asymmetry of reverse read (RR) and forward read (FR) of the TFT device. The physical mechanism can be well explained by the DIGBL. With accurate modeling, the asymmetry of RR and FR can be used to determine the GB trap lateral location and interface trap density.

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first < 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL's in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL's are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.

For the first time the WL-WL pass-gate voltage (VPASS) interference for charge-trapping (CT) NAND Flash devices is studied experimentally. Using a 38nm half-pitch BE-SONOS NAND Flash device we find the threshold voltage decreases significantly with increasing VPASS during reading, contrary to the common believe that CT NAND devices are immune to the interference. We clarify that this extraordinary effect becomes significant for the scaled CT NAND Flash, where a lightly doped junction or junction-free device allows the fringing field caused by VPASS to penetrate into the selected cell and affects the inversion electron density. A small S/D junction recess or a non-cut ONO WL profile is suggested to minimize such effect. Moreover, we also find that the programming speed also decreases when a smaller VPASS PGM is applied. Based on our findings we suggest to use low-K spacer material between WL-WL in order to have better short-channel effect, lower interference and larger memory window for further scaling to sub-20 nm node.

As NAND Flash device scales down, the source/drain junction engineering becomes a key factor for improving the short-channel effect, self-boostiSg program inhibit window, and cell reliability. In this work, the impact of trap-layer above junction (cut-ONO or non-cut ONO), Source/Drain Si recess, and junction doping are studied extensively for the 38nm half-pitch BE-SONOS charge-trapping NAND Flash devices. Our results suggest that a non-cut ONO with junction-free device shows the best memory window and small endurance degradation

This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >100K P/E cycling endurance for SLC and >3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN [1,2]. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.

An 8-layer, 75 nm half-pitch, 3D stacked vertical-gate (VG) TFT BE-SONOS NAND Flash array is fabricated and characterized. We propose a buried-channel (n-type well) device to improve the read current of TFT NAND, and it also allows the junction-free structure which is particularly important for 3D stackable devices. Large self-boosting disturb-free memory window (6V) can be obtained in our device, and for the first time the “Z-interference” between adjacent vertical layers is studied. The proposed buried-channel VG NAND allows better X, Y pitch scaling and is a very attractive candidate for ultra high-density 3D stackable NAND Flash.

Various 3D NAND Flash array architectures including P-BiCS, TCAT, VSAT, and VG are critically examined in this work by extensive 3D TCAD simulations. All structures have X,Y lateral scaling limitation since the minimal ONO thickness (∼20 nm) and poly channel thickness (∼10nm) can not be scaled further. Among them VG may have the best X-direction scalability to F∼2X nm node, and no penalty of increasing Z layer number since the channel current flows horizontally. We propose a buried-channel junction-free NAND to improve the read current for all 3D NAND arrays and our simulation results well support this structure. For the first time, “Z-interference” in 3D NAND Flash is examined and it indicates a new Z-direction scaling limitation. The present work is of crucial importance in understanding various 3D NAND Flash approaches.

Although planar floating gate (FG) device using high-K IPD has been proposed, our study indicates that out tunneling through IPD due to the high electric field is inevitable, leading to programming/erasing saturation. Moreover, charge trapping in IPD is a major concern. In this work, we propose a completely different approach - using a trapping IPD for storage. Our concept is to combine the merits of CT and FG - CT for good retention and scaling to few-electron regime and FG for edge effect immunity and faster erase. The planar “fusion” FG/CT devices are fabricated by replacing the conventional IPD ONO of a FG device by a CT BE-SONOS structure. Both simulation and experimental results indicate that most of the stored electrons are trapped inside the SiN trapping layer instead of the FG. The CT storage provides excellent retention even for a very thin tunnel oxide (≪5nm). On the other hand, the thin FG provides an equipotential channel that screens any non-uniform injection effect. Excellent memory window, scalability and reliability are demonstrated.

The interference and fringing field effects beyond sub-30 nm node charge-trapping(CT) NAND Flash are studied critically using 3D simulation. Due to the relatively large EOT (>15 nm) compared to the device dimension (F), the most severe interference comes from adjacent pass-gate WL bias disturb through the edge fringing field effect. On the other hand, the program charges in adjacent devices generate only minor interference effect (

Hot carrier damage, especially by hot holes, limits the reliability performance of nonvolatile memories (NVMs). The damage creates localized traps in the tunnel oxide and localized interface traps at the oxide/silicon interface. In this paper, we propose a novel method to independently quantify trapped charges localized in the oxide and at the interface. We applied the new method to probe the oxide degradation in nitride trapping memory and found (i) the oxide traps (N OT ) capture both electrons and holes, (ii) the retention degradation involves interface trap (N IT ) annealing, electron de-trapping, and hole de-trapping, (iii) upon baking, N IT annealing and electron de-trapping happen simultaneously while hole de-trapping dominates the long-term instability at 250°C, (iv) the V T instability can be improved by using an interface strengthening nitridation process.

The “junction-free” charge-trapping NAND Flash [1,2] is studied extensively. Simulation results show that the junction-free NAND Flash is scalable beyond 15 nm node (half pitch) with reasonable DC characteristics, while the conventional “with-junction” NAND device shows much worse short-channel effect. Simulation results show that lower p-well doping and smaller space (S) between the WL's are two key factors to enable the higher performance of junction-free NAND device. For the first time, we point out that the parameters of the region under the space (S) such as interface traps (Dit), parasitic trapped charge, and local p-well doping have strong impact on cell characteristics. Experimental results on junction-free BE-SONOS device showed some discrepancy with the simulation that may be due to non-ideal factors under the space. Finally, the feasibility of junction-free device on SOI for the future 3D NAND Flash is also examined.

We have successfully fabricated and characterized sub-30 nm and sub-20 nm BE-SONOS NAND flash. Good device characteristics are achieved through two innovative processes: (1) a low-energy tilt-angle STI pocket implantation to suppress the STI corner edge effect, and (2) a drain offset using an additional oxide liner to improve the short-channel effect. The conventional self-boosting program-inhibit and ISPP (incremental step pulse programming) for MLC storage are demonstrated for 20 nm BE-SONOS NAND operation. Read current stability and read disturb life time are also evaluated. The estimated number of storage electrons is only 50-100, and for the first time we have demonstrated successful data retention after 150degC baking in the ldquofew-electronrdquo regime. Our results strongly suggest that BE-SONOS is a promising charge-trapping (CT) technology for NAND Flash scaling.

We have successfully demonstrated a novel junction-free BE-SONOS NAND Flash. Junction-free devices greatly improve the short channel effect and thus promise scaling of NAND Flash below 20 nm node. Instead of S/D junctions a very small space (Lt 30 nm) is left between adjacent devices. Junction is formed only at the outer region of NAND array, while there is no junction inside the array. Fringe field from the gate inverts the Si under the narrow space allowing conduction without a diffusion junction. Successful n-channel, p-channel and TFT BE-SONOS NAND devices are demonstrated using this technique. Simulation results suggest that this novel junction-free technique is scalable beyond 20 nm node. Moreover, the junction-free devices are unaffected by the thermal budget in the 3D TFT devices. This new device can be implemented in the current NAND Flash process without introducing new masks.

The high-Vt state data retention of 2bit/cell SONOS using hot-hole erasing method is studied extensively using a 0.13 mum virtual-ground array NOR-type test chip. We design various trap-layer engineering using multi-layer stacks of SiN and SiON in order to change the intra-nitride conduction. However, our results show that the post-cycled retention is insensitive to the trap-layer engineering. Next, we apply the electrical refill method to test the retention, and find that retention can be improved. Hence our results supports the trap assisted charge loss mechanism. Finally, using a novel bit-by-bit tracking technique, we find that the retention behavior of an individual bit has a random but wide distribution, and some tail bits even show abnormal charge gain. This suggests that both electron and hole de-trapping happen during retention.

Unlike the floating gate Flash device, charge-trapping (CT) devices store charges locally and are thus profoundly affected by non-uniform injection effect. The characteristics of a CT device are dominated by the local minimum-Vt region along the channel width. We have analyzed various STI structures including raised-STI, recessed-STI, and near-planar structures, and found that the program/erase characteristics are strongly impacted by the STI corner geometry due to local field enhancement (FE) and non-uniform injection effects. Moreover, both gm and S.S. vary during program/erase and thus increase programming/erasing complexity. The read disturb, program disturb, and retention characteristics are examined in detail. These conclusions apply to all CT devices.

Reliability properties of bandgap engineered SONOS (BE-SONOS) (Lue et al., 2005) are extensively studied. First, the erase mechanism of BE-SONOS is confirmed as substrate hole tunneling through the ultra-thin ONO tunneling dielectric. Next, very long-term (>3,000 hours) high-temperature baking data (from 150 to 250degC) for various programmed/erased states and cycling history are collected and analyzed for a thorough understanding of the retention property. By transforming retention data (VFB-time) into de-trapping current (J) and modeling its dependence on electric field and temperature, the long-term retention of various programmed states are consistently and accurately predicted. This modeling technique avoids the ambiguity of the common Arrhenius plot, and is useful for developing other predictive models too. We have shown that BE-SONOS surpasses the 10-year 85degC storage criterion for Flash memory applications

The retention degradation mechanism of NBit/NROM (Eitan et al., 2000) is examined by several unique techniques that promise unequivocal results. The in-situ 150degC electrical testing is used to examine the electron/hole stability. We find no discernable electron/hole lateral migration in the nitride. Next, we apply the refill and soft erase methods (Lue et al., 2005) with various electrical conditions to study the charge loss mechanism. We demonstrate that the refill method can electrically modify the trap energy spectrum, and soft erase method can recover the damages induced by hot-hole stressing. The experimental results show that the vertical charge loss measured by Vg-accelerated retention test at 25degC is highly correlated to the charge loss measured at 150degC baking. Since refill and soft erase techniques alter the trapped electron energy spectrum and the excess-hole distribution differently, these correlations strongly support the vertical charge loss model. Finally, the retention is greatly improved by the refill and soft erase methods and further improvement may be expected by engineering the nitride traps