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Trabajo presentado al ISCAS celebrado en Seattle del 18 al 21 de mayo de 2008., Many logic circuit applications of resonant tunneling diodes are based on the MOnostable-BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates. More recently, generalized threshold gates, also suitable to be realized with MOBILE RTD structures, are being investigated. In this paper we propose a novel MOBILE circuit topology obtained by exploiting threshold logic concepts and properties. A comparison in terms of speed and power performance between the proposed topologies and previous reported ones is carried out.

A logic-in-memory structure, in which storage functions are distributed over a logic-circuit plane, is a solution to the communication bottleneck between memory and logic modules, one of the most serious problems in recent deep submicron VLSI systems technology. This logic-in-memory VLSI based on floating-gate MOS transistors merges storage and switching functions in a multiple-valued-input and binary-output combinational logic circuit that is useful for the realization of parallel arithmetic and logic circuits. The paper presents a general structure of a 4-valued-input and binary-output combinational logic circuit. It has two kinds of inputs, external and stored constant inputs. In the logic-in-memory VLSI, a large number of stored data are distributed in not only word-parallel but also in digit parallel manners.

The DSP division of Analog Devices is producing a CMOS, 75ns, 16 bit Arithmetic, Logic, and Shift Unit (ALSU). The ADSP-1200 features a 16-bit wide ALU, three ports, on board barrel shifter in parallel with the ALU, versatile register files, priority encoder and highly fielded instruction set. The device was specifically optimized to efficiently handle algorithms typically found in DSP. The first section of this paper gives an overview of the ADSP-1200. The second section describes the architecture and functionality of the device. Finally, the instruction set is briefly described. The ADSP-1200 shows that high speed CMOS combined with advanced packaging techniques results in effective, producible devices for DSP problems.

Parallel counters are multiple input circuits that count the number of their inputs that are in a given state. In this paper, the implementation of parallel counters with four-valued threshold logic is described and these implementation are compared to their binary full adder network counter equivalents. Since each signal variable in four-valued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over fifty percent savings in the total number of signal variables required to implement the parallel counter results. With the circuits we describe here, fifty percent fewer transistors and resistors are necessary for the implementation of four-valued logic parallel counters.

Application of low-level differential logic will be discussed, citing a bipolar 8 × 8 bit multiplier with a 15-ns multiply time. The device LSI circuit uses either 2's complement or sign-magnitude binary number notation. A digital parallel correlator operating at a 150-MHz data rate has also been developed.

A 1.6μm, 2-level netal, N-well logic array, containing gate array and PLA cells will be reported. The performance and area for a 16b ALU and 16b up-down counter will be compared with a conventional gate array implementation.

A 80K transistor chip, implemented in 2μm CMOS, with a die size of 15×15mm, will be disclosed. A LISP computer assembled with this circuit operates 3X faster than comparable machines.

A complementary logic circuit with Josephson junctions has been investigated theoretically and experimentally. This paper will discuss a circuit with a measured risetime of 100 ps, a power dissipation of 16.4 μW, with the flip-flop operated with a 1500-MHz input signal.

The Esaki diode is a potentially low-cost, high-speed, two-terminal device exhibiting a short-circuit stable, negative resistance over a portion of its volt - ampere characteristic. Under suitable bias and loading conditions, Esaki-diode circuits can perform threshold logic and binary memory functions and can provide power gain when switched. The authors show several appropriately-biased diodes resistively coupled together such that bistable operation is obtained. The three-phase pulse-clock system shown maintains unilateral flow of information and also serves as an unconditional reset of the corresponding logic blocks. Transfer of information occurs during the period of overlap of adjacent clock pulses where the overlap is longer than the propagation time of the information. The propagation time is a function of the reactances associated with the circuit. The inclusion of reactive components in the coupling networks to provide temporary storage of information during switching eliminates the need for overlapping clock pulses. The capabilities of the various types of coupling will be discussed, and some quantitative results will be given in the presentation.

Programmable logic ICs with a complexity of up to 2000 gates will be reported. An input transition detector powers up the circuits and differential logic in the critical speed paths affords a 25ns delay.

A CMOS array providing a maximum of 20,000 logic gates or logic and memory will be described. Typical gate delays of 1.0ns and memory access time of 15ns have been obtained using a 1.5μ twin tub process.

A 2MHz pipelined image processing chip designed with a 5μm NMOS process will be discussed. Multiple ion implant quaternary logic has been found to result in a 4-fold reduction in complexity compared to a conventional binary implementation.

A bipolar LSI linear chip, precisely mated to an in-process laser-trimmed thin-film-on-silicon resistor network, to realize a two-chip 0.003% accurate 12-bit D/A converter in a 24-pin DIP, will be covered.

A two-chip 32b VLSI CPU chip set with a cycle time of less than 200ns, using a 1.3μm double-level metal process will be reported. Chip contains 242K transistors sized at 8.75×11.26mm for an average density of 0.65 square mils per transistor.

This paper will discuss an investigation of the speed power relations of oxide-isolated subnanosecond logic gate circuits (ECL and E2CL) compared with double-diffused circuits. Under optimizing aspects, with respect to propagation delay, data of double-implanted integrated bipolar transistors and circuit performance will be given, dependent on implantation parameters.

This paper will report on a 9K ECL array with a 99.6ps propagation delay. The chip is ECL 10K or 100K compatible, consumes 20W typical and has 256 logic pins plus 64 supply pins.

This paper will cover the design of a CMOS EPROM process that serves to implement a 48 P-term AND-OR array with 16 inputs and 8 outputs. The array requires a 20mA quiescent current and 50mA maximum during switching and can be programmed using a conventional 21V EPROM programmer.

A 24-pin electrically-reprogrammable ASIC, implemented in CMOS EEPROM technology with two-layer polysilicon and two-layer metal, providing user logic complexity of 600-800 gate equivalents, will be described. Speeds of 15ns per internal logic level have been obtained with 50mW consumption.

THIS PAPER presents a critical comparison of the major circuit techniques employing solid-state components to perform the arithmetic functions in digital computers. The presentation is in three sections. The first considers the requirements which are necessary and sufficient to provide a useful circuit technique. The second section discusses an approach to the classification of the various techniques, establishes the evaluation criteria to be used in the final section, and presents illustrative examples in the form of a synthetic chronological development. The third section gives a more detailed survey of the design problems and performance characteristics of a number of techniques.

A 1.3μm gate array whose soft error rate is improved by a factor of 100 over a conventional design will be reported.

The use of 1.5μ CMOS technology to implement a 8000 equivalent gate array with double word line memory addressing on a 9.9×9.8mm2chip will be discussed. Describe, too, will be the implementation and operation of a 16b micro-processor with 1024b ROM and 256b RAM.

Transistor Resistor Locic (TRL) merits consideration as a form of semiconductor logical circuitry for data-processing systems as a consequence of its inherent simplicity, reliability and economy. The basic TRL building block and flip-flop are shown. The building block is seen to consist of a resistor OR gate followed by an inverting transistor amplifier. Any combinational logic function can be implemented using this block alone. The flip-flop consists of two building blocks connected back to back. The TRL circuit has found application in several relatively slow-speed digital systems. It is the purpose of this paper to present the results of a new look at TRL using several new high-speed, high-gain transistors. It is shown that the excellent properties of these transistors can be effectively exploited with TRL circuits operating economically and reliably at the moderately high speeds required in many digital systems. The analysis which follows primarily involves current relationships, since the operation of TRL circuits involves the switching of nearly constant current sources.

A PLA, whose architecture may be electrically programmed, will be described. The device has been built in 1.2μm EEPROM technology and operates at 20MHz with 380mW dissipation. On-chip scan diagnostics are used for testing.

An ECL FPAL with a total delay of 3.6ns at 1.0W will be reported. The chip has 64 product terms with 16 inputs and 8 outputs.

Circuit/device concepts, evolving from MTL/I2L, that improve power delay and speed limits of superintegrated logic, will be discussed. Results from exploratory devices show the feasibility of the approach.

A model that represents errors caused by power supply disturbances as delay faults will be discussed. Experiments reveal that the error susceptibility increases at high clock rates and that metastable states may result.

The degradation delay model is applied to accurately estimate the switching activity in CMOS digital circuits. The model overcomes the limitations of conventional gate-level logic simulators to handle the propagation of glitches, a main source of switching activity. Model results of a four-bit multiplier are within 4% with respect to HSPICE, while Verilog overestimations are up to 68%.

A method is presented for determining the occurrence of the inertial effect (pulse filtering) in CMOS digital logic gates to overcome the limitations of conventional approaches. It is based on accounting for individual input gate thresholds and a new scheduling mechanism, while maintaining compatibility with existing delay models.