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We propose a large-signal model that can simulate the power-added efficiency of p-pocket self-aligned gate GaAs MESFET's. This model includes a new drain current model and a gate bias-dependent RF output resistance to express the drain conductance and its frequency dispersion at each gate bias. In addition, gate-source and gate-drain capacitances are modeled by functions of two variables of gate and drain biases so as to fit the measured values of ion implanted channels. The simulated power-added efficiency agreed with the measured value with a maximum error of 5%. The intermodulation distortion was also simulated and the maximum difference between the simulated and measured results was reduced to one-fifth of the results simulated by the conventional model. Practical applications were demonstrated by the load-pull simulation and the /spl pi//4 shift QPSK-modulated signal simulation.

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

The effect of chip-mounting attachment on the thermal resistance of GaAs power field effect transistor (FET) modules has been experimentally investigated. The thermal resistance was evaluated for different GaAs chip thickness of 150 and 250 /spl mu/m through an electrical method utilizing temperature dependence of Schottky-barrier in the GaAs metal semiconductor FETs (MESFETs). The thermal resistance of low-cost epoxy-mounted GaAs chips, suitable for uniplanar monolithic microwave ICs (MMICs), was found not to increase even up to a chip thickness of 250 /spl mu/m, while that of AuSn-mounted GaAs chips increased as was conventionally expected. Numerical simulation has also been presented for the similar case of GaAs power MMICs. The result of simulation suggests that lower thermal conductivity of attachment material, such as epoxy attachment, leads to larger optimum chip thickness that minimizes the total thermal resistance.

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 /spl Omega//mm for the BP-LD3 structure indicate high potentiality for analog applications.

An ultrahigh-speed 8 bit multiplexer (MUX) has been developed for future-generation optical-fiber communication systems having a data rate of 20 Gb/s. This IC was fabricated using a 0.5 /spl mu/m WN/sub x//W-gate GaAs MESFET process based on optical lithography, ion implantation, and furnace annealing for good reproducibility and high throughput. The WN/sub x//W bilayer gate has a low sheet resistance, improving the circuit high frequency performance. To attain 20 GHz operation, advanced circuit techniques for the source-coupled FET logic (SCFL) were introduced. A cross coupled source-follower (CCSF) was developed mainly for the highest speed buffers to enhance the bandwidth. The first-stage T-type flip-flop was designed with optimization techniques and operated up to 21.1 GHz. >

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

The minimum device isolation distance (L/sub min/) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L/sub min/ is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L/sub min/ at room temperature is 1.3 mu m with a bias voltage of 2 V and an acceptor concentration of 10/sup 15/ cm/sup -3/. L/sub min/ decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V. >

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50- Omega on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5- mu m WN/sub x/-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230 degrees . >

Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WN/sub x/-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (L/sub G/=10, 4, 2, 1, 0.8, 0.5, 0.3 mu m, W/sub G/=20 mu m; W/sub G/-100, 40, 20, 10, 4, 2 mu m, L/sub G/=0.5 mu m). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN/sub x/-gate fabrication process. Injected excess charges at gate length below 0.5 mu m distorts the mobility evaluations. >

Asymmetric tilt-angle-implanted lightly doped drain (LDD)-WN/sub x/-GaAs MESFETs with an optimized transconductance performance are discussed. A tilt-angle implantation is used to reduce the parasitic source resistance below the gate sidewall without increasing short- and narrow-channel effects. This leads to a transconductance increase of nearly 25% for submicrometer FETs while the gate-source capacitance increase is almost negligible. The influence of the implantation angle on the threshold voltage transconductance, and Schottky-barrier characteristics is reported. >

The Schottky barrier of reactively sputtered WN x to p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFET's were fabricated with WN x gates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FET's with 2 µm × 24 µm gates were 0.088 mA/V2, consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.

A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm/spl times/4.73 mm. A basic cell, consisting of one DFET and three EFETs, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitance were 11-ps/fan-in. 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 /spl mu/m/spl times/3 /spl mu/m). An 8/spl times/8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.

Thermal-wave measurements are a very effective tool in the control of the threshold voltage V/sub th/ of GaAs MESFETS with a very thin (100-nm) active layer. A linear correlation is given between the thermal-wave signals and implantation into semi-insulating (SI) undoped LEC-grown GaAs substrates at 50 keV. In addition, the relation between the threshold voltage of GaAs MESFETs fabricated by direct Si/sup +/ implantation at 50 keV and dosage was experimentally obtained. Using these two results, the threshold voltage is easily predicted just after implantation by thermal-wave measurements and adjusted to the desired value by additional implantation. >

1985 IEEE International Solid-State Circuits Conference (ISSCC 85), Thursday, FEB 14, 1985 at Trianon Ballroom, 4:15 p.m.