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The constant growth of social media, unconventional web technologies, mobile applications, and Internet of Things (IoT) devices create challenges for cloud data systems in order to support huge datasets and very high request rates. NoSQL databases, such as Cassandra and HBase, and relational SQL databases with replication, such as Citus/PostgreSQL, have been used to increase horizontal scalability and high availability of data store systems. In this paper, we evaluated three distributed databases on a low-power low-cost cluster of commodity Single-Board Computers (SBC): relational Citus/PostgreSQL and NoSQL databases Cassandra and HBase. The cluster has 15 Raspberry Pi 3 nodes with Docker Swarm orchestration tool for service deployment and ingress load balancing over SBCs. We believe that a low-cost SBC cluster can support cloud serving goals such as scale-out, elasticity, and high availability. Experimental results clearly demonstrated that there is a trade-off between performance and replication, which provides availability and partition tolerance. Besides, both properties are essential in the context of distributed systems with low-power boards. Cassandra attained better results with its consistency levels specified by the client. Both Citus and HBase enable consistency but it penalizes performance as the number of replicas increases. [ABSTRACT FROM AUTHOR]

An artificial intelligence of things (AIoT) chip is a critical hardware component in edge devices that supports data acquisition and processing in the artificial intelligence (AI) era. In this paper, we introduce the architecture and circuit techniques for AIoT systems as well as the design challenges associated with them. To address the design challenges, we describe our design approaches to improve energy efficiency from the standpoints of system architecture, AI computing, and data acquisition circuits. Meanwhile, we present our most recent research progress and state-of-the-art AIoT chip demonstrations at a prestigious conference. Our design techniques improve power and energy efficiency by orders of magnitude on corresponding state of the arts (SOTA), allowing for an advanced AIoT chip design. [ABSTRACT FROM AUTHOR]

Wireless Body Area Network (WBAN) is a wireless network of short-range communication protocols for remote healthcare monitoring with the possibility of giving freedom of human body movements. Sensor nodes (motes) are usually located under the skin, implanted deep in the body, or ingested, as in the rare case of smart pills for medical and non-medical usage. Since the necessary connections of wearable and implantable devices are wireless, and the components use low batteries, processing and transferring the critical data can deplete the nodes' power. In most cases, it is impossible to exchange or re-power batteries. Holter monitoring, loop recorders, and wireless capsule endoscopy are some of the WBAN's applications for saving and transferring medical data. Wireless capsule endoscopy is the application for image transmission in WBANs, and the image compression in common is a specific segment of capsule endoscopy. Since the better compression of images increases the frame rate and typically improves the diagnosis process, selecting the compression algorithm should be relevant. The considerable scope of this comprehensive study pays attention to the various biomedical data compression approaches in WBANs. This paper focuses on power-efficient schemes of remote healthcare networks. In this survey article, the energy-based biomedical data compression approaches of WBANs and remote healthcare networks are accurately classified based on lossy, lossless, and hybrid techniques; later, a comprehensive comparison of each specific method's power consumption is presented. [ABSTRACT FROM AUTHOR]

This paper proposes a modified Schmitt-trigger (ST)-based single-ended 11 T (MST11T) SRAM cell. The proposed cell is best suited to ultra-low voltage applications. Two ST-based cross-coupled inverters comprise the storage cell of the proposed MST11T bit cell. In comparison with conventional inverters, ST-based inverters have sharp voltage transfer characteristics. As a result, the proposed bit cell's stability performance increases. The proposed SRAM cell's leakage power consumption is reduced because of the use of stacked N-type transistors. For the read operation of the proposed bit cell, the read decoupled technique is used. As a result, the read static noise margin (RSNM) has greatly improved. The proposed bit cell's write static noise margin (WSNM) is increased by adopting feedback-cutting methodology. The performance of the proposed bit cell is compared with that of conventional 6 T, conventional 8 T, Schmitt-trigger 10 T (known as ST2), modified PMOS-PMOS-NMOS-based cell core 10 T (MPPN10T), feedback-cutting 11 T (FC11T), Schmitt-trigger 11 T (ST11), and Schmitt-trigger 12 T (ST12T) cells. According to the simulation results, the proposed MST11T SRAM cell has RSNM of 2.42, 1.18, 1.71, 1.30, and 1.80 times higher when compared to 6 T, FC11T, ST2, MPPN10T, and ST12T, respectively. The WSNM of the proposed bit cell has been increased by 1.56, 2.44, 1.28, 1.71, 1.35, 1.52, and 1.02 times, respectively, over 6 T, 8 T, ST2, MPPN10T, FC11T, ST11T, and ST12T. Furthermore, the suggested cell has a read delay that is 1.32, 1.79, and 1.53 times lower than ST11T, FC11T, and ST12T, respectively. The proposed bit cell has a write delay that is 1.14 and 1.63 times lower than FC11T and ST11T, respectively. The proposed MST11T bit-cell consumes 3.74, 1.56, 4.59, 5.38, and 4.83 times less leakage power than the 8 T, ST2, MPPN10T, FC11T, and ST12 bit-cells, respectively. When compared to 8 T/ST2/MPPN10T/ST12T at 0.2 V supply voltage, the enhanced facts incur a 4.87/3.79/3.78/1.97 penalty in write delay. The figure of merit (FOM) is derived as a result of this extensive access to the revolutionary SRAM cell performance, i.e., offering greater values at a 0.2 V DC supply voltage. In addition, the paper examines the impact of manufacturing process and temperature changes on MST11T cell enactment, as well as the circuit robustness using HSPICE with 7-nm FinFET technology. [ABSTRACT FROM AUTHOR]

This paper presents static and dynamic theoretical analysis of a new Operational Transconductance Amplifier (OTA) dedicated to low-voltage and low-power applications. High linearity is obtained using signal attenuation for rail-to-rail operation. Design, layout and post-layout simulations have been carried-out with Cadence Virtuoso in a 0.18µm CMOS technology. Post-Layout Simulation (PLS) demonstrates proper operation down to ± 0.75 V supply voltage with a high open loop small-signal voltage gain of 58.26dB, a unity gain frequency of 18MHz and a total harmonic distortion of -66.55dB at 100 kHz for a peak-to-peak input voltage of 0.8V. Based on this circuit, two applications have been successfully demonstrated: on the one side, a 5th order Butterworth G mC filter and, on the other side, a voltage mode instrumentation amplifier. [ABSTRACT FROM AUTHOR]

Portable applications and battery-operated devices require highly reliable, stable, and low-power nanometer-sized embedded cache static random access memory (SRAM) cells. The conventional 6-transistor (6 T) SRAM cell and its variants suffer from malfunctioning during the read/write operations, and instability, and are vulnerable to the multi-bit soft-error rate at scaled technology node and low supply voltage (VDD). In this regard, this paper proposes an 12 T SRAM cell with reliable functioning and reduced multi-bit soft-errors appropriate for low-power portable applications. This cell performs single-end bitline decoupled read operation and write data-dependent feedback-cutting-aware differential write operation to improve the read static noise margin (RSNM) and write static noise margin (WSNM), respectively. The presence of stack transistors in the cell core and read path, and also high virtual ground (VGND) minimize the leakage power dissipation. The proposed cell is compared with other state-of-the-art SRAM cells at VDD = 0.7 V and under harsh process, voltage, and temperature (PVT) variations. It offers at least 1.18X higher RSNM, 1.27X higher WSNM, and 2.02X lower leakage power dissipation. It also shows the second-best read power and incurs a penalty in write power. This cell shows at least 1.17X, 1.32X, and 1.04X smaller spread in read delay, RSNM, and WSNM, respectively, when subjected to PVT variations. In addition, the proposed cell eliminates the write half-select disturbance by employing a separate gate to drive the access transistors and thus column-interleaving structure and error correction coding can be applied to reduce multiple-bit upset and increase soft-error immunity. The soft-error in the proposed cell is reduced by at least 1.37X in critical charge. Generally, the proposed cell offers the best overall performance among all the compared cells by showing the highest proposed figure of merit. [ABSTRACT FROM AUTHOR]

Variable energy constraints affect the implementations of neural networks on battery-operated embedded systems. This paper describes a learning algorithm for randomization-based neural networks with hard-limit activation functions. The approach adopts a novel cost function that balances accuracy and network complexity during training. From an energy-specific perspective, the new learning strategy allows to adjust, dynamically and in real time, the number of operations during the network's forward phase. The proposed learning scheme leads to efficient predictors supported by digital architectures. The resulting digital architecture can switch to approximate computing at run time, in compliance with the available energy budget. Experiments on 10 real-world prediction testbeds confirmed the effectiveness of the learning scheme. Additional tests on limited-resource devices supported the implementation efficiency of the overall design approach. [ABSTRACT FROM AUTHOR]

This paper presents a sub-microwatt sub-bandgap voltage and current reference that can generate proportional-to-absolute-temperature (PTAT) and complementary-to-absolute-temperature (CTAT) currents concurrently. The voltage reference is derived from the process-insensitive silicon bandgap voltage of a bipolar junction transistor, whereas the current reference is made by combining PTAT and CTAT currents. Line regulation is improved by incorporating cascode devices without an operational amplifier (opamp). Fabricated in a standard 0.18-µm CMOS process, the proposed bandgap reference occupies an active area of 0.4 mm2. The current and voltage reference ( I REF and V REF ) are measured as 170 mV and 21 nA, respectively, while the start-up settling response is measured as 20 ms at room temperature. The average temperature coefficient of I REF and V REF is 79.8 ppm/°C and 87.93 ppm/°C across the temperature range from − 40 to 120 °C, respectively. The power consumption is 134 nW at the minimum supply voltage of 1.2 V. The power supply ripple rejection of V REF is measured as − 10 dB at 100 kHz without any filtering capacitor, when the 1.6 V input line voltage is distorted by a 300-mVp-p ripple. The measured line sensitivity of the voltage and current reference is 0.142%/V and 0.757%/V, respectively. [ABSTRACT FROM AUTHOR]

IoT and wearable medical devices frequently require ultra-low power solutions that can support long spells of inactivity. This study presents a buck converter to control power stages using a novel pulse frequency modulation (PFM) system that reduces switching losses for low-power systems. The modulation of high and low-frequencies was demonstrated, where the high-frequencies exhibited better energy transformation between the inductor and capacitor, and the low-frequencies could be adjusted for different current loads, to reduce switching losses. This circuit is optimized for light load applications. Using voltage control oscillation (VCO), the frequency range of 0.5 MHz – 2.0 MHz can be adjusted to influence conversion efficiency for different loads. The design was simulated and then fabricated using TSMC 0.18um process. The core size was about 1500 × 1000um that includes power MOS. Measurements result an average conversion efficiency of 91% under a load of 0.1 mA – 10 mA. This chip is suitable for battery-based IoT systems, or wearable medical devices. [ABSTRACT FROM AUTHOR]

This paper proposes a new discrete cosine transform (DCT) processor. The micro-rotation section of the architecture is based on a shared-resource improved coordinate rotation digital computer (CORDIC) unit, in an enhanced scalable DCT engine. To reduce the resources, and utilization area all micro-rotation operations have implemented as one united block in overlapped form. Using one processing element, the memory-based architecture has reduced the power consumption. Inputs and outputs of the processor are in-order which can be taken into account as an advantage for the proposed design. The processor has a low-complexity and distributed controller. Furthermore, due to the shared-resource implementation of CORDIC-II unit, by reduction of adding, shifting operations both in size, and number, the processor has high capabilities in short word lengths in comparison with state-of-the-art DCT processors. Compared to existing prominent DCT processors, the proposed processor achieves better results with limited hardware resources. [ABSTRACT FROM AUTHOR]

Static random-access memories (SRAMs), which are the most ubiquitous in modern system-on-chips, suffer from high power dissipation and poor stability in advanced complementary metal–oxide–semiconductor (CMOS) technology due to continuous learning, which leads to increased short-channel effects (SCEs), thereby, leading to use of new nano-devices. The fin-shaped field-effect transistor (FinFET) with lots of impressive attributes like mitigated SCEs is an efficient replacement for CMOS to overcome the aforementioned concerns. In this regard, this paper aims to explore a novel single-bitline 9-transistor (SB9T) SRAM with bit-interleaving capability appropriate for low-power near-threshold operation in 7-nm FinFET technology. The relative performance of the proposed SB9T is estimated by comparing it with other seven contemporary SRAMs such as conventional 6 T, write–read enhanced 8T (WRE8T), transmission gate read decoupled 9T (TGRD9T), one-sided Schmitt-trigger 9T (ST9T), data-independent read port 10T (DIRP10T), PMOS-PMOS-NMOS-based cell core 10T (PPN10T), and feedback-cutting 11 T (FC11T) at a near-threshold supply voltage of 0.5 V. Simulation results inferred that the SB9T offers 1.77 × /1.36 × and 2.35 × /13.13 × /1.30 × improvement in read stability and writability compared to WRE8T/ST9T and 6 T/DIRP10T/PPN10T, respectively. Furthermore, it consumes the best dynamic read power, which is at least 1.50 × , the third-best dynamic write power, and the second-best static power. The proposed SB9T SRAM offers 2.89 × /2.37 × improvement in dynamic write power/static power, at the expense of 1.742 × area overhead, compared to 6 T. [ABSTRACT FROM AUTHOR]

This paper investigates a novel highly stable and robust single-ended 10T SRAM cell appropriate for low-power portable applications. The cell core of the proposed design is a combination of a normal inverter with a stacked NMOS transistor and a Schmitt-trigger (ST) inverter with a double-length pull-up transistor. This improves hold stability and leakage power dissipation. The read and write operations of the proposed cell are performed with the aid of separated paths and bitlines, lowering power consumption. The strong cell core and decoupled read path eliminate the read-disturbance issue in the proposed cell, resulting in read static noise margin (RSNM) enhancement. Furthermore, the feedback-cutting write-assist technique used in the proposed design mitigates the writing '1' issue; consequently, write static noise margin (WSNM)/write margin (WM) improves. To prove the superiority of the proposed SRAM cell in various performance metrics, it is compared with state-of-the-art SRAM cells, introduced as 6T, TG9T, 10T-P1, and SB11T, using HSPICE and 16-nm CMOS technology node taking into consideration the impact of the severe process, voltage, and temperature (PVT) variations. Obtained results at VDD = 0.7 V show that the proposed design offers the highest HSNM/RSNM/WSNM (or WM). The read/write delay of the proposed cell is 3.92X/2.37X higher than that of the 6T SRAM cell due to its single-ended reading/writing structure. However, in terms of power consumption, the proposed cell exhibits 1.64X/1.54X lower than that of 6T SRAM cell. Though the proposed cell occupies a 1.24X higher area compared with the 6T SRAM cell due to its higher count of transistor, it shows the highest proposed figure of merit among all the studied SRAM cells, which is 26.90X higher than that of 6T SRAM cell. [ABSTRACT FROM AUTHOR]

In this paper, the impact of the inductive peaking bandwidth enhancement technique on the input-referred noise performance of a 10 Gbps optical receiver, which includes the CMOS Regulated Cascode (RGC) Transimpedance Amplifier (TIA) is investigated and analyzed. By examining the noise equations in this paper, a novel low-noise design methodology, is introduced. Additionally, through the implementation of the structured gm/ID\documentclass[12pt]{minimal}\usepackage{amsmath}\usepackage{wasysym}\usepackage{amsfonts}\usepackage{amssymb}\usepackage{amsbsy}\usepackage{mathrsfs}\usepackage{upgreek}\setlength{\oddsidemargin}{-69pt}\begin{document}$${\text{g}}_{\text{m}}/{\text{I}}_{\text{D}}$$\end{document} approach and by selecting the suitable transistor dimensions, the power consumption as well as the noise values are reduced, while the values of the obtained gain and bandwidth are increased. To verify the performance of the designed TIA, the circuit issimulated in HSPICE using 90 nm CMOS technology parameters. The simulation results show the obtained gain value of 55.45 dBΩ, a bandwidth of 7.51 GHz and an input referenced noise value of 15.7 pA/√Hz at the 1.2 V power supply, while the circuit consumes 0.75 mW of power. [ABSTRACT FROM AUTHOR]

In this paper, a new high-gain operational transconductance amplifier (OTA) circuit is designed. The proposed circuit uses bulk-driven technique to reduce the required supply voltage while gain-boosting as well as positive feedback techniques are used to increase the gain of the circuit and compensate the gain reduction effect due to the use of bulk-driven transistors. The performance of the proposed circuit is simulated using 180-nm CMOS technology parameters and is optimized using an optimization algorithm for the main purpose of minimizing the power consumption of the circuit. Simulated performance of the proposed circuit for 1.2 V DC supply voltage shows 94.8 dB gain, 203-MHz bandwidth, and slew-rate of 365-V/µS while occupying die area of 1360 µm2. However, the proposed circuit is also designed for a low-voltage scenario with 0.75 V DC supply voltage that results in 73.7 dB gain, 131-MHz bandwidth, and slew-rate of 149-V/µS. [ABSTRACT FROM AUTHOR]

In this paper, a two-stage dynamic comparator circuit is proposed, which considerably reduces the power consumption as well as the power-delay product parameter, while improves the speed. Furthermore, the performance of the pre-amplifier stage in the proposed design is improved which properly reduces the kick-back noise as well as the power consumption. The proposed circuit operates at 1 V supply at the clock frequency of 6 GHz (high-speed scenario), which results in the static and dynamic power consumption of 112.77 nW and 848 μW, respectively. Moreover, the delay of the circuit is 36.6 ps, while the output offset voltage is only 8 mV, with the kick-back noise of 48 mV. On the other hand, the circuit can operate at 1 V supply and frequency of 500 MHz (low-power scenario), which results in the reduced static and dynamic power consumption of 112.77 nW and 188.9 μW, respectively while the offset of the circuit can be reduced to only 1 mv at the delay of 46.4 ps and kick-back noise of 39.75 mV. [ABSTRACT FROM AUTHOR]

This paper presents the design and analysis of a new low-voltage and low-power OTA-C universal filter which can realise four different system topologies including: Single-Input Single-Output (SISO), Single-Input Multi-Output (SIMO), Multi-Input Single-Output (MISO) and Multi-Input Multi-Output (MIMO), without any requirement of extra switching or adding other active elements to the core filter circuit. In addition, the proposed circuit has the ability to operate in all modes of operation (multi-mode) using the grounded capacitors to effectively reduce the parasitic effects. Furthermore, to decrease the power consumption effectively, the proposed OTA-C filter is biased in the subthreshold region which significantly reduces the power consumption. Moreover, the proposed circuit has a very low sensitivity to the values of transconductance and capacitance elements. Finally, the performance of the proposed universal filter is simulated in HSPICE, using 0.18 µm CMOS technology parameters. However, the simulation results justify the design accuracy and low-power performance as well as the capability of generating filtering responses simultaneously in the different system configurations. [ABSTRACT FROM AUTHOR]

This paper presents a new low-power exponential function generator based on the first three terms of a Taylor series. This generator is used in a VGA which provides approximately 86 db of gain-range for that VGA in general. Power consumption of the exponential function generator is about (105–172) µW in maximum and minimum modes of its operation. Comparing with other reported VGAs, the whole VGA + exponential function generator + bias circuit dissipates less power which is about (576–650) µW in maximum and minimum modes of its operation. The 86 db gain-range of the VGA spans from – 24 to 62 db. This circuit and another VGA without using the exponential current have been designed in TSMC RF 0.18 μm and the results have been compared. The layout of the circuit has also been carried out in Cadence and demonstrates that the exponential function generator and the whole VGA + exponential function generator occupy 23 µm × 18 µm (0.0004 mil 2 ) and 0.0017 mil 2 of die area respectively. The post-layout-simulation of the circuit was also fulfilled and the results are displayed. [ABSTRACT FROM AUTHOR]

This paper presents a micro-watt level energy harvesting system for piezoelectric transducers with a wide input voltage range. Many such applications utilizing vibration energy harvesting have a widely varying input voltage and need an interface that can accommodate both low and high input voltages in order to harvest as much energy as possible. The proposed system consists of two rectifiers, both implemented as negative voltage converters followed by active-diodes, and three switched-capacitor DC-DC converters to either step-up or step-down and regulate to the target voltage. The system has been implemented in a 0.18 μm CMOS process and the chip measures 3 mm2. Measurements show a low voltage drop across the rectifiers and high peak power efficiency of the DC-DC converters (68.7-82.2%) with an input voltage range of 0.45-5.5 V for the complete system. Used standalone, the DC-DC converters support input voltages between 0.5 and 11 V while maintaining an output voltage of 1.8 V at an output power of 16.2 μW. The ratio of each converter is selectable to be either 1:2, 1:3, or 1:4. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low power successive approximation analog-to-digital converter. An improved implementation of the binary weighted capacitors array and a novel comparator that operates in the time instead of the voltage domain are effective and power efficient. The circuit, fabricated in a conventional 0.18-μm CMOS technology, achieves a sampling rate of 100 kS/s and an effective number of bit of 9.4. Using a 1-V supply voltage, the achieved power consumption is 3.8 μW, leading to a Figure of Merit as low as 56 fJ/conversion-level. [ABSTRACT FROM AUTHOR]

In this paper, a low-power, low-noise and high swing capacitively coupled instrumentation amplifier for biomedical applications is proposed. It uses the folded cascode operational transconductance amplifier (FC-OTA) with current scaling at the output branch to reduce the noise. To overcome the reduction in the effective transconductance of the OTA due to current scaling, series-series and shunt-shunt feedback techniques are proposed at the folded node of the FC-OTA and the composite transistor is proposed at the bottom current source of the FC-OTA. An optimization procedure is also proposed for sizing the input transistors of the FC-OTA to obtain better noise-power tradeoff. To assess the efficacy of these techniques, a biopotential amplifier is designed in 0.18 µm CMOS process and it is studied through simulation. From this study, it is found that the proposed amplifier has a 1.5-22 times and 1.4 times higher input swing and output swing respectively compared to those reported in literature. It has a gain of 39.75 dB, a bandwidth of 0.3 Hz-4.4 kHz and a total input-referred noise of 3.19 µVrms integrated over 1 Hz-10 kHz. The power consumption of the amplifier is 4.07 µW at a VDD of 1.8 V. It achieves a noise efficiency factor of 2.78, and provides input and output signal swings of 14.86 mVpp, and 1.38 Vpp respectively at THD of 1%. [ABSTRACT FROM AUTHOR]

This paper presents a robust and low-power single-ended robust 11T near-threshold SRAM cell in 10-nm FinFET technology. The proposed cell eliminates write disturbance and enhances write performance by disconnecting the path between cross-coupled inverters during the write operation. FinFETs suffer from width quantization, and SRAM performance is highly dependent to transistors sizing. The proposed structure with minimum sized tri-gate FinFETs operates without failure under major process variations. In addition, read disturbance is reduced by isolating the storage nodes during the read operations. To reduce power consumption this cell uses only one bit-line for both read and write operations. The proposed SRAM cell reduces write delay, average power and PDP by 20, 78 and 62%, respectively as compared to the 9T single-ended SRAM cell. Moreover, the proposed cell enhances write static noise margin by 33% under process variation. [ABSTRACT FROM AUTHOR]

This paper describes a low-voltage phase-locked loop (PLL) design using a new calibration technique for low-power implantable biomedical systems. The proposed PLL uses a switching technique in the charge pump and a bulk-driven technique in the voltage-controlled oscillator (VCO) to reduce power consumption and operate at ultralow voltage. To compensate for the process variation, a calibration circuit is proposed to control the capacitor array of the VCO. This work was implemented in a 0.18- $$\upmu \hbox {m}$$ standard CMOS process with a 1.8-V supply voltage. The results show that the proposed PLL can operate from 402 to 405 MHz with a 0.7-V power supply and provides ten channel spaces for switching (where every channel has a bandwidth of 300 KHz) for biomedical system applications. At 405 MHz, the measured phase noise and reference spurs are $$-99.49$$ dBc/Hz at 1 MHz offset and $$-48.04$$ dBc, respectively. Furthermore, the measured root-mean-square jitter and peak-to-peak jitter are 9.93 and 82.03 ps, respectively. The total power consumption of the PLL is only 0.425 mW, and the active die area is 0.067 $$\hbox {mm}^{2}$$ . [ABSTRACT FROM AUTHOR]

This paper presents an analog filter based on Rauch biquadratic cell. The filter exploits an improved analog stage that makes linearity performance uniform over the entire pass-band frequency region. All feedback analog filters suffer from poor linearity when the input tones frequency is in close proximity to the closed-loop poles frequency, where loop-gain reduces. This often forces an overdesign with higher current (higher power consumption) and/or higher overdrive voltages (lower dynamic range) in order to meet the linearity specifications over the whole filter pass-band region. The hereby proposed Rauch scheme resolves such a binding issue without power increasing and having the same IIP3 at low and at high frequency (up to the filter closed-loop poles frequency). Hence the linearity performance is in first approximation independent on the input tones bandwidth. In order to validate the hereby proposed idea a 4th-order 25 MHz −3 dB bandwidth pseudo-differential filter has been designed and simulated in CMOS 28 nm technology. The prototype consumes 820 µW from 1 V supply voltage and has 15 and 13 dBm IIP3 at 5 and 6 and 20 and 21 MHz input tones, respectively. [ABSTRACT FROM AUTHOR]

The low-power current feedback instrumentation amplifier (CFIA) circuits using local feedback configuration are reported in the literature for biomedical applications. However, they have limitations such as low gain, higher area, and higher noise due to the need for higher source degeneration resistors (in tens to hundreds of kΩ), and higher minimum achievable bandwidth (in tens of kHz). In this paper, a low-power, low-noise CFIA using closed-loop configuration is proposed to overcome these limitations. It uses a folded cascode operational transconductance amplifier with a lower value of source degeneration resistor (in the order of few kΩ) in the input stage to reduce the noise without compromising the loop gain. As the bandwidth of the proposed CFIA is defined as unity-gain bandwidth of the CFIA's loop gain, it can be reduced below 10 kHz without increasing area. The proposed CFIA is designed and implemented in a 0.35 µm CMOS process for a current of 9.6 µA with a supply voltage of 3 V, and its performance is evaluated through simulation. It has a gain of 34 dB, total input-referred noise of 3 µVrms, and a noise efficiency factor of 3.81. It achieves a bandwidth of 8.8 kHz using a load capacitor which is more than four times smaller than that of local CFIA. It provides an input signal swing of 16 mVpp at THD of 1% and the CMRR of 118 dB. [ABSTRACT FROM AUTHOR]

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools. [ABSTRACT FROM AUTHOR]

Reading the memristor memory cell without changing its resistance state is one of the potential problems to be addressed in the memristor-based memory design. This paper presents a novel read scheme that achieves a non-destructive read operation, consumes less power, provides high endurance and adapts itself based on the process variations. The proposed scheme uses built-in self-tuning circuitry to obtain the optimum amplitude and width of the refresh pulse required to completely retrieve the state of the memristor after the read cycle. As the scheme uses refresh pulse only when needed, the scheme saves nearly 50% of average power when compared with a conventional fixed pulse read method. The self-tuning circuits are validated by a generic, accurate, and efficient "voltage threshold adaptive memristor" model. The validation results prove that the proposed tuning circuitry achieves optimum refresh pulse size under various read disturbance faults. [ABSTRACT FROM AUTHOR]

In this paper, a new energy-efficient sample and hold (S/H) circuit based on the proper combination of the Miller-effect and double-sampling technique is presented in the Carbon Nanotube Field Effect Transistor (CNTFET) technology. In order to improve the accuracy and increase the input dynamic voltage range, a new CNTFET-based linearized switch circuit is introduced to be utilized as both the input sampling and output buffer switches. The proposed circuit is simulated in HSPICE using 32 nm CNTFET technology parameters. The simulation results confirm that the proposed S/H circuit properly operates for the data rates of higher than 2 GS/s. In addition, the proposed S/H circuit shows 14-bit resolution, 86.29 dB of SNDR for a 0.4 Vp-p, 218.75 MHz sinusoidal input signal at 2 GS/s sampling rate. [ABSTRACT FROM AUTHOR]

In this paper, the design of low-noise, low-power transimpedance amplifier (TIA) is presented for a miniaturized amperometric based continuous blood glucose monitoring system for wearable devices. The proposed multi-stage cascode common source transimpedance amplifier circuit is designed and implemented in a 180 nm CMOS technology. It has been demonstrated that the proposed TIA shows a significant increase in transimpedance gain, 1.72 GΩ with a bandwidth of 180 kHz and input referred current noise is 18 fA/√Hz for an input current of 200 pA. The total power consumption is 52 μW with a 1.4 V supply and occupies a chip area of 110 μm × 140 μm. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and power-efficient data conversion. The amplification stage of the proposed DTDC is designed using self-biasing technique, which helps to reduce external biasing requirement to bias bulk/gate of the transistors. The self-biasing technique controls threshold voltage (Vth) of the transistors either for fast switching (low-Vth) or for low power dissipation (high-Vth). The latch stage of the proposed DTDC is designed with novel dynamic CMOS inverters to improve the regeneration speed. The mathematical equations for delay and offset voltage are derived for the proposed DTDC and improvements are mentioned. The proposed DTDC is designed in CADENCE and simulated with SPECTRE using 45 nm CMOS process technology at the low power supply of 0.8 V to verify the outcomes. The simulation results reveal that the delay and power dissipation of the proposed DTDC are 166.29 pS and 2.3 µW respectively. The analysis of 1-sigma offset error is performed using Monte-Carlo simulation. Here, the mismatch and process variation are considered and the samples are generated randomly till 200 samples (runs). Additionally, the peak input voltage error due to kickback noise is 0.219 mV for a differential input voltage of 5 mV. [ABSTRACT FROM AUTHOR]

In this paper, energy efficient VLSI architectures for linear turbo equalization are studied. Linear turbo equalizers exhibit dramatic bit error rate (BER) improvement over conventional equalizers by enabling a form of joint equalization and decoding in which soft information is iteratively exchanged between the equalizer and decoder. However, turbo equalizers can be computationally complex and hence require significant power consumption. In this paper, we present an energy-efficient VLSI architecture for such linear turbo equalizers. Key architectural techniques include elimination of redundant operations and early termination. Early termination enables powering down parts of the soft-input soft-output (SISO) equalizer and decoder thereby saving power. Simulation results show that energy savings in the range 30–60% and 10–60% are achieved in equalization and decoding, respectively. Furthermore, we present finite precision requirements of the linear turbo equalizer and an efficient rescaling method to prevent overflow. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit 2-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) without calibration based on 0.18 μm 1P6M CMOS technology. To gain one bit of resolution without increasing the number of capacitors, one-side-fixed technique is used to generate the proposed switching procedure based on merged capacitor switching (MCS) switching procedure. Besides, a new DAC control logic is proposed by inserting the SAR logic circuits into level-shift circuits to reduce the complexity of the DAC control logic, enable high-speed and low-power operation and reduce the chance of race and hazard of the combinational logic circuit at the same time. The measured results show the proposed ADC achieves an SNDR of 67.26 dB and consumes 183.3 μW at 1.8 V power supply and 2 MS/s, the peak DNL and INL are +0.66/−0.64 LSB and +0.75/−0.74 LSB, respectively, resulting in a figure-of-merit of 48.63 fJ/conversion-step. The ADC core occupies an active area of 630 × 570 µm. [ABSTRACT FROM AUTHOR]

The implementation of a video reconstruction pipeline is required to improve the quality of images delivered by highly constrained devices. These algorithms require high computing capacities—several dozens of GOPs for real-time HD 1080p video streams. Today's embedded design constraints impose limitations both in terms of silicon budget and power consumption—usually 2 mm2 for half a Watt. This paper presents the eISP architecture that is able to reach 188 MOPs/mW with 94 GOPs/mm2 and 378 GOPs/mW using TSMC 65-nm integration technology. This fully programmable and modular architecture, is based on an analysis of video-processing algorithms. Synthesizable VHDL is generated taking into account different parameters, which simplify the architecture sizing and characterization. [ABSTRACT FROM AUTHOR]

Wearable telecare and telehealth systems are those which can be worn on the human body and continuously monitor a user's vital status. Even though these systems have already shown promise in applications for improving medical service quality and reducing medical costs, a short battery life significantly restricts the widespread use of these systems. Low-power technologies (a general name for technologies which use various approaches to reduce the power consumption of the associated electronics) can help alleviate this disadvantage of wearable telecare and telehealth systems. In this paper, we review recent developments and applications of low-power technologies in wearable telecare and telehealth systems, sorting the various approaches into two categories: hardware-based approaches and firmware-based approaches. This paper focuses on illustrating how to realize these approaches but does not provide a quantitative analysis of different approaches, since the intended applications of these approaches are quite different, hence numeric comparison is not meaningful. Given the proliferation of wearable telecare and telehealth systems, there will be a greater emphasis on the development of low-power technologies in this field. [ABSTRACT FROM AUTHOR]

This paper presents a low-power high linearity ΣΔ analog-to-digital converter (ADC) for audio applications. By adopting low noise large output swing operational amplifiers in a 2-1 cascaded modulator, not only can the noise floor be reduced, but the input signal range can also be enlarged. A low-power, area-efficient digital decimation filter was also designed to decrease the area and the power cost. The ADC was fabricated in the SMIC 65 nm single-poly-eight-metal (1P8M) mixed-signal complementary metal-oxide-semiconductor (CMOS) process with a die area of 0.36 mm. Measurement results showed that a 90 dB peak signal to noise plus distortion ratio (SNDR) and a 93 dB dynamic range (DR) were achieved over the 22.05 kHz audio band. The power dissipation was 2.2 mW from 1.2 V power supply, which is suitable for audio codec applications. [ABSTRACT FROM AUTHOR]

This paper presents a low power ring oscillator-based spread-spectrum clock generator with three-step frequency and voltage-controlled oscillator (VCO) gain calibration for S-ATA applications. To meet the low jitter requirements with a small VCO gain, a ring-type VCO with three step frequency calibration and gain calibration scheme is proposed. The proposed coarse tuning method selects the optimal tuning currents and capacitances of the ring VCO to optimize the phase noise. The gain of ring-type VCO can be reduced and kept constant with the proposed three-step frequency and VCO gain calibration. As a result, it can improve the phase noise characteristics of the ring-type VCO and make it more robust to the PVT variations. Also, charge pump up/down current mismatches are compensated with the current mismatch compensation block. This chip is fabricated with 65 nm CMOS technology, and the die area is 430 × 460 μm. The power consumption is 12 mW at 1.2 V supply voltage. The measured RMS jitter and phase noise are 2.835 ps and −96.83 dBc/Hz at 1 MHz offset, respectively. [ABSTRACT FROM AUTHOR]

This paper presents the design and performance of an ultra-low-power 4/5 frequency divider based on a CMOS ring oscillator. Measurements show a 198 % locking range (6 MHz–1.3 GHz) for both division ratios at room temperature, covering the MICS band and 433 and 915 MHz ISM bands while consuming only 4.07 μW from a 1 V supply at 400 MHz. The wide locking range and low power consumption makes it very suitable for ultra-low-power wireless systems. The divider is fabricated in a 90 nm CMOS process and occupies 45 μm 2 of area. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low-power VLSI implementation of H.264/AVC baseline decoder. A systematic methodology for power reduction is proposed and applied at various design abstraction levels. At the algorithm level, the computational complexity is optimized. At the architecture level, pipelining and parallelism are widely adopted to reduce the operating frequency; hierarchical memory organization optimizes power-hungry memory accesses; hardware sharing reduces the total switching capacitance. At the circuit level, the knowledge about signal statistics is exploited to reduce number of transitions; data dependent signal-gating and clock-gating are introduced which are dynamic techniques for power reduction; multiplications are reduced and optimized, while complex dividers are totally eliminated. At the physical level, cell sizing and layout are optimized for power efficiency. The VLSI implementation shows that with UMC 0.18 μm technology, the proposed design is able to decode realtime QCIF 30fps at 1.5 MHz. The decoder contains 169 k logic gates and 2.5 KB on-chip SRAM. The total chip area is 4.4 × 4.4 mm in a CQFP 208 package. The measured power consumption is 973 μW @ 1.8 V and 293 μW @ 1.0 V. The low-power and realtime features make our design ideal for portable or mobile applications. [ABSTRACT FROM AUTHOR]

This paper presents a low-power, wide-range variable gain RF transmitter for 900 MHz-band wireless communication applications based on a standard 0.18 μm CMOS technology. A very wide-range variable gain and high linearity up-conversion mixer is obtained by using a newly transconductance stage. High linearity at low power dissipation driver amplifier can be obtained by adopting a folded cascode topology with an additional gate-source capacitor. The measured results show conversion gain of 16 dB, dB-linear gain variation of 47 dB with the linearity error less than ±0.5 dB, output P-1 dB of 2 dBm, and OIP3 of 12 dBm while dissipating 4 mA from 1.25 V supply. [ABSTRACT FROM AUTHOR]

A New CMOS four-quadrant analog multiplier is presented in this paper. The proposed multiplier is suitable for low supply-voltage operation and its power consumption is also very low. The proposed circuit has been simulated with the HSPICE and simulation results are given to confirm the feasibility of the proposed analog multiplier. According to the simulation results, under the supply voltage of 1.5 V, the input range of the proposed multiplier can be 120 mV and the corresponding maximum linearity error is less than 3.2%. Moreover, the power dissipation of the proposed circuit is only 6.7 μW. The proposed circuit is expected to be useful in analog signal processing applications. [ABSTRACT FROM AUTHOR]

This paper proposes a one-branch zero-IF receiver topology, which samples the I and Q signals of the modulated RF carrier with one signal path by means of a multiphase local oscillator. The suggested one-branch receiver works without matching problem, and it is also capable of cancelling out the flicker noise and DC-offset when the local oscillator is configured to the four-phase mode. The one-branch receiver saves much area and power compared with the traditional two-branch ones. All of the advantages above make the one-branch receiver topology a promising architectural candidate for low-power and low-cost RF CMOS receiver designs. [ABSTRACT FROM AUTHOR]

The complex valued matched filter correlators consume maximum power in the DS/SS CDMA receivers. These correlators accumulate 1024 samples lying in the range −7 to +7. This accumulation needs 3 data bits, 1 sign bit and 10 extra bits for overflow. Hence, the correlator can be implemented as a cascade of 4-bit full adder and a 10-bit incrementer. As a ripple carry adder (RCA) consumes the least power among all the existing adder architectures, we have implemented the 4-bit adder as a RCA. Previous incrementers were implemented as ripple counters. In this paper we propose a novel incrementer which is faster than a ripple counter based incrementer. Hence, it can be operated at a reduced voltage resulting in considerable power reduction. The incrementer is implemented using multiplexers, AND gates and TSPC registers. The ripple-counter correlator and the proposed incrementer correlator were laid out in MAGIC using 0.5 μ CMOS technology followed by power estimation using HSPICE. It is shown that the proposed architecture requires 50% less power than a ripple counter based design. [ABSTRACT FROM AUTHOR]

In this paper, a novel ultra-low-power, low-voltage, ultra-high output resistance and uniquely high bandwidth (BW) femto-ampere current mirror is proposed. Pre-layout results with HSPICE in TSMC 0.18 $${\upmu }\hbox {m}$$ CMOS technology are given at 1.2 v power supply that prove such exceptional features of the proposed current mirror as: ultra-low consumed power of 1.56 $${\upmu }\hbox {w}$$ , ultra-high output resistance of 1.98 $$\hbox {T}\Omega $$ , very low output voltage of 91 mv and most exceptionally, the extra high BW of 26.5 MHz that is, so far, unique at such extra low minimum output current of 1.8 fA. Also, post-layout plus Monte Carlo simulation results are performed with CADENCE in the same abovementioned technology. Most favorably, this study also proves the same exceptional quality of the features as: the same ultra-low consumed power, fairly the same output voltage of 92 mv, ultra-high output resistance of 1.45 $$\hbox {T}\Omega $$ and still uniquely high BW of 17.5 MHz but at extra low output current of 5.5 fA. Good robustness of the proposed current mirror against PVT non-idealities is also proved by Monte Carlo simulations. [ABSTRACT FROM AUTHOR]

This paper describes the design and realization of a programmable 4th-order, G-C bandpass filter for biomedical applications. The core 2nd-order filter stage is realized by a simple gyrator-C active inductor structure with a single MOSFET as the transconductor element. The capacitive input attenuation technique is used to enhance the linearity of the filter. The proposed filter was designed and simulated with a 1-V power supply voltage with process parameters from a standard 0.18 µm CMOS technology. Post-layout simulation shows that the center frequency of the filter is adjustable from 80 Hz to 6.18 kHz by using a programmable bias current generator. At a nominal center frequency of 945 Hz and the quality factor of 3, the filter exhibits a dynamic range of 57.6 dB and an input-referred noise of 174.2 µV. The filter consumes only 6 nW from a 1-V single power supply voltage and the active area of the overall circuit is 0.088 mm. [ABSTRACT FROM AUTHOR]

The growing demand of Internet of things based portable gadgets motivate to develop low power static random access memory (SRAM) cell. It occupies large portion in modern system on chip devices. In this context, a detailed review on various SRAM cell topologies has been performed which includes comparative analysis of design parameters and challenges. To perform the comparative analysis, considered SRAM cell topologies are simulated with cadence virtuoso IC6.1.5-64b at 45 nm generic process design kit technology file. It is worthy to notice that 9T SRAM cell has highest value of read stability among considered cells. It is attributed to use of differential read decoupled structure. The 7T SRAM cell has highest value of write ability among considered cells. It is observed that 8T SRAM cell has lowest read power dissipation among considered cells. It happens due to the use of stack transistor in read path of the cell. The lowest value of read access time is also observed in 8T SRAM cell among considered SRAM cells. It is 1.82 × higher as compared to conventional 6T SRAM cell. Further, the write access time of 9T SRAM cell is lowest among considered cells. This is 1.41 × less as compared to conventional 6T SRAM cell. Static noise per unit area to power delay product ratio (SAPR) is used to evaluate the overall performance of considered SRAM topologies. It is observed that 8T SRAM cell has the highest value of SAPR among considered SRAM cells. It is 1.91 × as compared to conventional 6T SRAM cell. All the comparison has been done at 1.0 V supply voltage. [ABSTRACT FROM AUTHOR]

This paper proposes a 10-bit 100 MS/s 20 MHz low power pipelined analog-to-digital converter (ADC) with switched capacitor based programmable gain amplifier (PGA) suitable for wireless receiver applications. In the proposed ADC the double loading problem caused in the first stage of 10-bit pipelined ADC is avoided. In order to minimize the power consumption, split-capacitor sharing correlated double sampling and op-amp sharing technique has been used. Using the technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined ADC. Switched capacitor topology based PGA occupies an area of 0.0031 mm. Switched capacitor topology based PGA with the integration of 10-bit pipelined ADC consumes 25.54 mW of power at 100 MS/s from a 1.8 V power supply. [ABSTRACT FROM AUTHOR]

This paper presents power and area analysis of two-stage comb-based decimation structures for high decimation factors. The first stage is either in a recursive form cascaded-integrator-comb (CIC) or in a non-recursive form, while the second stage is in a recursive form. The proposed structures are compared with a single CIC structure. We demonstrated how to choose the decimation factor of the first stage in order to get simultaneously the highest possible power reduction and the lowest possible area increase, in a comparison with a single CIC structure. Additionally, the modified two-stage structure with an increased attenuation and a reduced power consumption is presented. Analysis is supported by MATLAB simulations and validated by the VHDL implementations. [ABSTRACT FROM AUTHOR]

The complexity of radiofrequency circuit design comes from the large number of parameters to be adjusted. Constant node shrink in CMOS process and variation of technology skills significantly contribute to this complexity. The paper reports on a reliable and portable design methodology based on a low-power figure of merit (FOM) and inversion coefficient applied to the design of a low noise amplifier (LNA). The design procedure considers the circuit specifications and the optimization of the FOM. As a case of study it is applied to 2.4 GHz LNA designed in a 28 nm technology then exploited to compare different CMOS technology nodes: 28, 65, 130 nm. [ABSTRACT FROM AUTHOR]

This paper investigates low-energy consumption and low-power hardware models and processor architectures for performing the real-time recognition of objects in power-constrained autonomous systems and robots. Most recent developments show that convolutional deep neural networks are currently the state-of-the-art in terms of classification accuracy. In this article we propose to use of a different type of deep neural network-stacked autoencoders-and show that within a limited number of layers and nodes, for accommodating the use of low-power accelerators such as mobile GPUs and FPGAs, we are still able to achieve both classification levels not far from the state-of-the-art and a high number of processed frames per second. We present experiments using the color CIFAR-10 dataset. This enables the adaptation of the architecture to a live feed camera. Another novelty equally proposed for the first time in this work suggests that the training phase can also be performed in these low-power devices, instead of the usual approach that uses a desktop CPU or a GPU to perform this task and only runs the trained network later on the FPGA. This allows incorporating new functionalities as, for example, a robot performing runtime learning. [ABSTRACT FROM AUTHOR]

Complexity management, portability and long term adaptivity are common challenges in different fields of embedded systems, normally colliding with the needs of efficient resource utilization and power balance. Image/signal processing systems, though required to offer a large variety of complex functions, have also to deal with battery-life limitations. Wearable signal processing systems, for example, should provide high performance and support new generation standards without compromising their portability and their long-term usability. These constraints challenge hardware designers: early stage trade-off analysis and power management automated techniques are helpful to guarantee a reasonable time-to-market. In the field of video codec specifications, the MPEG standard known as Reconfigurable Video Coding (RVC) framework addresses functional complexity and adaptivity leveraging on the intrinsic modularity of the dataflow model of computation, but it still lacks in offering power management support. The main contribution of this work is providing an automatic early-stage power management methodology to be adopted within the MPEG-RVC context. Starting from different high-level specifications, our mapping methodology identifies directly on the high-level models disjointed homogeneous logic clock regions, where the platform resources can be enabled/disabled together without affecting the overall system performance. To extend its usability to the RVC community, we have integrated this methodology within the Multi-Dataflow Composer (MDC) tool. MDC is a tool for on-the-fly reconfigurable signal processing platforms deployment. In this paper, we extended MDC to address power-aware multi-context systems. To prove the effectiveness of our work, a coprocessor for image and video processing acceleration has been assembled. This latter has been synthesized on a 90 nm ASIC technology, where demonstrated up to 90 % of reduction in the dynamic power consumption on different dataflow-intensive applications. The coprocessor has been implemented also on FPGA, confirming, partially, the benefits of adopting the proposed methodology. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage continuous-time delta-sigma modulator (DSM) intended for the receiver of an ultra-low-power radio. The DSM features a 2nd-order loop filter implemented with a single operational amplifier to reduce the power consumption. Furthermore, a 4-bit quantizer is used to achieve high resolution while keeping the sampling frequency low. The quantizer is realized using the successive approximation register architecture with asynchronous control which is more power efficient than the commonly used flash architecture. The DSM has been implemented in a 65 nm CMOS process. Simulation results show a peak SNDR of 65 dB over a 500 kHz signal bandwidth. The DSM consumes 69 $${\upmu }$$ W from a 800 mV power supply. [ABSTRACT FROM AUTHOR]