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This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area. [ABSTRACT FROM AUTHOR]

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

Digital Circuits applications are expanding rapidly in modern times because they generate correct signals without errors or interferences. These digital circuits play important roles in data storage operation, as well as the implementation of image processing applications on hardware where the power, speed, and area of an electronic device play a significant role, particularly in the field of modern VLSI technology. The digital comparator with more number of bits plays an important role in image processing applications. In the proposed research paper, an attempt is made to design a speed and area efficient 32-bit comparator. To improve the speed of the comparator a modified priority encoder technique is used. It shows that the area of proposed 32-bit digital comparator consumes 573.73 units which are 20% better than when compared with the conventional comparators and the speed improved by 50% when compared with the Conventional Comparators. The proposed implementation is simulated on the 'Encounter(R) RTL Compiler RC14.28'. [ABSTRACT FROM AUTHOR]

In this research, an all-optical 1-bit comparator (AOCMP) is designed using two-dimensional photonic crystals (2D-PhCs) nonlinear ring resonators (NRRs), and its performance is analyzed based on the threshold switching method. By optimizing the structural parameters of NRRs, such as the refractive index and radius of the rods, this resonator can operate with desired wavelength (1550 nm) within the operating frequency range determined by the transverse magnetic (TM) band diagram. The performance of the proposed AOCMP is analyzed in terms of various factors such as optical switching power, bit rate, time delay, and ON-OFF contrast ratio that are calculated using a finite difference time domain (FDTD) simulation. Also, the operating frequency range (the wavelength range of 1355–2178 (nm)) is investigated using the plane wave expansion (PWE) method. The optimized optical device has exhibited a high contrast ratio of 10.36 dB within a very small size of 325 ${\rm{ \mu }}{{\rm{m}}^2}$ μ m 2 . [ABSTRACT FROM AUTHOR]

This paper presents a new compact monopulse comparator network system (MCNS) using a modal substrate-integrated waveguide (SIW) hybrid coupler for the first time. The main objective of this research is to evaluate the performance of dual-plane MCNS based on return loss and coupling coefficients. A detailed analysis, design, and implementation of dual-plane MCNS is performed using the four modal SIW hybrid couplers. The sum and difference signals required by the monopulse antenna are generated with the proper orientation of couplers. The in-phase and out-phase characteristics of the couplers are generated using TE102 and TE201 orthogonal degenerate modes. A complete planar and compact SIW structure has a footprint of 58.2 mm × 58.2 mm. MCNS is fabricated on a single-layer Rogers RO4003 substrate with a permittivity of 3.55 and thickness of 0.787 mm using a photo-lithographic process. MCNS provides excellent return loss characteristics at all input and output ports. It measured the isolation better than 20 dB for all output ports in the desired frequency band. It achieved good coupling between all input and output ports. Simulation and measured results show that at 10 GHz, MCNS gives better performance parameters and can be used in monopulse antenna. [ABSTRACT FROM AUTHOR]

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13. [ABSTRACT FROM AUTHOR]

Comparison of numbers represented in residue number systems (RNS) is considered as a difficult RNS operation. However, RNS comparators faster than the straightforward "convert-to-binary and compare" alternative have been recently reported. Nevertheless, we present improved RNS comparators for three balanced 4-moduli sets (listed in the title, above) based on shortcut mixed radix conversion. Synthesis results show considerable improvements regarding some figures of merit. For example, 29% (24%) speedup (cost reduction) for the first moduli set, 18% cost reduction for the second, 28% lower power dissipation and 64% energy saving regarding the third one in comparison to previous works are achieved. [ABSTRACT FROM AUTHOR]

Localized data conversions for sensors placed under harsh environmental conditions often require Analog to Digital Converters (ADC) capable of working under wide operating temperature range. Even though the fastest analog to digital converter, flash ADC is omitted from the high temperature regime due to the requirements of reference voltage source, reference voltage divider and a comparator array capable of providing stable operation under wide operating temperatures. A CMOS Schmitt inverter-based internal reference comparator array for flash ADC which is efficient in terms of area and power consumption, capable of working under wide temperature range is presented in this paper. The proposed idea replaces the reference voltage source, resistive reference voltage divider and differential comparator array of a conventional flash ADC by an array of suitably sized Schmitt inverters. The circuit was simulated for static and dynamic characteristics with gpdk 180 nm library using cadence virtuoso simulation suite. The voltage transfer characteristic curve (VTC) of the proposed comparator array was found invariable when a temperature sweep in the range of −40 to 170 degree Celsius was performed. Each of the comparator in the proposed array consumes a silicon area of 40.68 u m 2 and the average dynamic power consumption per cycle is estimated as 103.1 uW. [ABSTRACT FROM AUTHOR]

In the present scenario, power, speed, and area of an electronic device play a significant role specifically in the field of modern VLSI technology. In this research, small power dissipation and a less area-based single 12-bit comparator has been designed using a multiplexer. To improve the speed of the comparator a completely unique technique has applied, where three 4-bit comparator blocks have been used rather than a single 12-bit comparator. These comparator blocks compare simultaneously two signals each having 4-bits. The aim of this paper is to design and implement a 2-bit digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. Finally, the novel technique has been applied to improve the overall performance of a 12-bit comparator. The results of this paper are simulated on the EDA tanner tool realized in 32-nanometer technology at 0.7 V supply voltage. It shows that the propagation delay of 12-bit digital comparator using the novel technique is 5.15 nanoseconds which is approximately 30% less than the proposed multiplexer-based single 12-bit comparator. [ABSTRACT FROM AUTHOR]

Expression of the HAHB4 sunflower transcription factor confers drought tolerance to wheat event IND-ØØ412-7 (HB4® wheat). After confirming the compositional equivalence of event IND-ØØ412-7 with conventional wheat, its nutritional similarity to its non-genetically modified (GM) counterpart was analyzed by performing a 42-day broiler feeding study. Isoenergetic diets containing 40% flour from wheat event IND-ØØ412-7, its non-GM counterpart Cadenza, and a commercial variety were included in the study. Broilers' performance was analyzed by measuring feed intake, weight gain, feed conversion, and time to reach 2.8 kgs. The yield was evaluated by carcass weight, breast meat, and abdominal fat. No differences were found between wheat event IND-ØØ412-7 and the non-GM counterpart. A few significant differences were found with the commercial variety which were associated with the genetic background, different from the other two materials. These results support the nutritional equivalence of event IND-ØØ412-7 with conventional wheat. [ABSTRACT FROM AUTHOR]

Neuropsychological impairments are observed in individuals with Bipolar Disorder (BD), yet knowledge of how cognitive deficits unfold in real-time remains limited. Given intraindividual variability in mood observed in people with BD, and the potential for mood and cognition to be mutually influential, we employed ambulatory assessment technologies to examine potential contemporaneous (same survey) and lagged (next survey) relationships of congition and mood. Outpatients with BD (n = 46) or no psychiatric disorders (heathy volunteers [HV]; n = 20) completed in-laboratory neurobehavioral assessments and 14 days of smartphone-administered mobile cognitive tests and ratings of affective variables. Linear mixed-effects models were used to analyze real-time relationships between mobile cognitive test performance and mood. On in-laboratory tests, participants with BD showed worse cognitive performance than HVs as well as mild depression severity; mood and cognitive performance were unrelated. On mobile cognitive tests and surveys, participants with BD showed somewhat worse cognitive performance and ratings of lower energy and greater sadness relative to HV participants. Among those with BD, mania and sadness earlier in the day related to worse processing speed and better working memory performance, respectively, on the next survey. In contrast, same survey ratings of greater stress related to better working memory, and greater happiness related to better processing speed. Real-time assessments of mood and cognition provide incremental information beyond what can be gleaned from laboratory assessments. Understanding how these affect-related changes in processing speed emerge and play out in daily life may provide clinically useful information for treatment planning. [ABSTRACT FROM AUTHOR]

A voltage supply scalable analog voltage comparator for a wide input range is presented in this paper. A digital gate-based methodology is used to design the comparator in order to extend the use of automation in the analog designs. Therefore, the proposed comparator is enormously cost-effective, reduces the time-to-market, scalable to newer technologies, and more immune to process variations than the conventional CMOS analog voltage comparators. The comparator is designed using Semi-Conductor Laboratory (SCL) 180 nm digital CMOS technology at a supply voltage of 1.8 V. The power consumption of the proposed comparator is 160 µW approximately with total delay and offset voltage of 1.63 ns and 4.28 mV, respectively. Also, 4-bit and 5-bit flash ADC is designed as an application. The measured values of DNL/INL are ± 0.4/± 0.4 LSB and 0.42/± 0.6 LSB for 4-bit and 5-bit, respectively. [ABSTRACT FROM AUTHOR]

Dry eye disease (DED) is a multifactorial disease of the ocular surface characterized by loss of homeostasis of the tear film and accompanied by symptoms such as ocular discomfort and visual disturbance. DED is one of the most common reasons for seeking medical care in the United States and across the world. Despite this, there are a limited number of pharmacologic therapies for the treatment of DED in the United States and Europe. This review examines the different pivotal trials for DED medications and the impact the vehicle in each trial. In recent clinical trials, the vehicle of the active formulation of the medication is often used as the active comparator. A literature review of published dry eye clinical trials was performed to identify the pivotal clinical trials of DED medications and to compare treatment effect and further understand the impact of the vehicle on clinical trial outcomes. The pivotal clinical trials for the currently approved treatments for dry eye have widely varying study designs. The variations include differences in inclusion criteria, outcome measures and efficacy endpoints, and whether or not the use of concomitant artificial tears is allowed. These differences make it difficult for accurate comparisons to be made between DED medications. Each trial demonstrated that the vehicle alone has some beneficial effect on signs and symptoms of dry eye disease. This review discusses the varying trial designs and vehicles used in the pivotal studies for the four approved dry eye medications in the United States and Europe, as well as novel vehicles under development and clinical trial recommendations. [ABSTRACT FROM AUTHOR]

The inclination of individuals to improve their performance when it lags behind that of others with whom they naturally compare themselves can be harnessed to optimize the individuals' effort in work and study. In a given set of individuals, we characterize each individual by his relative deprivation, which measures by how much the individual trails behind other individuals in the set doing better than him. We seek to divide the set into an exogenously predetermined number of groups (subsets) in order to maximize aggregate relative deprivation, so as to ensure that the incentive for the individuals to work or study harder because of unfavorable comparison with others is at its strongest. We find that the solution to this problem depends only on the individuals' ordinally measured levels of performance independent of the performance of comparators. [ABSTRACT FROM AUTHOR]

Two similarly designed studies compared user experiences with a second-generation extra-thin-wall, 5-bevel 32 G × 4 mm pen needle (PN) with redesigned hub versus four thinner commercially available PNs. Adults (18–75 years old) with type 1 or type 2 diabetes and ≥3 months of experience with pen injectors qualified for single-visit, single-blinded randomized studies. The investigational 32 G PN was compared with three 33–34 G × 3.5–4 mm PNs in Study 1 and one 34 G × 4 mm PN in Study 2. Participants completed 12 abdominal injections of 0.3 mL sterile saline using insulin pens in 6 pairs, each comprising one investigational 32 G PN and one comparator PN in random order. After each injection pair, participants compared injection pain via relative 150 mm visual analog scale (VAS) and perceived dose delivery force via relative 5 point Likert scale. Adjusted models tested injection pain scores (primary endpoint) for noninferiority and, if met, then for superiority. ClinicalTrials.gov identifiers: NCT03878758 and NCT03878745. The investigational 32 G PN met noninferiority as well as superiority criteria for less injection pain vs. each comparator (p <.01), with adjusted mean relative VAS scores 9.1–17.6 in Study 1 (n = 154) and 7.3 in Study 2 (n = 55). The investigational 32 G PN was also superior vs. each comparator PN in requiring less relative perceived force to deliver the dose (p <.01). The investigational 32 G PN was associated with less participant-reported injection pain and less perceived dose delivery force compared with four thinner PNs, suggesting no additional pain reduction or force reduction benefit conferred by the thinner PNs. [ABSTRACT FROM AUTHOR]

Purpose: To evaluate the impact of guselkumab on work productivity, including absenteeism and presenteeism, in psoriasis patients with and without depression/anxiety. Methods: VOYAGE 2 is a randomized, double-blind, placebo-controlled, and comparator-controlled, phase 3 trial that compared guselkumab with adalimumab in patients with moderate-to-severe psoriasis. Absenteeism was evaluated among patients who reported that their skin prevented work/study based on the Dermatology Life Quality Index (DLQI) work/study domain (score = 3) at baseline. Presenteeism was assessed by summarizing mean changes in four Work Limitations Questionnaire (WLQ) domain scores at week 24. Analyses were compared between treatments and stratified by depression/anxiety status at baseline. Results: At week 24, 82.1% and 50.0% in the guselkumab and adalimumab groups, respectively, reported a DLQI work/study score = 0 (no effect of skin on work/study) (p <.001). Mean changes (improvements) were greater in guselkumab-treated versus adalimumab-treated patients in the work limitations domains of Physical Demands (−6.9 vs. −3.3, p <.05), Mental-Interpersonal (−6.3 vs. −3.2, p <.06), and Output Demands (−6.2 vs. −2.2, p <.05). Improvements were consistent in patients with and without depression/anxiety. Conclusions: Psoriasis patients treated with guselkumab had significantly better improvements in absenteeism and presenteeism compared with those treated with adalimumab, regardless of depression/anxiety status. [ABSTRACT FROM AUTHOR]

Russia, Ukraine and Belarus are good comparators sharing a common Soviet past, similar cultures and religions, while in the COVID-19 crisis they have pursued quite different policies. Belarus has denied the pandemic and undertaken no measures. Russia played down the epidemic for a long time and then undertook half-hearted and incoherent measures. Ukraine feared the virus and carried out an early and strict quarantine in a centralized policy. While testing has been sparse until recently and death tolls remain uncertain, Belarus and Russia appear to have done poorly in terms of health, while Ukraine has so far done much better. It is too early to judge the economic outcomes. [ABSTRACT FROM AUTHOR]

In this study, Perturb and Observe Maximum Power Point Tracking algorithm and Model Predictive Control (MPC) algorithm are combined to improve the dynamic performance of the control structure of boost converters used in renewable energy systems. For this purpose, a digital control method that does not need any comparator is developed. The maximum power point current value is determined from the Maximum Power Point Tracking (MPPT) algorithm and it is used as the reference for current control operation in the MPC algorithm. Dynamic capability and tracking performance of the proposed control method is validated by simulation and experimentally. The dynamic behaviour of the control algorithm is analysed by carrying out step change tests. Results show that the control method has excellent dynamic performance thanks to its feature of reference tracking in only one switching period. Furthermore, overshoots and undershoots are successfully eliminated. [ABSTRACT FROM AUTHOR]

The conventional single-stage comparators, as the basic elements of analogue-to-digital converters (ADCs), are modified for offset and mismatch errors to be utilised in multi-bit per stage pipeline structures. At first, in single-stage comparators, pre-amplification and latch operations are managed by temporary domination of positive or negative feedback via the bulk potential variations in PMOS (p-channel metal oxide semiconductor) devices. Then, the offset correction scheme is added to provide highly matched unit cells within the sub-ADCs of the pipeline structure. Monte-Carlo analysis with 100 iterations shows that input-referred offset reduces to 0.35 mV at σ, while input offset was randomly applied from a Gaussian distribution with 30 mV at 3σ. Using as unit cells of sub-ADCs in a 12-bit 100 MS/s pipeline ADC, ENOB (and SFDR) would be improved from 8.5-bits (and 53.6 dB) to 11.25-bits (and 74.2 dB), when offset error and bulk potential of PMOS devices experiences random variations with 25 mV and 60 mV at 3σ, respectively. Power consumption reaches to 0.45 mW at 625MS/s comparison speed. Post-Layout simulation results are presented at all process corners using the BSIM3v3 model of a 0.18 µm CMOS technology. [ABSTRACT FROM AUTHOR]

A timing correction approach is proposed in this article to improve the performance of high-speed serial data link involving pulse position modulation (PPM) and pulse amplitude modulation (PAM) techniques. The proposed technique corrects the timing error that arises from combining the PAM approach with the PPM approach, which allows transmitting more bits and hence achieving higher data rate for the designed serial link. The proposed technique uses the recovered AM bits to adapt the reference voltage of the comparator circuit at the receiver side in order to correct the jitter results from combining the time modulation with the amplitude modulation. A 5-bit 4-Gb/s serial data link that involves PAM and PPM has been designed and simulated using the proposed technique in 130 nm CMOS technology using 800 MHz as an input clock signal. The simulation results indicate that when combining AM and PPM techniques, the total number of the transmitted bits can be increased using the proposed technique. The total power consumption of the proposed link is less than 84 mW. A performance comparison between the proposed link and other serial links has been carried out that indicates an improved performance for serial links involving the proposed technique. [ABSTRACT FROM AUTHOR]

This paper proposes a time domain modelled built-in self-test (BIST) with ramp noise projection and their effects on analogue to digital converter (ADC) in testing. A self-biased linear ramp generator has been proposed for high precision testing. Threshold inversion quantization (TIQ) comparator based fast switching flash ADC has considered under test. A time domain model of output response analysis technique has been proposed to calibrate the linearity errors of the converter. An ADC has been validated with different input frequencies to characterize the harmonic distortion and average delay of the system. The proposed testing technique requires less time to measures the uncertainties of the ADC since the full computation is performed within one ramp cycle. The testing results of the proposed BIST technique are aimed to characterize, validate and compare to the best results of the existing ADC BIST techniques for test accuracy. [ABSTRACT FROM AUTHOR]

A computationally simple approach to inference in state space models is proposed, using approximate Bayesian computation (ABC). ABC avoids evaluation of an intractable likelihood by matching summary statistics for the observed data with statistics computed from data simulated from the true process, based on parameter draws from the prior. Draws that produce a "match" between observed and simulated summaries are retained, and used to estimate the inaccessible posterior. With no reduction to a low-dimensional set ofsufficient statistics being possible in the state space setting, we define the summaries as the maximum of an auxiliary likelihood function, and thereby exploit the asymptotic sufficiency of this estimator for the auxiliary parameter vector. We derive conditions under which this approach—including a computationally efficient version based on the auxiliary score—achieves Bayesian consistency. To reduce the well-documented inaccuracy of ABC in multiparameter settings, we propose the separate treatment of each parameter dimension using an integrated likelihood technique. Three stochastic volatility models for which exact Bayesian inference is either computationally challenging, or infeasible, are used for illustration. We demonstrate that our approach compares favorably against an extensive set of approximate and exact comparators. An empirical illustration completes the article. for this article are available online. [ABSTRACT FROM AUTHOR]

Objectives: To develop a self-reported measure for medication adherence and compare its ability to predict the proportion of days covered (PDC) with contemporary scales.Methods: Retrospective prescription fill data from three community pharmacies in the Southeastern US were assessed to identify patients that were 18 years of age or older, and had received at least one medication for diabetes, hypertension, or dyslipidemia. A cross-sectional survey containing the Medication adherence Estimation and Differentiation Scale (MEDS) was administered among these pharmacy patrons. The MEDS assessed the extent and reasons for non-adherence. Survey responses were anonymously linked with retrospective prescription fill data. A total of 685 patients were sampled. The proportion of days covered (PDC) was used as the criterion measure. The Morisky, Green, and Levine Adherence Scale (1986 Morisky scale) and the Medication Adherence Reasons Scale (MAR-Scale) were used as comparators.Results: The MEDS presented a five-factor solution-worries about side-effects, worries about addiction, worries about cost, lack of perceived need, and unintentional non-adherence (CFI = 0.97; RMSEA = 0.06; SRMR = 0.03; standardized factor loadings greater than 0.5, and statistically significant). The relationship between MEDS scores and PDC was statistically significant (unstandardized regression coefficient = -0.50, p < .01). The MEDS performed better than the 1986 Morisky scale (R2 = 0.02 vs 0.05, standardized regression coefficient = -0.13 vs -0.21) and the MAR-Scale (R2 = 0.02 vs 0.05, standardized regression coefficient = -0.12 vs -0.21) in predicting PDC.Conclusions: The MEDS demonstrated good psychometric properties and performed better than the comparator scales in the prediction of PDC. [ABSTRACT FROM AUTHOR]

The XOR/XNOR gates are basic building blocks for various digital systems like adders, comparators, multipliers, parity-generator/checker and encryption processor. This paper proposes two realisations each using 2-pass transistors/2-transmission gates and 2-inverters. All the proposed circuits are simulated and compared with existing circuits using Cadence Spectre on both 180 and 90 nm CMOS technology with varying supply rail (from +0.8 V to +1.8 V). The simulation results confirm that the proposed circuits achieve a full rail-to-rail swing, high performance and high noise margin at low voltages. Analytical expressions in support of simulation-results wherever required are included. A typical application in Hamming-code generation is proposed. [ABSTRACT FROM AUTHOR]

Purpose: Interleukin (IL)-17 and IL-23 inhibitors are the newest biologic agents used in the management of moderate-to-severe psoriasis. Active comparator studies allow for direct comparison of different biologic agents. We sought to systematically investigate the efficacy of newer biologic agents compared to earlier biologics. Materials and methods: We conducted a literature search for randomized control trials that compared the efficacy of a biologic agent with an active comparator. Articles from January 1 2010 to June 26 2017 were searched. Reference lists were also reviewed for studies for inclusion. Results: Twelve studies were included, a majority being phase III trials. All of the studies compared the efficacy of IL-17 and IL-23 inhibitors with adalimumab, etanercept, or ustekinumab with the exception of one study that compared the efficacy of ustekinumab with etanercept. IL-17 and IL-23 inhibitors consistently demonstrate superior efficacy over TNF inhibitors and ustekinumab as assessed by 75%, 90%, and 100% improvement in baseline Psoriasis Area and Severity Index (PASI) scores at week 12. Conclusions: Overall, IL-17 and IL-23 inhibitors appear to demonstrate superior efficacy and more rapid clinical improvement when compared to older biologic agents. This review may help predict patient outcomes, manage patient expectations, and biologic agent utilization. [ABSTRACT FROM AUTHOR]

Gain and offset represent two important measures to determine the accuracy of a comparator. Thus, analysis on these parameters is very important as they offer designers better understanding of the circuit and allow exploring trade-offs during design. In this paper, two methods were presented to derive a set of design equations that describe the gain, sensitivity, offset, and systematic mismatches observed in typical comparator circuits. A three-stage, fast complementary metal-oxide semiconductor (CMOS) comparator structure is analysed and simulated in order to validate the proposed methods. A 0.13 μm CMOS technology is used for simulations with 1.5 V supply voltage. Bisection theorem was used for gain and sensitivity analysis. Simulation results show that high gain improvement can be possible by using the design equations. The input offset voltage, due to mismatch in the width of the metal oxide semiconductor field-effect transistors (MOSFET) (W) and mismatches in the threshold voltages of the N and P type MOSFETs(VTHN, VTHP), is analysed using a proposed balanced method. The same comparator structure is used for the input offset voltage analysis. Simulations show that an offset improvement can be achieved following the design equations found through the proposed method. [ABSTRACT FROM PUBLISHER]

Quantum dot-cellular automata (QCA) emerge as a research area to design nanometre scale logic circuit. In digital logic design, a comparator is the fundamental building block that performs the comparison of two numbers. This paper deals with the design of reversible building block for 1-bit comparator and its implementation in QCA. An improved QCA layout of Feynman gate is also achieved. The QCA Feynman gate is denser and has low delay than the existing circuit. The proposed reversible comparator has quantum cost 9, whereas the QCA reversible comparator has the quantum cost 0.927. The quantum cost based comparison of the proposed QCA reversible comparator with conventional reversible comparator shows the cost effective circuit design in QCA. The simulation result matched the truth table of comparator which approves the functional capability of the proposed QCA layout of comparator. All the proposed layouts dissipate very low power. [ABSTRACT FROM PUBLISHER]

Two types of low-power asynchronous comparators featured with input data statistical characteristic are proposed in this article. The asynchronous ripple comparator stops comparing at the first unequal bit but delivers the result to the least significant bit. The pre-stop asynchronous comparator can completely stop comparing and obtain results immediately. The proposed and contrastive comparators were implemented in SMIC 0.18 μm process with different bit widths. Simulation shows that the proposed pre-stop asynchronous comparator features the lowest power consumption, shortest average propagation delay and highest area efficiency among the comparators. Data path of low-density parity check decoder using the proposed pre-stop asynchronous comparators are most power efficient compared with other data paths with synthesised, clock gating and bitwise competition logic comparators. [ABSTRACT FROM PUBLISHER]

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of ‘weak 0’ existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both ‘good 1’ and ’good 0’. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time. [ABSTRACT FROM PUBLISHER]

Aim: To psychometrically assess cognitive domains in adolescents with ADHD during long-term open treatment with robust dosing of extended-release methylphenidate (OROS MPH). Methods: Data were derived from a prospective clinical study of adolescent ADHD, employing the Cambridge Neuropsychological Test Automated Battery (CANTAB), before and after up to one year of treatment with OROS MPH. In the absence of placebo control, a similar age and gender group of youth without ADHD served as comparators. Results: During the course of treatment with OROS MPH, ADHD youth’s performance significantly improved across multiple CANTAB tasks, including spatial working memory, rapid visual processing, verbal recognition memory, set shifting, and inhibition/vigilance. ADHD subjects’ scores in several CANTAB tasks, including spatial working memory, planning, and set shifting, were significantly more impaired at baseline compared to the non-ADHD comparison group; these significant differences were no longer seen at endpoint. Conclusions: Statistically significant improvements in multiple cognitive domains were observed in a sample of adolescents with ADHD over the course of 12 months of robust treatment with extended-release methylphenidate. Rigorous, monitored stimulant treatment may be associated with objectively determined cognitive benefits; however, practice effects in this open trial cannot be ruled out. Further study on this important topic is warranted. [ABSTRACT FROM PUBLISHER]

This article provides findings from a review of the published English-language literature of criminological research in and on Taiwan - over the period 2000-2010, and sets the findings against other Asian comparators. The article identifies tropes and trends in purpose, method, theory, and collaborative networks of criminological research on Taiwan. The findings and analysis, hold, as it were, a mirror up to the criminological communities in both Taiwan and other parts of the English-speaking world. We conclude with a consideration of these issues in the broader context of the "internationalization" of criminology. [ABSTRACT FROM AUTHOR]

This paper reports the design of multi-standard sigma delta modulator with low power consideration. It uses the cascaded methodology for modulator design to reduce power dissipation and single feedback system has been used to provide higher stability. The concept of oversampling and noise shaping is used in the design of modulator to increase Signal to Noise Ratio (SNR). The OP-AMP designed has a gain of 62 dB and phase margin of 72° to make the design stable. The second order sigma delta modulator designed can be used for either GSM or WCDMA applications at a sampling frequency of 5 MHz and 20 MHz, respectively. The bandwidth of the signal considered for GSM and WCDMA is 200 KHz and 2 MHz, respectively. The SNR and dynamic range obtained for GSM is 82 dB and 71 dB, respectively, and for WCDMA the same is 62 dB and 54 dB, respectively. The multi-standard modulator is designed in standard 180 nm CMOS technology at a power supply of 1.8 V and the total power consumed is 4.867 mW. [ABSTRACT FROM AUTHOR]

The simulation and experimental study of proportional integrator (PI) controlled DC bus voltage of three phase shunt active power filter (APF) to improve power quality by compensating harmonics and reactive power required by nonlinear load is proposed. The compensation process is based on sensing mains currents only, an approach different from conventional methods, which usually require harmonics or reactive volt-ampere values of the load. The non-sinusoidal mains voltage problem is resolved by using phase locked loop (PLL) system. Pulse width modulation (PWM) signal generation is based on hysteresis control comparators to obtain the switching signals.ű Various simulation and experimental results are presented under steady state and transient conditions. [ABSTRACT FROM AUTHOR]

Practical stability is of significant practical importance in scientific and engineering problems but less investigated for descriptor systems. This paper develops the concepts of practical stability to descriptor systems and by using Lyapunov functions and comparison principle, presents some techniques to specify admissible control sets, such that the motion of the closed-loop descriptor systems is practically stable and impulsive-free. Finally, as an application, this paper discusses linear time-invariant descriptor systems and derives a sufficient condition. To illustrate our approach, a simple circuit network and a numerical example are analysed. [ABSTRACT FROM AUTHOR]

Design considerations for a high-speed CMOS comparator for application in highspeed analogue-to-digital conversion are presented. Extensive simulations show that the comparator designed accordingly operates well above 250 MHz clock speed in standard 0.5 mum CMOS technology. An accuracy of 5 mV and average power consumption of 0.3 mW on 3.3 V power supply is observed using simulations when it operates at 250MHz. [ABSTRACT FROM AUTHOR]

A method for generating a constant envelope band-limited binary phase-shift keying signal using a sine-wave crossing technique is proposed. This method is simpler than other common methods since it employs comparators and an EX-OR gate instead of the multipliers which are usually used. The results obtained are quite satisfactory. [ABSTRACT FROM AUTHOR]

Investigates non-linear analog-to-digital conversion using a non-linear function of time. Comparison of the function of time with the voltage through the analog comparator; Theory of operation; Electric circuit diagram.

A free-running multivibrator for generation of very non-symmetrical waveforms is described. The multivibrator includes a differential pair which functions as a simple comparator, two single-transistor switches and two capacitors. The charge of a large capacitor determines the duration of the first quasi-stable state (space), the recharge of a small capacitor determines the duration of the second quasi-stable state (mark). The calculations of the quasi-stable state durations are given. The circuit can provide a space/mark ratio of the order of 1000–5000 at the frequency of 1 kHz and this ratio becomes larger for smaller oscillation frequencies. The circuit can be retuned for a different oscillation frequency without transient response. The modification with one capacitor for smaller space/mark ratios is considered also. [ABSTRACT FROM AUTHOR]

A new high-gain CMOS voltage comparator circuit is presented and its simulated performance described. This simple source-coupled pair comparator circuit requires only eight MOS transistors. [ABSTRACT FROM AUTHOR]

A phase-locked regulator system (PLRS) of a universal motor with a phase-frequency comparator (PFC) is theoretically and experimentally studied. System asymptotic stability is proved theoretically and stability criteria are given. The theoretical results are in very good agreement, with measurements. Finally, it is concluded that the PLRS of a universal or series DC motor is a cheap system with excellent speed regulation. [ABSTRACT FROM AUTHOR]

A phase-locked regulator system (PLRS) of separately excited DC motors with a phase-frequency comparator is theoretically and experimentally studied. For the phase-frequency comparator a new non-linear but simple model which explains the system behaviour very well is introduced. System asymptotic stability is proved theoretically and stability criteria are given. The effect of input changes on system performance is quantitatively described. Finally it is shown that the theoretical results are in very good agreement with measurements obtained from an actual system on the basis of which some practical design aspects are discussed. [ABSTRACT FROM AUTHOR]

A new phase-comparator using bucket brigade device (BBD) is proposed. It is composed of a conventional phase-comparator with a phase shifter using BBD in the feedback path. Its dynamic range is wider than that of the conventional phase-comparator. This phase-comparator will find many applications, such as a demodulator for the widely phase-modulated wave and a component for PLL. [ABSTRACT FROM AUTHOR]

In a recent publication, Boutin et al. (1979) have presented some circuits ideas on a broadband square-wave frequency multiplier. These circuits need a comparator type A/D converter which is both rare and expensive. In the present paper, some new circuits are presented in which the A/D converters have been replaced by D/A converters which are cheaper and more accessible. [ABSTRACT FROM AUTHOR]

A technique is proposed for implementing parallel tree-like comparator circuits with fan-in constrained gates, exhibiting logarithmic comparison time growth. The tehnique is based on formulating the binary comparator logic to resemble the carry look ahead logic of the binary adder. The implementation is extended to modular tree comparator networks. [ABSTRACT FROM AUTHOR]

Presents a programmable CMOS current comparator circuit which employs seven identical small-dimension MOS transistors, and whose threshold current is adjustable without the need to change any of the MOS transistors. Programmable range; Comparator circuit for analog VLSI neural networks.

Describes the design and analysis of a high-speed gallium arsenide (GaAs) comparator circuit with less power consumption and area. Use of high-speed GaAs comparator circuit on high-speed A/D conversion and artificial neural networks applications; Analysis of the comparator to determine the effects of threshold deviations on the resolution; Use of controlled sizes of devices to minimize susceptibility to threshold deviations while maintaining optimum performance.

A CMOS window comparator which is capable of accepting a digital input reference is presented. The comparator uses two external resistors to adjust the boundaries as a percentage of the reference voltage. The reference input is a digital word which is converted, using an on-chip DAC. The proposed circuit is a useful building block for various applications like process control, automatic testing and the implementation of analogue built-in self-test (BIST) structures, etc. [ABSTRACT FROM AUTHOR]

Presents a high-speed, high-accuracy complementary metal oxide semiconductor (CMOS) comparator design that is based on standard auto-zero techniques. Auto-zero comparison routines; Description of a switch-controlled and a capacitor-controlled cross-coupled comparator; Simulation results.

A new high-speed high-resolution CMOS comparator is reported in this paper. A new offset-voltage-cancellation technique is used to reduce the effect of clock feed-through or charge pumping. The effective input voltage is doubled by the use of a cross-multiplexed technique. SPICE simulations using a modified MOS3 model (Wong 1986) show that the comparator reported here is capable of resolving 40 μV in less than 2·5 μs and 100 μV in 1 μs. [ABSTRACT FROM AUTHOR]

This paper reports a comprehensive general analysis of sine comparators for distance protection of transmission lines. A mathematical basis is developed for realizing rectilinear characteristics and a graphical construction is presented to derive the necessary input signals for the sine comparators for obtaining a variety of pick-up characteristics on the impedance plane. A new criterion in multi-input sine comparators (sequence comparators) for the discrimination of faulty and healthy conditions of a protected transmission line section is established and a comparator model in schematic form is presented to realize the popular quadrilateral polar characteristics based on the new criterion. [ABSTRACT FROM AUTHOR]