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The time-dependent dielectric breakdown in thin gate oxides is studied and a new methodology is proposed that is applicable to a wide range of gate stacks for extracting soft breakdown (SBD) and post-SBD wear-out (WO) parameters from measuring the time to hard breakdown ([t.sub.HBD) only. A new complete reliability prediction model is proposed that has included SBD and WO.

The article presents various different techniques that can be employed for the evaluation of the threshold voltage shift induced by the negative bias temperature instability (NBTI). The effects of sensing and recovery are shown to be the major factors that need to be considered during the process of voltage evaluation.

The behavior of FinFET devices is analyzed under electrostatic discharge (ESD) conditions for various layout and process conditions. The results have shown that the possible extreme sensitivity of FinFET devices might not be a showstopper for the advanced nanotechnologies if ESD is considered during the technology development.

The impact of strain on negative bias temperature instability (NBTI) is assessed by studying devices with polycrystalline-Si/SiON as well as deposited metal gate/high-[kappa] and FUSI/high-[kappa] gate stacks. The studies have shown that there is no degradation of intrinsic NBTI behavior due to process-induced strain.

The development and application of the variable-frequency charge pumping (CP) technique for high-k materials via independent control of the low-level discharging time and the high-level charging time of the pulse is reported. The appearance of two bands superimposed on top of the usual base-level CP curve due to application of large pulse amplitude to the gate has revealed the presence of two separate defect energy level in the high-k dielectric.

The impact of positive charging on the performance of pMOSFETs is examined.

The pitfalls and limits of the conductance method for alternative semiconductor metal-oxide-semiconductor (MOS) are discussed. Findings suggest the successful adaptation of the conductance method for reliable ad compete extraction of the interface trap density.

The article presents the accuracy of three-lumped-parameter model for gate impedance of MOSFET devices at frequencies from dc to the gigahertz range.

The impact of chlorine residue concentration in thin Hf[O.sub.2] films on the MOSFET device time-dependent dielectric breakdown (TDDB) is discussed. The results have shown that the presence of chlorine residue has no important impact on the trap generation and reliability of atomic layer deposition (ALD) Hf[O.sub.2] layers.

A study was conducted to examine the effects of source/drain activation thermal budget and premetallization degas conditions on interfacial regrowth, carrier mobility, and defect densities for Si[O.sub.2]/Hf[O.sub.2]/TaN stacks. The mobility degradation arises from an increase of defects, both within the interface layer (IL) and the high-[kappa] bulk, as detected by both pulsed current-voltage and charge-pumping measurements.

Comparison of digital and analog figures-of-merit of FinFETs and planar bulk MOSFETs reveal an interesting tradeoff in the analog/RF design space. It is found that FinFETs possess the key advantages over bulk MOSFETs including reduced leakage, excellent subthreshold slope, and a better voltage gain without degradation of noise or linearity.

Electrostatic discharge (ESD) reliability simulations at circuit-level are used to develop an approach for modeling the breakdown and snapback behavior of advanced MOSFET structures. The junction and gate leakage currents due to increased tunneling in the scaled-down CMOS technologies are described, and parameter extraction procedures for the model parameters are also presented.

Low equivalent oxide thickness (EOT) and high-performing n-channel transistors with a Hf[O.sub.2]/TaN gate stack and a low thermal-budget process is demonstrated using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an EOT of 8 Angstrom, a leakage current of 1.5/a[cm.sup.2] at [V.sub.G] = 1 V, a peak mobility of 190 [cm.sup.2]/V .s and a drive current of 815 [mu]A/[mu]m at an OFF-state current of 0.1 [mu]A/mum for [V.sub.DD]= 1.2V.

Complementary measurements of the drain and gate low-frequency noise are used as a powerful probe for sensing the hafnium-related defects in nMOSFETs with high-kappa gate stacks and polysilicon gate electrode. Drain noise measurements indicate that for low hafnium content (23%) and thin high-kappa thickness (2nm), the defect density at the substrate dielectric interface is similar to conventional SiO2 and gate-noise measurements suggest that defect density is degraded by the hafnium content.

The degradation of a n-type lateral DMOS transistor is shown to be related to the injection of hot holes in the drift region field oxide. A new degradation model using the bulk current as the driving force reproduces the saturation effects observed in the parameter shifts.

The report stated that the key assumption in this model is that the trap-trap distance or trap-interface distance is the dominant parameter in the conduction mechanism causing anomalous charge loss. The oxide is characterized by a single parameter, the trap density. The studies stated that failure rate calculations are possible for different oxide qualities, thicknesses and voltage. Two-trap and three-trap percolation paths can limit the failure rate.

Physical processes responsible for the generation of hole traps in silicon dioxides are investigated. It is indicated that the most important processes for hole-trap generation are found to be in direct interaction of injected holes with the oxide.

The hot-carrier degradation behavior of both lateral and vertical integrated DMOS is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Findings show that due to the specific nature of the vertical DMOS (VDMOS) device, the hot hole injection is absent in the device and the channel N(sub it) formation is substantially lower in the VDMOS.

Dielectric relaxation currents in SiO2/A12O3 and SiO2/HFO2 high-kappa dielectric stacks were studied. The thickness dependence, gate voltage polarity dependence and temperature dependence of the relaxation current in high-kappa dielectric stacks are discussed.

Research involving charge trapping and dieleof SiO[subscript 2]-Al[subscrip 2]O[subscript 3] gate stacks with TiN electrodes ctric reliability is described and discussed.

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]

The electron generation causes two reliability problems for the thin gate oxide used in the current and future generations of the CMOS processes. During the initial stage of stress, more field traps are generated, but their generation rate is significantly slowed down as the stress continues.

The influence of field-effect transistor (FET) gate oxide breakdown on the performance of a ring oscillator circuit is studied using statistical tools, emission microscopy and circuit analysis. It is further demonstrated that many hard breakdowns can occur in this circuit without affecting its overall function.

Research into hole trapping amd trap generation in the gate silicon dioxide is presented.

A new study investigates the properties of transport mechanisms after soft breakdown in thin oxide nMOSFETs.

The origin of the Fowler-Nordheim-induced substrate hole current was re-examined.

The effects of increased temperature on degradation and lifetime prediction of thin silicon-dioxide films are discussed.

A new study investigates the effect of nitridation on hot hole injection by comparing oxynitrides and oxides.

A study was conducted to examine the effects of high temperature operation on the reliability of source side injection-Flash E2PROM devices. The long-term persistence of cell degradation was evaluated as basic degradation monitors were utilized to understand the physical origin of the observed cell behavior. Results suggested no long-term relief of disturb effects when source side injection devices are operating at 150 degrees C.

The electric breakdown or B-mode stress-induced current (SILC) is of interest as a mode of breakdown in ultra thin oxide layers. It has recently been shown that after soft breakdown (SBD) now significant variations in threshold voltage and transcondunctance of metal-oxide-semiconductor FETs. The SBD phenomenon has been studied in capacitors and in nMOSFET's, and it is shown that a substrate current component is introduced by SBD, which is strongly linked to the gate current.