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The article studies a novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI). Findings reveal the characteristics of NOI mask ROM, including 2-bits-per-transistor operation, body effects, hot carrier impact, and array layouts.

The characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-[Al.sub.2][O.sub.3] gate dielectrics are examined. The studies have shown that the relatively inferior n-FET has resulted from the larger source/drain contact resistance, higher surfaces states scattering, and lower substrate-doping concentration.

The experimental hole gate direct tunneling current of p-MOSFETs are described under shallow trench isolation (STI)-induced longitudinal compressive stress, which has not followed the trend caused by the strain-altered valence-band splitting alone. The strain-retarded oxide growth rate has enhanced hole direct tunneling and has reversed the conventional trend due to the strain-altered valence-band splitting.

A physics-based compact subthreshold current model is described for short-channel nanoscale double-gate MOSFETs. The electrostatics is dominated by capacitive coupling between the body electrodes, the potential is obtained as an analytical solution of the 2-D Laplace equation and the current modeling is based on drift-diffusion theory.

A huge drain current hysteresis and transient behavior observed during pseudo-MOSFET ([Psi]-MOSFET) drain current-gate voltage measurements is reported. Measurements suggest that the drain current hysteresis in mainly due to substrate deep depletion, with simulations confirming that transient behavior is dependent on substrate generation.

This paper presents a new hardware implementation of gate drive circuits applied to low-power neutral-point-clamped (NPC) multilevel three-phase inverters. The proposed circuit is based on commercially available MOS-gate driver ICs (MGDs) for large-scale applications, which may reduce the total cost of implementation of NPC inverters. Only one dc power supply is required to feed all the gate drivers for the three-phase system. Detailed design procedures are presented, which include the protection circuits for avoiding hazardous switching states of the power switches. Experimental results of a laboratory prototype demonstrate the validity of the proposed circuit. These results also suggest that for achieving safe operation of snubberless power switches during transients, a hybrid implementation of each NPC phase leg, consisting of MOSFETs with voltage ratings at half the dc bus voltage and of insulated gate bipolar transistors rated at the total dc bus voltage, is recommended. Index Terms--Charge pump technique, gate drive circuit, switch-voltage balancing, three-level neutral-point-clamped (NPC) inverter.

Electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge has shown low off current, which is suitable for Schottky barrier (SB) p-MOSFETs. The incorporation of high-quality Schottky diodes in the source/drain of a Ge channel PMOS has shown that a highly doped substrate is used to minimize the source-to-drain subthreshold leakage current.

A physical description of two specific aspects in drain-extended MOS transistors, that is, quasi-saturation and impact-ionization effects, is described and these factors are attributed to the Kirk effect. The model is validated by MATLAB program and has displayed excellent scalability for various transistor dimensions, drift-region doping concentration and voltage-handling capability.

A new experimental method is described for determining the backscattering coefficient and the ballistic ratio of n- and p-FDSOI and multigate nanodevices. Universal abaci are developed in order to accurately extract backscattering coefficients for n- and p-FDSOI MOSFETs both in linear and saturated regimes.

A newly designed low-sensitivity, low-bounce, high-linearity current-controlled oscillator (CCO) is described for a single-supply mixed-mode instrumentation system. The sensitivity of the proposed CCO is nearly independent of the power supply voltage that is less than a conventional current-starved oscillator.

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 x 32 and 4 x 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence. Index Terms--MOSFET array, parametric test, probe pads, source biasing, test structure design, variability.

In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current-voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method. Index Terms--Charge carrier mobility, contact resistance, electric variables measurement, MOSFETs.

A temperature-dependent RF large-signal model is constructed by modifying the Verilog-A code of the Angelov model for unique characteristics of GaN MOSHFETs. Different from the previously reported EEHEMT-based model, the present electro-thermal model can fit the temperature effects on threshold shift and transconductance degradation, the drain current in the linear region, and the gate capacitance near the cutoff region. As the result, the power, gain, efficiency, linearity, drain current, and gate current of both Class-A and Class-AB amplifiers are accurately simulated over a wide range of input powers, matching impedances, and ambient temperatures. Index Terms--Gallium compounds, MODFETs, MOSFETs, power amplifiers, pulse measurement, semiconductor device modeling, temperature measurement, thermal resistivity.

As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal-oxide-semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is quantitatively studied. The circuit gain, the 3 dB bandwidth and the unity-gain bandwidth of the tested nanoscale transistor circuit are calculated concurrently capturing the discrete-dopant-number-and discrete-dopant-position-induced fluctuations in the large-scale statistically sound 'atomistic' device/circuit coupled simulation. For the 16-nm-gate MOSFET circuit, the number of discrete dopants, varying from zero to 14, may result in 5.7 % variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4 % variation of the unity-gain bandwidth. To suppress the high-frequency characteristic fluctuations, an improved doping distribution along the longitudinal diffusion direction from the MOSFET's surface to substrate is further performed to examine the associated fluctuation. The improved vertical doping profile with less dopants locating near surface of channel effectively reduces the fluctuations of the circuit gain, the 3 dB bandwidth and the unity-gain bandwidth dramatically. Compared with the original doping profile, the reduction is 32.3%, 19.4% and 51.8%, respectively. This study provides an insight into random-dopant-induced intrinsic high-frequency characteristic fluctuations and verifies the potential fluctuation suppression technique on high-frequency characteristic fluctuations of nanoscale transistor circuit. Index Terms--Characteristic fluctuation, fluctuation suppression technique, high frequency, modeling and simulation, nanometer scale metal-oxide-semiconductor field effect transistors (MOSFET) device and circuit, random dopant effect.

In modern pulsed power systems, often, fast solid-state switches like MOSFETs and insulated gate bipolar transistor (IGBT) modules are used to generate short high power pulses. In order to increase the pulsed power, solid-state switches have to be connected in series or in parallel. Depending on the interconnection of the switches, parameter variations in the switches and in the system can lead to an unbalanced voltage or current. Therefore, the switches are generally derated, which results in an increased number of required devices, cost, and volume. With an active gate control, derating and preselection of the switching devices can be avoided. In this paper, an active gate control of paralleled IGBT modules, which has been developed for converters with inductive load, is explained in detail and adapted to a solid-state modulator. This paper focuses on achieving a low-inductance IGBT current measurement, the control unit implementation with a field-programmable gate array and a digital signal processor, as well as the balancing of the pulse currents. Index Terms--Active gate control, current balancing, insulated gate bipolar transistor (IGBT) modules, printed circuit board (PCB)-Rogowski coil, solid-state modulator.

The mechanism responsible for the dependence of hole mobility on SiGe channel layer thickness is investigated for channel thickness of 1.8nm. Due to the combination of phonon and interface scattering the mobility is found to degrade for channel thickness below 4nm and for SiGe films of channel thickness greater than 2.8nm the scattering is not very significant.

The optimization of a high-voltage superjunction (SJ) power MOSFET by using fabrication based on porous-silicon formation is discussed. The studies have shown that the inclusion of an oxide layer between the p and n columns has helped in increasing the device efficiency in addition to its ability to prevent dopant interdiffusion.

The uncertainties of two commonly used two- and three-step deembedding methods are examined by comparing the RF figures of merit with those of an accurate pad-open-short one in actual 0.13-[micro]m MOSFETs. The deembedding uncertainty of two- and three-step methods is reduced without the pad open pattern by a simple deembedding method by using extrinsic and intrinsic admittances in specific splitting fractions.

Threshold voltage and drain current instabilities in state-of-the-art 4H-SiC MOSFETs with thermal as-grown Si[O.sub.2] and NO-annealed gate oxides are analyzed by using fast I-V measurements. Postoxidation annealing in NO has passivated the oxide traps and has reduced the instability.

The application of double-epilayer structure to two types of testing devices with different pitches is discussed. Findings reveal a significant improvement in unclamped inductive switching (UIS) performance and a reduction in gate-to-drain charge.

A fully three-dimensional (3-D) atomistic quantum mechanical simulation is presented for examining the random dopant-induced effects in nanometer metal-oxide-semiconductor field-effect transistors (MOSFETs). Results suggest an increase in the threshold fluctuation and a decline in threshold lowering due to quantum mechanical effects.

Ultrafast on-the-fly (UF-OTF) technique is used for examining the impact of gate insulator process on negative-bias temperature instability (NBTI). Interface trap dominated degradation is observed in plasma oxynitride films with low interfacial nitrogen density.

A (PSP)-based small-signal metal-oxide-semiconductor field-effect transistor (MOSFET) model is presented. Findings reveal the successful determination of the correct capacitive behavior in the presence of velocity saturation.

This paper introduces a new MOSFET inverter module for driving small brushless dc motors used in fans and water-pump applications. The proposed power module integrates six MOSFETs and three dedicated gate-driving high-voltage integrated circuits (HVICs) in a transfer-molded full-pack package. It provides optimized loss and epoxy molding compound characteristics by using particularly designed MOSFET and dedicated HVIC. This paper describes the package design, the MOSFET, and the HVIC of the proposed module used in motor-drive applications, where power dissipation, electromagnetic interference, and noise immunity are primary concerns. Index Terms--Brushless dc (BLDC) motor, high-voltage integrated circuit (HVIC), inverter module, MOSFET.

A closed-form surface potential solution is obtained for gate oxide-silicon film interface, silicon-film-buried oxide interface and buried oxide-substrate interface of fully depleted silicon-on-insulator (SOI) MOSFETs by considering the effect of substrate charge. Three different equations are obtained by solving the 1-dimension Poisson equation in vertical direction and they are solved for various regions of operations.

The threshold voltage variation in Schottky-barrier (SB) MOSFETs with different geometric parameters as well as devices with dopant segregation is examined. A multigate structure has suppressed the threshold voltage variation by improving carrier injection by reducing its sensitivity to the SB height inhomogeneity.

The effect of MOSFET channel material and channel structure on the inversion layer capacitance is investigated. The results have helped in understanding the channel material and structure standoffs that have controlled the inversion layer capacitance.

The noise mechanisms at high frequencies in MOSFETs are studied and an analytical model is described that is applied to floating body silicon-on-insulator (SOI) MOSFETs. The studies have shown that scaling of the transistor structure will improve transconductance and reduce the noise figure (NF), but at the cost of a reduced operating drain voltage range.

The validity of the parabolic effective mass approximation is examined by computing the ballistic injection velocity of a double-gate, ultrathin-body (UTB) n-MOSFET. The injection velocity has shown strong dependence on the device structure as the thickness of the UTB has changed and it has the same trend as mobility for different surface/transport orientations.

A novel n-channel MOS transistor with a silicon-germanium (SiGe) heterostructure embedded beneath the channel and silicon-carbon source/drain (Si:C S/D) stressors is described. The impact of scaling the device design parameters on transistor drive current and linear transconductance performance is examined.

A high effective work function and a very low [V.sub.t] Ir gate on HfLaO p-MOSFETs is described by using novel self-aligned low-temperature shallow junctions. The gate-first process has shallow junctions of 9.6 or 20 nm that are formed by solid phase diffusion by using Si[O.sub.2]-covered Ga or Ni/Ga.