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Amorphous SiC (a-SiC) films are the most promising dielectric diffusion barriers to replace silicon nitride in Cu-interconnect technology. However, reclaim of wafers with a-SiC films is a challenge issue for mass production. In this paper, a novel wafer reclaim method is proposed. It is observed that a-SiC can be oxidized to Si[O.sub.2] in both dry [O.sub.2] and steam ambients at temperatures as low as 550 [degrees]C. The oxidation mechanism can be described by the Deal-Grove model that is traditionally used to describe oxidation of Si. Experiments prove that the oxidation process is clean and uniform. It is also observed that carbon doped oxide (CDO) films can be oxidized easily, too. Therefore, oxidation followed by HF etching could be a universal process to reclaim wafers deposited with a-SiC or CDO films. Since the oxidation rate of Si substrates at medium temperatures is much lower than that of a-SiC and CDO films, the oxidation process is virtually self-limiting. Compared with a traditional reclaim method based on wafer polishing, this universal oxidation-etching method exhibits great benefits in terms of low cost, high throughput, and the ability to perform nearly unlimited numbers of reclaim cycles. Index Terms--Amorphous silicon carbide, low dielectric constant, wafer reclaim.

Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process developing is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between inter-metal-dielectric and SACL material are preferred. The SACL thickness in via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16[micro]m. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13-[micro]m technology node. Index Terms--Copper, dual-damascene, interconnections.

The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N+/P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V. [ABSTRACT FROM AUTHOR]

Electrical instabilities of a-SiC:H film during electric-field stress are examined. A dialectric polarization model is proposed to explain high electric-field instability.

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

Numerical simulations are conducted to investigate the effect of contact interface recession on the external resistance of self-aligned silicided (salicide) source/drain structures. It is shown that the silicidation mechanismcauses a rise in resistance that may be in the order of several hundred ohms-micrometers. The simulated results are then compared to reported measurements of external resistance for which a 20% error is found.

Experimental results of a study investigating the influence of fluorine contained in ions implanted into platinum silicide structures are reported. Both implantation-through-metaland implantation-through-silicide cases are analyzed to analyze the high-temperature stability obtained through flourine inclusion. A fluorine-buffer model is developed to account for the improvement and a hypothesis concerning the Si-F layer's role is proposed. Fabricated Schottky junctions with and without fluorination are also evaluated.

In this article, the degradation mechanism of the Ge N+-P junctions with a thin GeSn surface layer is investigated, aiming for source/drain (S/D) application in emerging field-effect transistors. GeSn is a promising channel material with high carrier mobility, which can offer a better performance of the field-effect transistors. By performing thermal annealing at different temperatures, the reverse-biased leakage current increases apparently when annealing temperature exceeds 550 °C. X-ray diffraction (XRD) analysis indicates most Sn atoms escape from lattice sites while secondary-ion mass spectroscopy (SIMS) analysis indicates enhanced Sn diffusion in Ge bulk after ion implantation. Therefore, a degradation model considering Sn-defects interaction is proposed to explain the degradation of junction leakage current and possible solution is proposed. [ABSTRACT FROM AUTHOR]

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control. [ABSTRACT FROM PUBLISHER]

The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunneling orientation was proposed. The ETL structure performs more favorably than does the traditional lateral tunnel FET structure in an all-silicon device. By using low bandgap materials in the ETL, the ON-state BTBT current increases and an extremely low intrinsic OFF-state current is maintained because of the small low bandgap junction area. The onset voltage of the bipolar BTBT can also be postponed using ETL band engineering. The optimized parameters of the Six\rm Ge1\-{\rm x} ETL tunnel FET structure increase the ON-state current 10^7\--10^8 times compared with that of the traditional lateral silicon tunnel FET. The minimal subthreshold swing (SS) and ON/OFF current ratio also improve, the SS decreases from 47 mV/decade to 29 mV/decade, and the ON/OFF current ratio increase from 10^5 to 10^10. In this paper, the effects of the ETL parameters on device performance are discussed in detail. [ABSTRACT FROM PUBLISHER]

Fringing-induced barrier lowering (FLBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, shod sidewall spacer, and minimum gate/drain (G/D) overlap, the Ioff with a dielectric constant of (k) 100 is only 1.6 times higher than that with k = 3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FLBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node. [ABSTRACT FROM AUTHOR]