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International audience; The interactions of a moving crack with self-emitted acoustic waves are studied in ion-implanted circular plates of crystalline silicon, where complex reproducible surface patterns made of local roughness variations are observed. A simple geometrical model, considering the sole propagation of A0 Lamb waves inside the assembly, allows full prediction of all of these pattern shapes and their dependence on system parameters (crack velocity, elastic properties). Acoustic waves propagating along and behind the crackfront are shown to play a central role in fracture-pattern formation. When the crack front is curved, surface patterns originate independently of any edge reflection or frequency preselection from acoustic waves propagating along and behind the crack. As in case of Kelvin wake patterns, fracture patterns emerge from geometrically induced coherence.

3D analysis of an arsenic-doped silicon fin sample is performed in a transmission electron microscope (TEM). High angle annular dark-field scanning TEM (STEM-HAADF) and energy-dispersive x-ray spectroscopy (STEM-EDX) modes are used simultaneously to extract 3D complementary multi-resolution information about the sample. The small pixel size and angular step chosen for the STEM-HAADF acquisition yield reliable information about the sidewall roughness and the arsenic clusters’ average volume. The chemical sensitivity of STEM-EDX tomography gives insights into the 3D conformality of the arsenic implantation and its depth distribution. Non-negative matrix factorization method is employed to identify the chemical phases present in the sample automatically. A total variation minimization algorithm, implemented in 3D, produces high-quality volumes from heavily undersampled datasets. The extension of this correlative approach to electron energy-loss spectroscopy STEM tomography and atom probe tomography is also discussed.

In this paper, Y+163°-cut LiNbO 3 (LNO) Film Bulk Acoustic Resonators (FBAR) with patterned bottom electrodes (AlSi or W) and a sacrificial layer cavity have been fabricated using a layer transfer process (4-inch). Unlike previous work based on films oriented towards the X axis [1], the Y+163° orientation provides a single resonance at 2.2 GHz, with an effective electromechanical coupling factor (k t 2) of 26 %. Thanks to this single mode behavior and to the energy trapping induced by the heavy tungsten electrodes, the quality factor at antiresonance (Q a ) is increased to 600. Moreover a Temperature Coefficient of Frequency (TCF) of –45 ppm/°C is obtained. This demonstrates a significant improvement towards introducing LiNbO 3 as an alternative to AlN in Bulk Acoustic Wave (BAW) filters for the new generation of RF filters.

International audience; Vibrations induced by crack propagation in a strip of bonded silicon wafers are studied. A new optical setup enables the fast recording of crack-originated acoustic waves, emitted both ahead and behind the crack front, in bonded and separated wafers, respectively. Three types of crack-induced vibrations are identified, corresponding to different excitations and responses of the system: (1) “pneumatic” vibrations involving inertia and gas expansion/compression, (2) standard flexural waves involving inertia and bending rigidity, and (3) post-crack vibrations involving inertia, bending rigidity, and coupling to gas pressure. We show that a standard “beam on elastic foundation” model can explain these latter vibrations that occur along crack edges and is consistent with the observed frequencies.

International audience; MeV energy hydrogen implantation in silicon followed by a thermal annealing is a very smart way to produce high crystalline quality silicon substrates, much thinner than what can be obtained by diamond disk or wire sawing. Using this kerf-less approach, ultra-thin substrates with thicknesses between 15 pm and 100 pm, compatible with microelectronic and photovoltaic applications are reported. But, despite the benefits of this approach, there is still a lack of fundamental studies at this implantation energy range. However, if very few papers have addressed the MeV energy range, a lot of works have been carried out in the keV implantation energy range, which is the one used in the smart-cut (R) technology. In order to check if the nature and the growth mechanism of extended defects reported in the widely studied keV implantation energy range could be extrapolated in the MeV range, the thermal evolution of extended defects formed after MeV hydrogen implantation in (100) Si was investigated in this study. Samples were implanted at 1 MeV with different fluences ranging from 6 x 10(16) H/cm(2) to 2 x 10(17) H/cm(2) and annealed at temperatures up to 873 K. By cross-section transmission electron microscopy, we found that the nature of extended defects in the MeV range is quite different of what is observed in the keV range. In fact, in our implantation conditions, the generated extended defects are some kinds of planar clusters of gas filled lenses, instead of platelets as commonly reported in the keV energy range. This result underlines that hydrogen behaves differently when it is introduced in silicon at high or low implantation energy. The activation energy of the growth of these extended defects is independent of the chosen fluence and is between (0.5-0.6) eV, which is very close to the activation energy reported for atomic hydrogen diffusion in a perfect silicon crystal. (C) 2017 Elsevier B.V. All rights reserved.

Improving the thermal stability of Ni/GeSn intermetallics is of great importance to avoid surface degradation and Sn segregation. For this purpose, we studied the effects of pre-amorphization by ion implantation (PAI) of GeSn layers prior to metallization. The impact of Si, Ge, C, or Ge + C PAI was evaluated in terms of phase sequence, morpohological, and electrical evolution during the solid-state reaction. The overall phase sequence, followed by in situ x-ray diffraction, was comparable with or without PAI and went as follows: the Ni 5(GeSn) 3 hexagonal phase was obtained first, followed by the mono-stanogermanide phase: Ni(GeSn). Nevertheless, the threshold temperature for phase formation varied. These variations, depending on the nature of the implanted ions, can be related to kinetic and/or thermodynamic factors as supported by the analysis of bibliography for silicides and germanides. Additionally, it was reported that the use of Si or Ge implantation did not significantly impacted the surface morphology of the layers. On the other hand, the implantation of C positively impacts the surface morphology evolution by delaying Sn long-range diffusion and Ni(GeSn) agglomeration. This trend was then highly beneficial for preserving electrical stability in an enhanced process window.

The use of plasma immersion ion implantation (PIII) is a relevant approach for the development of advanced solar cells technologies at lower cost (€/W p ). In this paper, we report on the development of homogeneous boron (B) doping of n-type crystalline silicon (cSi) substrate by the PIII technique. Using diborane (B 2 H 6 ) as gas precursor, various doping profiles were identified fitting the requirements for boron-doped emitters in n-type PERT solar cells. Particularly, saturation current density (J 0e ) of 50 fA/cm 2 were achieved on symmetrical samples for a 94 Ω/sg textured B-emitter passivated with SiO 2 /SiN stack. Bifacial n-type Passivated Emitter Rear Totally-diffused (n-PERT) solar cells were fabricated using the PIII technology and conversion efficiencies up to 19.8% on 239 cm 2 Cz-Si wafers were obtained. As a consequence, these results indicate that PIII can compete with beamline technology but will have lower running cost. It is therefore a promising technology to create high efficiency cSi solar cells.

3D sequential integration enables the full use of the third dimension thanks to its unique contact density far above the possibilities of 3D packaging solutions. However, as the transistors are sequentially stacked over each other, the thermal budget allowed for the fabrication of the top transistor is limited by the maximal temperature accepted by the already made bottom one. It was previously described that a thermal budget of T > 500 °C is enough to degrade the bottom transistors performance. So the technological challenge is to develop low temperature routines for the fabrication of the top devices. For that, different processes have to be adapted, mainly the dopant activation step, where the T > 1000 °C spike annealing must be replaced. In this contribution, we present the feasibility to dope by solid phase epitaxial regrowth (SPER) at 450 °C thin Si films (22 nm) containing high dopant concentration of 5 × 10 20 at/cm 3 . For n- and p-type dopants, the 450 °C SPER rendered low sheet resistance values, as low as the ones obtained with the high temperature activation method.

International audience

International audience; The interaction of a propagating crack in implanted silicon with self-emitted acoustic waves is studied and reveals the generation of periodic patterns on wafers surfaces after separation. The measurement and identification of the acoustic waves have been experimentally achieved showing the emergence of dominant shear waves acoustic frequencies related to the crack velocity. The surface modifications are made of roughness modulations at large scale due to periodic deviations of the crack front. A physical mechanism explaining the pattern formation is proposed accounting for the observed wavelengths.

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

Localized p-doping is a keystone in the development of many GaN based devices that need selectively doped pocket area such as MOSFETs or PIN diodes. Electrical activation of implanted Mg has been obtained lately with GaN grown on sapphire substrate using an AlN based protective layer combined with multi cycle of rapid thermal annealing at very high temperature (>1300 °C) proving the feasibility and interest of the method [1]. The use of Si (111) substrate allows a better integration of the process on microelectronic production line. However the growth of GaN on Si (111) is less mature and necessitates a buffer usually composed of a complex staking based on AlN intermediate layers [2]. The difference in lattice parameters and thermal extension coefficient in the stacking may make the samples more unstable during the high thermal budget required for doping activation. In the last few years, several groups focused their research on the prevention of GaN surface degradation at high temperature [3] and we have shown that a combination of in situ epi deposited AlN and SiN thin layers is very efficient to avoid this phenomena [4]. Here, we propose to study the impact of high thermal annealing on the evolution of the damage in Mg-implanted GaN (on Si). Indeed, comprehensive studies of the GaN healing mechanism in this kind of structures are not yet reported. We use samples of GaN layer grown by MOCVD on Si (111) using an AlN based buffer layer and protected by an AlN/SiNx cap layer. These samples are implanted with Mg fluences ranging from 1013 to 1015 at/cm² corresponding to maximum effective concentration between 5.1017 and 5.1019 at/cm3 in the implanted layer. 400 °C -1100 °C anneals are proceeded in controlled N2 atmosphere. X-Ray Diffraction (XRD) and Photoluminescence (PL) measurements point out that ion implantation induced damage are healed thanks to different mechanisms: both lattice strain relaxation and point defect annihilation can occur during annealing with different kinetics. Indeed as we can see on Fig.1a, on samples implanted with low to medium fluence (up to 1014 at/cm²), relatively low temperature anneals (< 450 °C) are enough to obtain a near complete correction of the lattice deformation. However, surprisingly, the PL spectra of 400 °C annealed samples shown on Fig1.b indicates that a lot of non-radiative defects are still present and shutting down the PL intensity. The spectra of the sample annealed at 1100°C exhibits bands characteristic of Mg in Ga site (Mg(Ga)) which proves the necessity of a higher thermal treatment to reduce non radiative defects concentration and promote Mg incorporation in the GaN lattice. As shown on Fig 2.a, an increase of the fluence (1015 at/cm²) leads to an increase of the induced strain but also of the temperature necessary to fully relax it (1100°C). However, the PL spectra (Fig 2.b) indicates that even after such a high thermal treatment, the PL intensity of the bands associated with Mg(Ga) is weaker than for medium fluence despite the higher Mg concentration in the matrix [4]. We assume that this behavior may be due to residual damage. This is supported by Transmission Electron Microscopy images of the layer (not shown here) that evidence remaining defective pockets after a 1 h 1100 °C in N2 annealing. These results give insight on the healing mechanism occurring during the activation anneal of Mg implanted in GaN. They also highlight that damage management is a critical parameter for GaN (on Si) p-doping via Mg implantation. To reach this objective, we will show that it is necessary to implement further specific processes to limit the implantation induced damage and to improve the damage recovery efficiency. 1. Tadjer, M.J., et al., Selective p-type Doping of GaN:Si by Mg Ion Implantation and Multicycle Rapid Thermal Annealing. ECS Journal of Solid State Science and Technology, 2015. 5(2): p. P124-P127. 2. Charles, M., et al., The effect of AlN nucleation temperature on inverted pyramid defects in GaN layers grown on 200 mm silicon wafers. Journal of Crystal Growth, 2017. 464: p. 164-167. 3. El-Zammar, G., et al., Surface state of GaN after rapid-thermal-annealing using AlN cap-layer. Applied Surface Science, 2015. 355: p. 1044-1050. 4. Lardeau-Falcy, A., et al., Capping stability of Mg-implanted GaN layers grown on silicon. physica status solidi (a), 2016. Figure 1

H implantation in Si/Si:B/Si structures is a promising route to improve the Smart Cut™ process and transfer thin Si layers of reduced roughness and controlled thickness onto regular Si wafers. However, the mechanisms driving this process are unknown and thus difficult to model or optimize. For this reason, we have experimentally studied the redistribution of H which takes place in such structures after implantation and during annealing using SIMS and TEM. We show that the Si:B layer already traps H during implantation and form platelets parallel to the wafer surface. During annealing, the H atoms implanted in the Si regions are slowly transferred toward the Si:B layer where they are trapped on large platelets which grow further during annealing. Routes to optimize this process go through the minimization of H precipitation in the pure Si regions. This can probably be achieved by optimizing the implantation conditions.

International audience; Production costs and energy efficiency are the main priorities for the photovoltaic (PV) industry (COP21 conclusions). To lower costs and increase efficiency, we are proposing to reduce the number of processing steps involved in the manufacture of N-type Passivated Rear Totally Diffused (PERT) silicon solar cells. Replacing the conventional thermal diffusion doping steps by ion implantation followed by thermal annealing allows reducing the number of steps from 7 to 3 while maintaining similar efficiency. This alternative approach was investigated in the present work. Beamline and plasma immersion ion implantation (BLII and PIII) methods were used to insert n-(phosphorus) and p-type (boron) dopants into the Si substrate. With higher throughput and lower costs, PIII is a better candidate for the photovoltaic industry, compared to BL. However, the optimization of the plasma conditions is demanding and more complex than the beamline approach. Subsequent annealing was performed on selected samples to activate the dopants on both sides of the solar cell. Two annealing methods were investigated soak and spike thermal annealing. Best performing solar cells, showing a PV efficiency of about 20%, was obtained using spike annealing with adapted ion implantation conditions.

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.

We have studied the development of cracks in gas-implanted silicon, from nano-scale to wafer-scale which is at the heart of the SmartCut™ technology. We will discuss the results of X-ray scattering experiments that allow the monitoring of growth of nanometer-size cavities (platelets) from implantation to their full development where they reach sizes of several tens of nanometers. The nucleation, growth and coarsening mechanisms of these nanometer size platelets are interpreted within the Ostwald ripening framework. At larger annealing times, some micron-size defects called microcracks appear, and experience again some competitive growth, dominated by coalescence. The growth of these micron-size objects depends on their interactions with smaller-size platelets. The modelling of this interaction can explain the dependance of split time with temperature. Microcrack development is a key step in the SmartCut™ process. Finally the propagation of the fracture front will be discussed. We will discuss the velocity dependence of the crack front with temperature and present some new measurements of dynamic crack opening displacement. Figure 1

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

In this paper, we report on implantation parameters allowing the delamination of large surface of ultra-thin silicon substrates by using MeV hydrogen implantation. We particularly focus on the effects of both hydrogen fluence and implantation energy, on the size of the largest delaminated surface in one piece. We demonstrate that thin silicon substrates with thicknesses between 30 µm and 70 µm can be extracted from silicon commercial wafers. In this study, the used-material, the implantation energy and the hydrogen fluence ranges are (100) Si, 1.5 MeV-2.5 MeV, 1×1017cm–2-2×1017cm–2, respectively. We find that, by increasing hydrogen fluence, the maximum achievable surface of delaminated substrates in one piece can be doubled. Indeed, by XTEM, we observed that fracture precursor defects are mostly oriented along {111} in the case of the lowest fluence, which are unfavorable for a good surface-parallel crack propagation. For the highest fluence, precursors are oriented along {100} which are parallel to the substrate surface, therefore they allow propagation over longer distances of cracks parallel to the substrate surface. We also find that, despite of the raise of the proportion of precursors oriented along {111}, the total surface of delaminated substrates significantly increases with the implantation energy. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The doping of n-type silicon solar cells was investigated using two ion implantation techniques: beam line and plasma immersion. Initially, we evaluated the benefits of beamline ion implantation in replacement of diffusion anneal doping process. Two different annealing routines were studied. The first one using a single annealing to activate both B implanted emitter and P implanted BSF, while the second one used two different annealing to separately activate each dopant. Good yield was reached with a record cell of 20.33% efficiency. Secondly, we investigated the doping by plasma immersion ion implantation where the final objective was the fabrication of a solar cell fully doped by plasma. BF3 and B2H6 were compared as precursor gases for the boron emitter doping, while PH3 was used for the BSF doping. Hybrid cells were fabricated using both implantation techniques and a maximum efficiency of 19.8% was obtained. First cells fully doped by plasma shown promising results with a yield of 18.8%.

This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III–V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III–V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III–V compound interface.

International audience; Crack propagation in implanted silicon for thin layer transfer is experimentally studied. The crack propagation velocity as a function of split temperature is measured using a designed optical setup. Interferometric measurement of the gap opening is performed dynamically and shows an oscillatory crack "wake" with a typical wavelength in the centimetre range. The dynamics of this motion is modelled using beam elasticity and thermodynamics. The modelling demonstrates the key role of external atmospheric pressure during crack propagation. A quantification of the amount of gas trapped inside pre-existing microcracks and released during the fracture is made possible, with results consistent with previous studies. (C) 2015 AIP Publishing LLC.

We present a study of the influence of H2 as a carrier gas on the nucleation and growth of silicon quantum dots (Si-QDs) on SiO2 by chemical vapor deposition (CVD). Compared to deposition from pure SiH4, the dilution of SiH4 in H2 leads to a strong decrease of the nucleation/growth rate, with the same Si-QDs morphology however. The effects of doping gas, phosphine and diborane, on Si-QDs nucleation and growth were also investigated. Silanol groups at the SiO2 surface were identified as nucleation sites for Si-QDs. We study the influence of H2 and doping gases on their activity toward Si-QDs nucleation.

The morphological stability during activation annealing of Mg-implanted GaN layers (2 μm thick) grown on Si (111) is studied for several protective layers and fluencies in the 1013–1015 at. cm−2 range. We show that a thin capping, composed of a few nanometer thick AlN and SiNx stacks grown in situ just after GaN deposition, provides a good solution to retain flat morphology and no strain cracking up to 1 h annealing at 1100 °C in N2. These results are compared to thicker protective stackings with AlN layers of Si3N4 or SiO2 deposited after the implantation that withstand a thermal budget of up to 1 h at 1200 °C in N2. The efficiency of these different cap layers to limit GaN damage during high-temperature annealing is studied as well as the impact of Mg implantation process on the cap resilience. The quality of the GaN sublayer is studied by low-temperature photoluminescence to analyze structural/optical defects and Mg related complexes. X-ray diffraction is performed to evaluate residual strains at the different process stages.

Nonvolatile memory structures using Ge nanocrystals embedded in SiO2 have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of nc-Ge density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that nc-Ge are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (>10 nm) seems to be a promising way for p-type ...

Substrate Requirements & Product Roadmap Bulk silicon device technologies are reaching fundamental performance scaling limitations. To support Fully-Depleted SOI design introduction at 28nm node, SmartCut® technology has demonstrated in the past years its capability to deliver ultra-thin SOI (i.e ultra-thin silicon and ultra-thin buried oxide) substrates, in volume production mode with high quality and ultra-low roughness. [1, 2] These UTBOX (or UTBB) materials are routinely prepared with a typical SOI layer of 12nm thick controlled wafer to wafer and across the wafer at maximum +/- 0.5 nm. Buried Oxide layer can be thinned down to 10nm. Silicon on Insulator technology can also be adapted for other device architectures, such as FinFet on SOI. However, even if Silicon & Fully Depleted technology can support the electrostatic scaling down to 14nm node, material innovation is necessary for advanced technologies such as node 10nm and beyond. Strained-SOI material already demonstrates some of its substrate capability [3], performance benefit [4] and integration advantages [5] for 10nm FDSOI MOSFET. High mobility is also targeted using Germanium-rich materials, already known for extremely high hole mobility and low hole effective mass. [6] Thus SiGeOI material is included in product roadmap, as shown on Figure 1. This paper will report latest achievement in sSOI, GeOI, & SiGeOI materials preparation, developed to support technology nodes beyond 10nm. Substrate Preparation Fig. 2 shows typical SmartCut ® process, adapted for sSOI, GeOI & SiGeOI material preparation. It benefits of previous FDSOI developments optimizing buried oxide growth, ionic implant, bonding & splitting process steps for highly uniform thin layer transfer. It introduces engineered donor wafer including SiGe and/or strained-silicon Epi layers. Refresh process is also adjusted, to be able to re-use donor epitaxy, optimizing material cost & quality. During finishing process, specific steps including polishing, thermal treatment & cleanings are introduced to manage stress & germanium. GeOI Substrate Demonstration Fig. 3a shows TEM cross section of GeOI material, including 10nm Oxide capping, 60nm Ge layer and 150nm Buried Oxide. No crystal defect is observed by cross-sectional TEM. Using chemical etching for defect delineation, Threading Dislocation density, numbered from optical microscope view as on Fig. 3b, is estimated in E7 cm-2range. SiGe0.70OI Substrate Demonstration Germanium concentration on finished product, 70% on current development samples, is determined by donor epitaxy layer.To ensure tight thickness control, in addition to excellent Epitaxy uniformity & optimized SmartCut process, SiGeOI finishing process step implements the selective chemical etching instead of using the substantial polishing removal process as previously reported for GeOI substrate preparation.[7] As shown in Fig. 4a, it enables to reach the SiGe layer uniformity better than +/- 8% on 300mm substrates. Finished SiGeOI surface roughness is also characterized using 30x30 µm² AFM with a RMS value lower than 3 A (Fig. 4b). References [1] W. Schwarzenbach et al., ECS Trans., vol. 45, p.227, 2012 [2] W. Schwarzenbach et al., ECS Trans., vol. 53, p.39, 2013 [3] W. Schwarzenbach et al, ICICDT 2012 [4] A. Khakifirooz et al, VLSI Symp. 2012 [5] F. Andrieu et al, VLSI Symp. 2014 [6] S. Takagi, IEEE TED, 2008 [7] J. Widiez et al, ECS Trans., Vol. 64, p 35, 2014 Figure 1

We have developed a two steps chemical vapor deposition (CVD) process which permits to dissociate the nucleation and the growth of silicon nano-crystals. In the first step, silicon “clusters” of a diameter below 1 nm are nucleated by exposure of the SiO2 substrate to SiH4. In the second step, these clusters are grown selectively using SiH2Cl2 as silicon precursor. TEM analysis shows that the silicon quantum dots (Si-QDs) obtained with this process are mono-crystalline. The main advantage of this two steps process is that the size dispersion is sharpened compared to a standard one step process because of the dissociation of the nucleation and the growth of the Si-QDs.

International audience; Ultrahigh vacuum atomic force microscopy has been used to inject and detect charges in individual silicon nanocrystals. The sensitivity of our measurements is shown to be better than 2e. Injected charge saturates as a function of injection time for a given electric field. The potential of the charged nanocrystal as a function of the number of charges in the dot is in good agreement with a simple electrostatic model.

In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

3D Sequential Integration (3DSI) with ultra-small 3D contact pitch (

The impact of dual Ge/C pre-amorphization implantation (PAI) processes on the Ni0.9Pt0.1(7 nm)/Si system phase sequence has been investigated by advanced X-ray diffraction techniques and transmission electron microscopy (TEM). Using a high carbon implantation dose, it is found that the expected development of Ni-rich phases is not observed: a thick amorphous Ni1−xPtxSi layer developed until Ni0.9Pt0.1 full consumption, followed by the development of a thin crystalline Ni1−xPtxSi layer along the TiN interface. By increasing the temperature further, this last one abruptly thicken, creating the final silicide layer. An alternative model to grain boundary diffusion is discussed, accounting for the final distribution of the foreign species within the silicide layer. The use of Ge in dual Ge/C PAI processes is proposed to impact the growing mechanisms by alloying to fine-tune the carbon distribution in the substrate sub-surface.