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ASIC advances are forcing us to make radical changes in the way we simulate and sign off silicon. To keep pace with increasing complexity and to achieve the timing accuracy […]

If you examine your design requirements, design-cycle time application and end-use objectives, you should be able to select a complex PLD or FPGA that satisfies your most important requirements. With […]

Is BIST the best strategy for embedded memory? Will the overhead for testability be worth it? What are the testability issues for analog blocks? How important is at-speed emulation for […]

The use of FPGAs is growing explosively, forcing veteran programmable logic vendors to enhance performance with new-generation products. At the same time, more semiconductor giants are being tempted to enter […]

Still dealing with custom more than semicustom, analog designers plod along the trail without the help of synthesis, a standard analog HDL or test methodology. But the determined can still […]

Although testability is finally getting the respect it deserves from both vendors and users, it's clear that if you're designing testability into complex ASICs using today's tools, you'll still have […]

Recent advances in high-level synthesis technology and system verification through reprogrammable hardware emulation have pushed in the direction of hardware/software codesign and promise to enhance your ability to bring error-free […]

High-density ASICs force focus on testability High gate counts and maturing software tools have changed the economics of ASIC design. While ever-more-sophisticated tools have automated other tasks, the reliance on […]

Are mixed cells and arrays the solution ASIC vendors claim? As customers clamor for shorter turnaround times for complex ASIC designs, silicon vendors are pushing the practice of putting down […]

The elongated run times of increasingly complex IC and board designs have forced silicon and software vendors alike to chase after network-distributed processing. ASIC designers are finally getting a taste […]

Caught up in the integration race, ASIC vendors have pushed silicon beyond the design, assembly and test resources of most OEMs. Advanced processes with submicron geometries have brought to market […]

Test can be likened to the middle child; it's given no attention until it causes problems While the more glamorous aspects of the ASIC design cycle have held the industry […]

Because silicon is only as competitive as the tools used to design it, vendors involved in the hot FPGA and complex PLD market have been scurrying to deliver what they […]

To a market taken with programmable technologies such as PROMs, FPGAs and PLDs, VLSI Technology (San Jose, CA) has introduced a new concept in programmability: programmable functional system blocks (pFSBs) […]

The complexity of both silicon and the systems into which it's going is forcing designers to higher levels of abstraction for complex ASICs, and the use of synthesis is putting […]

Leading ASIC vendors have been preparing for the rush to notebook, palmtop and penbased computers by introducing low-voltage cell-based and gate array products. Among the latest to turn out 3-V […]

When looking for high-fault-coverage test programs, you have to decide if you're willing to support full scan, or if a back-end approach will be less intrusive. Mentor Graphics (Wilsonville, OR) […]

So far, VHDL's user acceptance is still behind that of Verilog, which is perceived to be a de facto industry standard. Core issues such as the lack of tools and […]

CrossCheck testability reaches commercial gate array family It took longer than expected, but, more than three years after CrossCheck Technology (San Jose, CA) was founded, the first commercial silicon implementation […]

Chase for process portability prompts advances in cell library tools With the trend toward technology-independent design, library developers require parameterized cell representations that can be modified and reused as design […]

A new floorplanning tool for submicron gate arrays, Compass Design Automation's ChipPlanner gives ASIC vendors and designers placement and timing analysis features that bridge the gap between design intent and […]

Processed in Hewlett-Packard's production-proven 0.8-(micro)m CMOS technology, Actel's ACT 3 FPGAs share the PLICE antifuse interconnect technology of ACT 1 and 2 devices, but capitalize on improvements in the circuit […]

Prism from NeoCAD is the first timing-driven software tool to provide automatic post-map partitioning of logic functions into multiple FPGAs in the same family. Available as an option to the […]

With real technological innovation apparently stalemated, suppliers of design automation tools are zeroing in on business opportunities that fall under the category of services. Vendors have discovered that it takes […]

Anticipating how much impact any new technology will have on the industry is always difficult, especially if that technology is high-priced and perceived by the user as risky. But a […]

For use at both customer sites and at Gould AMI, the new Mixed-Signal Design Solution (MSDS) incorporates analog model generators as well as analog design-for-testability features. Gould AMI claims that […]

The bottom line in the programmable device market is to give designers the fastest time-to-market with the highest-speed device. The founders of Peer Research, now QuickLogic (Santa Clara, CA), having […]

Aimed at high-end ASIC designers using deep submicron technologies, the SimLine Verilog HDL simulator from FrontLine Design Automation has several characteristics that distinguish it from Verilog-XL and other Verilog HDL […]

A new behavioral synthesis tool developed by Synopsys can be used for virtually any design that can be described by an algorithm. The Behavioral Compiler is targeted at time-to-market-sensitive ASIC […]

For pre-silicon prototyping, the Enterprise Emulation System from Quickturn Systems (Mountain View, CA) is based on a multiplexed architecture that's separated into logic emulation modules and a reprogrammable backplane. You […]

Two weeks ago, Oki Semiconductor (Sunnyvale, CA) announced the 0.8-[unkeyable]m CMOS three-layer metal MSM30S0000 sea-of-gates arrays, with up to 225,000 gates, of which 135,000 are usable. Based on Oki's first-generation […]

The 300K ASIC family from LSI Logic is based on a 0.6μm CMOS process and has up to 600,000 usable gates per device. The family includes gate array, cell-based and […]

A 6,000-gate programmable logic device (PLD) from Latice Semiconductor, claimed to have a maximum system-level performance of 80 MHz with a 15-ns propagation delay, is available in two versions: a […]

The altera N-to-1 mask-programmed logic device can merge up to 40 erasable programmable logic devices that have been used for prototyping and early production into a single MPLD for volume […]

The ANAsim mixed-mode simulator from ANAmation integrates relaxation and event-driven methods to simulate analog and digital circuits with a single engine. Witn ANAsim, users don't have to designate circuit elements […]

JEDEC committee proposes standard ASIC terminology Rapidly changing ASIC design technology has led the industry to a point where a friendly discussion on the state of the art can lead […]

Software lets ASIC designers compare FPGAs up front A new translation package from Exemplar Logic promises to be a cost-effective aid for ASIC designers. The FPGA Compiler lets designers analyze […]

Users want migration path The energy level in Silicon Valley is at a more-fevered pitch than usual. And most of that energy is connected in some way to field-programmable gate […]

The balancing act of choosing an ASIC ASIC designers know that the first vendor to market with silicon captures the lion's share of volume and profits. When choosing an ASIC […]