40 results on '"Tuck, Barbara"'
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2. Be ready to make trade-offs when selecting a programmable architecture
3. Testing fully diffused blocks embedded in complex ASICs
4. Vendors vying for FPGA market try different strategies
5. Analog designers still trail behind their digital counterparts
6. ASIC testability tools force trade-offs in silicon, performance and coverage
7. Technologies move toward hardware/software codesign
8. High-density ASICs force focus on testability; getting an ASIC of 20,000-plus gates to market on time means building testability into the design flow
9. Are mixed cells and arrays the solution ASIC vendors claim? Does embedding fully diffused blocks on gate arrays
10. Network-distributed processing reduces run times for complex designs
11. European consumer products replete with mixed-signal, DSP technology
12. High-density gate arrays: products too far ahead of technology?
13. Is synthesis the solution for testing complex ASICs?
14. FPGA, complex PLD vendors rush to support silicon with advanced tools
15. VLSI uses ViaLink antifuse to embed programmability into ASICs, ASSPs
16. EDA leaders getting serious about automatic test generation
17. ASIC choices increase for mixed 3-V/5-V designs
18. Choices expand to incorporate design for testability
19. VHDL poised to overtake Verilog as support grows
20. CrossCheck testability reaches commercial gate array family
21. Chase for process portability prompts advances in cell library tools
22. Vendor-independent floorplanner links synthesis with ASIC layout
23. Improved FPGAs deliver fast, predictable performance
24. Timing-driven partitioning tool splits design into multiple FPGAs after mapping
25. EDA vendors push to boost top-down design productivity
26. CrossCheck testability solution extended with interface to ATE
27. Mixed-signal ASIC toolset offers analog design for testability
28. Interconnect key to speed of new programmable ASICs
29. Verilog HDL simulator targets deep submicron ASIC designs
30. Behavioral synthesis tool generates state machine controller, datapath and memory
31. Prototyping system emulates up to six million gates
32. Oki enhances sea-of-gates performance
33. 0.6-(micron) CMOS ASICs offer system performance solutions
34. High-density PLD runs 80 MHz, programmable in-system
35. Mask-programmed device integrates up to 40 EPLDs
36. Implicit mixed-mode simulation for analog/digital ASICs
37. JEDEC committee proposes standard ASIC technology
38. Software lets ASIC designers compare FPGAs up front
39. Users want migration path
40. The balancing act of choosing an ASIC
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