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We present an interpretation of conventional figure-of-merit (FOM) and average input-referred noise current density (IRNCD) that characterizes optical receivers to determine how technologies and circuits best address energy efficiency. A design methodology is presented for differential optical receivers based on Cherry-Hooper Emitter Follower (CHEF) front-end designs targeting 56-Gbps applications is realized in a 130-nm SiGe BiCMOS process. The electrical measurements in a 50- $\Omega$ environment demonstrate data rates up to 112 Gbps and 84 Gbps for two design variants. In an open input and maximum gain configuration, the rms input referred noise currents are 3.59 $\mu$ $A_{RMS}$ and 2.41 $\mu$ $A_{RMS}$ and the corresponding average input referred noise current densities are 17.25 $pA/\sqrt{Hz}$ and 12.86 $pA/\sqrt{Hz}$. The packaged electro-optical measurements of the receiver variants is carried out with a single commercial off-the-shelf (COTS) photodetector demonstrate open eyes at data rates up to 64 Gbps. At 60 Gbps, the receiver variants achieve a $BER < 10^{-10}$ and $BER < 10^{-9}$. The total power consumption for the variants are 162 mW and 138 mW for overall energy efficiencies (with respect to electro-optical performance) of 2.53 $pJ/bit$ and 2.3 $pJ/bit$. [ABSTRACT FROM AUTHOR]

We present a comparison of design trade-offs for transimpedance, sensitivity, DC voltage offset cancellation, group-delay variation (GDV), common-mode rejection, and overload for transimpedance amplifiers (TIA) based on balanced, unbalanced, and pseudodifferential topologies. The TIAs are implemented monolithically in the IHP 250-nm SiGe BiCMOS EPIC process (fT = 190 GHz). Measurement results shown here support data rates to 50 Gb/s with BER better than 10−10. The power consumption of the TIAs is 54 mW for TIA designs that approach 1 pJ/b. [ABSTRACT FROM AUTHOR]

A code-domain transceiver front end that incorporates a transmit modulator and a receive (RX) RF signal correlator is presented. An integrate-and-dump $N$ -path filter improves rejection by 8 dB. We propose an RF chopper switch with 12.1-/23.1-dBm P1dB/IIP3 for both RF correlation and filtering that rejects TX self-interference by 49.5 dB. Walsh and Barker codes are generated with fine and coarse tuning for synchronization. The RX power consumption is 18 mW, including dynamic power (1-V supply) and four analog amplifiers (1.5 V) at the operating frequency of 1 GHz and the code rate of 200 megachip-per-second (Mc/s). The TX modulator operates to RF power levels up to 34.3 dBm and consumes less than 40 mW for 300 Mc/s. Over the air testing demonstrates synchronization with Barker codes. [ABSTRACT FROM AUTHOR]

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch. [ABSTRACT FROM AUTHOR]

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ($\lambda /4$) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

This paper presents an explicit analysis of the bandwidth and port imbalance of a subquarter-wavelength transmission-line (t-line) transformer and verifies this with the design of a two-stage D-band power amplifier (PA). Series power combining techniques incorporate both stacked heterojunction bipolar transistors (HBTs) and power combining using an 8-way sub-quarter-wavelength t-line transformer above 100 GHz. The extremely compact power combining methodology leads to a small die area of 0.62 mm2 and a record 254-mW/mm2 output power per unit die area. The PA has been fabricated in a 90-nm silicon germanium BiCMOS technology and produces more than 21-dBm output power over the frequency range of 114–130 GHz with a peak output power of $160~{\mathrm{mW}}\approx 22~{\mathrm{ dBm}}$ at 120 GHz and a 3-dB small-signal bandwidth of 35 GHz. This output power is 32% higher than the highest prior art, while the chip area is 77% smaller. [ABSTRACT FROM AUTHOR]

This paper presents a link analysis for optical interconnects based on CMOS scaling toward FinFET devices. An on-chip wavelength division multiplexing (WDM) link is modeled assuming silicon photonic ring modulators, WDM multiplexers and demultiplexers, and photodetectors. A high-speed CMOS transceiver is designed and evaluated using 28-nm FD-SOI and 14-nm FinFET processes. Compared to 28-nm FD-SOI, the 14-nm FinFET offers higher intrinsic gain and allows for 50% higher transconductance per drain current suggesting more energy-efficient circuit design. Cosimulation of the photonic and electronic devices demonstrates an optimum energy efficiency of \sim 2\, \textpJ/b at 25\, \textGb/s for a bit-error rate of 10^-12 including laser and ring tuning power. [ABSTRACT FROM PUBLISHER]

Double-edged pulsewidth modulation (DPWM) is less sensitive to frequency-dependent losses in electrical chip-to-chip interconnects. However, the DPWM scheme instantaneously transmits information at a different rate than a synchronous source. This paper presents an 8-/9-bit line-coding scheme to compensate for the timing skew between the DPWM and synchronous clock domains while limiting the size of buffering required in the transmitter and receiver. Furthermore, preemphasis is introduced and analyzed as a means to improve the signal integrity of a DPWM signal. A multiphase-based, time interleaving receiver architecture using a sense amplifier is presented for high-speed data recovery. The DPWM transceiver is implemented in a 45-nm CMOS Silicon on insulator and operates at 10 Gbit/s with 10^-12 bit error rate and consumes 96 mW. The power consumption of the 8-/9-bit coding hardware is 1.5 mW at 10 Gbit/s demonstrating low-power overhead. [ABSTRACT FROM AUTHOR]

Circulators and quasi-circulators (QCs) have a tradeoff between maximum isolation and bandwidth. We present a tunable distributed active circuit to achieve high isolation over a wide frequency range. The reported QC provides more than 40-dB suppression between transmit (TX) output signal at the antenna and TX leakage into the receive (RX) port over a tuning range of 5.3–7.3 GHz in small-signal operation. Large-signal TX-RX suppression is optimized across power level. The TX output achieves peak power of 18 dBm and 12% power-added efficiency at 6.3 GHz. The QC is designed in a high-resistivity 45-nm CMOS silicon-on-insulator process and occupies an area of 1.62~ \text mm \times 0.97~ \text mm . [ABSTRACT FROM PUBLISHER]

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100-\Omega load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s. [ABSTRACT FROM PUBLISHER]

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2\, \times \,2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm. [ABSTRACT FROM PUBLISHER]

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution. [ABSTRACT FROM PUBLISHER]

This paper presents a pulse-compression radar baseband analog signal processing integrated in a silicon process for low cost and power dissipation. The analog signal-processing circuitry exhibits the autocorrelation properties of the polyphase codes, maximizes the sensitivity and resolution of a pulse radar system, and alleviates speed and resolution requirements of the analog-to-digital converter (ADC) via an analog correlator. The circuitry includes a two-stage variable gain amplifier (VGA) for high dynamic range, a correlator/integrator circuit, a comparator, and offset calibration circuits. The differential 6-bit VGA is designed to adaptively track the Friis path loss through rapid change of the VGA gain and offset calibration, relaxing the dynamic range requirements of the correlator. The measured performance shows a VGA gain variation of 52 dB and a VGA group-delay imbalance of 50 ps over 64 states. The high-speed pulse compression/correlation is performed in analog current domain and the speed requirement on the ADC is reduced by a factor equal to the duty cycle lowering the ADC power consumption. The chip is fabricated in a 90-nm process, wire bonded on the FR4 printed circuit board, and tested with a Stratix IV field-programmable gate-array board to evaluate the system performance for different radar polyphase codes. [ABSTRACT FROM AUTHOR]

A broadband amplifier is realized with cascaded stagger-tuned stages that are equalized for high bandwidth and low gain ripple. The staggered frequency response is demonstrated to improve the transimpedance limit of active circuits. The staggered response is demonstrated with a Darlington feedback amplifier and a constructive wave amplifier, which achieves low group delay. The broadband amplifier is implemented in a 0.12-\mu\ m SiGe BiCMOS process and achieves a 3-dB bandwidth of 102 GHz. The gain is 10 dB with 1.5-dB gain-ripple and group-delay variation under \pm6 ps over the entire 3-dB bandwidth. The chip occupies an area of 0.29 \ mm^2 including the pads and consumes 73 mW from a 2-V supply. [ABSTRACT FROM PUBLISHER]

An Si photonic transmitter is integrated in a 130-nm silicon-on-insulator complementary metal–oxide–semiconductor technology. A high-speed photonic ring modulator is designed for 25-Gb/s operation with an 8-dB extinction ratio. The ring is driven with a 2.4\-Vpp swing using a low-power inverter driver. With a reference receiver, the 25-Gb/s link is measured with a bit error rate (BER) of 10^-12. The total transmitter power consumption is 17 mW at 25 Gb/s for an energy efficiency of 680 fJ/b excluding laser and ring tuning power. [ABSTRACT FROM PUBLISHER]

A W-band, cascaded constructive wave amplifier realizes high gain and bandwidth in a 0.12 \mum SiGe BiCMOS process. The amplifier achieves 37.5 dB gain at 90 GHz with a 3 dB bandwidth of 14.6 GHz. Consequently, this amplifier demonstrates a gain-bandwidth product as high as 1,095 GHz. At nominal bias condition, input and output return losses are better than 11 dB over the entire 3 dB bandwidth and the output-referred P1 dB is -5.5 dBm. The amplifier consumes 65 mW from a 1.8 V at a nominal bias condition and 130 mW from a 2 V at a high-gain bias condition. The chip occupies an area of 0.39 mm^2 including the pads. [ABSTRACT FROM PUBLISHER]