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The reliability results of floating-gate (FG) memory using 5-nm tunnel oxides in mature to advanced logic processes from multiple foundries are described. The studies have shown that it is possible to develop a small-bit-count FG nonvolatile memory (NVM) array by using 5-nm oxide, which has enabled embedded logic NVM in advanced CMOS processes with no additional masks or processing steps.

The aim of this study was to quantify image noise and signal recovery in respiratory gated PET. A Jaszczak phantom filled with [sup.18]F was placed on a custom built motion platform. Different source to background activity ratios were used. An Anzai belt, a surface tension monitoring device, was strapped around the phantom to track the motion and to trigger the gated PET cycle. Data were acquired into 12 bins throughout one gating cycle. The binned data were also summed to produce image sets representing acquisitions with different numbers of gates, including a non-gated image set. The image noise was estimated using the bootstrap method. Images were generated from 100 sinogram replicates and reconstructed using ordered subsets-expectation maximization (OSEM), 4 iterations and 8 subsets. From the reconstructed image replicates, mean and standard deviation images were created, from which the average image signal-to-noise ratio (SNR) and contrast-to-noise ratio (CNR) of each sphere were calculated. The SNR and CNR were evaluated as a function of the number of gates. The SNR and CNR result in the expected Poisson limited correlation with the number of gates for the larger lesions. Because of the motion, the CNR calculated from the images produced with no or few gates is nearly a factor of 2 less than the expected value for the 3 smallest spheres. As the number of gates increases, the CNR correlates with the expected values. Beyond 6 gates, image noise dominates over any signal improvement, which is reflected in the low CNR values of the smallest spheres. The results of this study show that gating can provide improvement in signal recovery with minimal loss of CNR for small, moving lesions. Index Terms--Gating, image noise, PET, respiratory motion.

Performance of multichannel lateral insulated gate bipolar transistors (MC-LIGBTs) fabricated in a cost-effective, fully implanted, CDMOS-compatible process in junction isolation technology is reported. It is shown that combining the MC and the SA-segmented N (super +)P/P(super +) [NPN] anode concepts creates a device that exhibits both low on-state and turnoff losses and is best placed for use in power IC applications.

The Lambert function-based analytic solution for the surface potential of undoped-body single gate bulk MOSFETs is extended to offer an explicit analytic solution of the surface potential of undoped-body symmetric dual-gate devices. The error produced by the proposed solution compared to exact results is small for typical device dimensions and bias conditions.

The analysis of the leakage power and input pattern dependence o leakage for extremely scaled double-gate circuits is presented, comparing with those of conventional bulk-Si counterpart. Physics-based numerical two-dimensional simulation results for DG CMOS device/circuit power are presented, identifying that DG technology is an ideal candidate for low-power applications.

The effects of preamorphization implantation (PAI) on the interface properties between hafnium-silicate (HfSiO) gate dielectrics and silicon substrates were examined. It was found that in the case of an NH3 nitrided interface, the PAI could improve the interface trap density [D(sub IT)] compared with the no PAI case.

This paper introduces a new resonant gate driver for both the top and bottom switches of a synchronous buck converter. A coupled inductor is used to reduce the size as well as to transfer energy between the top and bottom gate driving. A possible semi-conductor integration approach is proposed for this resonant gate driver based on a self-adaptive control method. Theoretical analysis, simulation and experimental results prove that the proposed driver can greatly reduce the gate driving loss and that it is well suited to high-frequency applications. Index Terms--Gate drive, high frequency, resonant gate drive.

An innovative dual-metal gate complementary metal-oxide semiconductor (CMOS) technology that relies on nitrogen-concentration-controlled TiNx film is proposed. The technology is based on the discovery that threshold voltage depends on the concentration of nitrogen in the TiNx electrode.

The amount of nitrogen at the Si/SiO[subscript 2] interface is increased, compared to traditional gate oxidation, by using nitrogen implantation and the initial O[subscript 2] method to manufacture 0.13 micromillimeter metal-oxide semiconductor field-effect transistors (MOSFET). Time of flight secondary ion mass spectroscopy (TOF-SIMS) analysis indicates that the initial O[subscript 2] injection can make the peak concentration at the interface high.

A new silicon RF vertical double-diffusion metal-oxide semiconductor field-effect transistor (VDMOSFET) structure is proposed, which includes a dummy gate between the device's active gates. The dummy gate acts as a field plate, minimizing drain-to-gate feedback capacitance and raising its breakdown voltage.

A new bulk 50 nm metal-oxide semiconductor field-effect transistor (MOSFET) with n[superscript +] poly-Si sidegates is described. A main gate with a work function different from that of n[superscript +] poly-Si sidegates is used.

Synthesis of a high-quality graded oxide is described. Grading is accomplished by growing a high-temperature oxide above the silicon dioxide viscoeleastic temperature under a pregrown lower-temperature silicon dioxide layer.

A performance-constrained minimum power-area optimization is used to predict physical oxide thickness scaling limit from a circuit-level perspective. Using the physical alpha-power law MOSFET model, an expression for propagation delay is developed.

An expression for bits that can be programmed per unit of time, in flash memories using the ramped gate programming (RGP), is used to optimize memory bandwidth and derive design curves. Preliminary results indicate that memory can exceed 10 Mb/s with optimized cell programming and that it can be negatively affected by device scaling.

A tantalum nitride (TaNx) metal gate complementary metal oxide semiconductor (CMOS) technology is described, which uses a low-resistivity bcc (body-centered-cubic)-phase tantalum metal layer. It features low-temperature processing (below 550 degrees centigrade) except for gate oxide formation.

Metal gate work function deviation (crystal orientation deviation) causes threshold voltage deviation in damascene metal gate transistors. If TiN work function (crystal orientation) is controlled by means of a chemical vapor deposition (CVD) technique, threshold voltage deviation of surface channel damascene metal gate transistors is significantly improved and is less than that for conventional polysilicon gate transistors.

A 2.4Fsquared memory cell technology with a self-aligned-type stacked-surrounding gate transistor (S-SGT) dynamic random access memory (DRAM) is proposed. Why the S-SGT DRAM is a candidate for future ultra-high-density DRAMs is explained.

An enhancement-mode AlGaAs/InGaAs/AiGaAs heterojunction field-effect transistor (HJFET) has been developed, with a 5mm Al[sub 0.5]Ga[sub 0.5]As barrier inserted between an In[sub 0.2Ga[sub0.8]As channel layer and an upper Al[sub 0.2]Ga[sub 0.8]As electron supply layer. Results indicate that the HJFET is appropriate for single low voltage power applications.

Research into the measurement of tunneling currents through gate oxides is presented. A model which predicts electron tunneling from the conduction and valence band and hole tunneling from the valence band in CMOS systems is proposed.

Research into the suppression of the parasitic bipolar effect in MOSFET structures is presented. A design which offers near complete protection against circuit failure, and thus applications in SOI circuits, is proposed.

It has been possible to develop an experimental structure to measure the gate current noise down to a current spectral intensity of 10(super -27) A2/Hz. The LF gate noise level is very sensitive to any change in the transport mechanisms arising at the surface of GaAs power MESFETs.

Results of a SiO2/Si3N4/SiO2 (oxide-nitride-oxide) gate insulator stack deposited on GaN using vapor jet deposition are presented.

Gate oxides on low-dose separation by implanted oxygen (SIMOX) substrates, produced by the ITOX process, were examined.

Gate length scalability of lightly doped drain and non-LDD n-MOSFET's was examined.

This paper deals with an active gate drive (AGD) technology for high-power insulated gate bipolar transistors (IGBT's). It is based on an optimal combination of several requirements necessary for good switching performance under hard-switching conditions. The scheme specifically combines together the slow drive requirements for low noise and switching stress and the fast drive requirement for high-speed switching and low switching energy loss. The gate drive can also effectively dampen oscillations during low-current turn-on transient in the IGBT. This paper looks at the conflicting requirements of the conventional gate drive circuit design and demonstrates using experimental results that the proposed three-stage AGD technique can be an effective solution. Index Terms: Active gate drive, gate drive circuit, gate resistor, insulated gate bipolar transistor switching transient

Four different kinds of constant current stresses were applied to N2O-grown and O2-grown, 4-nm thick gate oxides and the resultant interface-trap density was measured. The charge pumping method was used to measure the interface-trap density produced under the stresses. The injection of impact-ionization-generated hot holes is shown to be the most significant reason for interface trap creation under V (sub G) < 0 FN stress at high oxide field. It is also shown that the substrate-hot-hole stress induces more interface traps than substrate-hot-electron stress.

An experimental and theoretical demonstration of the impact of tunneling currents and channel resistance on the measured gate-to-channel capacitance using long-channel metal oxide semiconductor field effect transistors with sub-20-angstrom gate oxide is presented. A model is derived for the terminal capacitance in terms of tunneling conductance, intrinsic capacitances, measurement frequency and channel length. The model is useful in characterizing a measured extrinsic capacitance fall-off in strong inversion and its relationship with the oxide thickness and channel length of the test structure.

A study on semiconductor optical amplifiers reports on such an amplifier with a 1.55-micron wavelength and spot-size converters of thickness-tapered stripes. The experimental approach involved the investigation of bulk InGaAsP active stripes with submicrometer and nearly square cross sections as these structures provide a large gain leading to a low operating current and a gain that is sensitive to optical input polarization. Experimental methods and results are presented.

A study was conducted to analyze the influence of SiN gate sidewall processes on the parasitic resistance of shallow p+ extension region based on a complementary metal oxide semiconductor process integration perspective. The optimization of shallow junction formation processes to reduce the parasitic resistance was examined. Results indicated that a germanium preamorphization process minimizes the total parasitic resistance to enhance the drain saturation current.

A study was conducted to analyze a novel quasi-two-dimensional gate-induced drain leakage framework and use it to determine the band-to-band tunneling current. Results indicated excellent agreement between the computed results using a quasi-two-dimensional model with measured values for a broad range of gate and drain biases. Findings also showed that the model can be utilized to stimulate hot-carrier band-to-band tunneling current for p-channel flash memory device.

Research was conducted to investigate the characteristics of a simple logic gate consisting of a radio frequency-superconducting quantum interference device (SQUIDs) and direct current SQUID. The Josephson junctions were fabricated via the focused ion beam method. Experimental results were evaluated based on a phenomenological model of the proposed Josephson junction. Circuit simulation was made which confirmed the temperature dependence of the output voltage level.

This paper reports on the ellipsometric monitoring of SRAM gate patterns in KrF lithography. Results showed that ellipsometry is practical for monitoring repetitive patterns. A multivariable regression analysis was applied to predict gate lengths by using ellipsometric parameters. A good agreement (3[Sigma] = 8.7 nm) between the measured width by CD-SEM and the predicted ones was achieved. Standard deviation of the predicted width (repeatability) was 0.5 nm. This suggests that ellipsometry is superior to CD-SEM in arriving at the average values.

Gate drive circuits for modern power electronic switches, such as MOSFET and insulated gate bipolar transistor (IGBT), often require electrical isolation. This paper describes the modeling and experimental results of some coreless printed circuit board (PCB)-based transformers that can be used for MOSFET and IGBT devices at high-frequency (500 kHz to 2 MHz) operation. PCB-based transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits. With no core loss, coreless transformers are found to have favorable characteristics at high-frequency operations. This project demonstrates an important point that the size of the magnetic core can approach zero and become zero when the frequency is sufficiently high. Index Terms - Coreless PCB transformers, gate drive circuits, high-frequency magnetics.

Gate drive circuits for power MOSFET's and insulated gate bipolar transistors (IGBT's) often require electrical isolation. Coreless printed circuit board (PCB) transformers have been shown to have desirable characteristics from a few hundreds of hertz to a few megahertz and can be used for both power and signal transfer at low-power level. At low operating frequency, the magnetizing inductance has such low impedance that the driving power requirement could become excessive. This paper describes the use of a coreless PCB transformer for isolated gate drive circuits over a wide-frequency range. based on a resonance concept, the optimal operating condition that minimizes the power consumption of the gate drive circuits is developed and verified with experiments. The coreless PCB transformer demonstrated here confirms a fundamental concept that the size and volume of a magnetic core could approach zero and become zero if the operating frequency is sufficiently high. Coreless PCB transformers do not require the manual winding procedure and tires simplify the manufacturing process of transformer-isolated gate drive circuits and low-power converters. Their sizes can be much smaller than those of typical core-based pulse transformers. The electrical isolation of a PCB is much higher than that of an optocoupler. Index Terms - Coreless PCB transformers, gate drive circuits, high-frequency magnetics.

This paper describes the modeling and implementation of a coreless printed circuit board (PCB)-based transformer with 'multiple' secondary outputs. This new PCB transformer has been successfully applied in complementary gate drive circuits in a novel low-profile power converter with high-power density and a converter bridge. The PCB-based transformers do not require the manual winding procedure and thus simplify the manufacturing process of transformer-isolated gate drive circuits. The use of the multiple secondary outputs can in principle simplify the complementary gate drive circuits that are often required in many power electronics applications. Index Terms - Coreless PCB transformers, gate drives, magnetics.

A method is presented to monitor the state of a converter with an unlimited number of paralleled insulated gate bipolar transistor (IGBT)/diode modules with individual gate drives. The monitoring functions can be implemented without extra signal processing or load-side components. The method is based on the active gate-controlled current balancing (CB) principle. This principle is reviewed in the first part of this paper, and the necessary supplements to implement the monitoring functions are shown. In the second part, experimental measurements are shown. This new control method allows monitoring the state of a converter and balancing the losses and current sharing between paralleled power devices without the need to match the devices nor the gate drives. Thus, the overall reliability can be increased without increasing the costs. Since no matching of the devices is needed, the handling and logistic costs can be significantly reduced. IGBT/diode modules for standard paralleling are selected, and only modules of the same class can be paralleled without excessive derating. The presented method allows switching off one of the paralleled branches in the case of parameter degradation and to keep the converter operating at a lower power. Index Terms - Availability, current balancing, insulated gate bipolar transistor, monitoring, paralleling. power converter, power module, power semiconductor devices, power semiconductor switches.

The bias temperature instability in surface-channel p+ polysilicon gate p-metal oxide semiconductor field effect transistors (p-MOSFETs) was investigated. Findings revealed that a large negative threshold voltage shift is induced by negative bias temperature stress in short-channel p-MOSFETs. The degradation of the gate oxide near the gate edge was due to the electrochemical reaction between holes and oxide defects and was enhanced by boron penetration through the gate oxide from p+-gate.

The dual material gate (DMG) field effect transistor (FET), a generic new type of FET, was proposed and demonstrated. The gate of the DMGFET consisted of two laterally contacting materials with different work functions. This structure is advantageous in that the threshold voltage near the source is more positive than near the drain which resulted in a more rapid acceleration of charge carriers in the channel and a screening effect to suppress short-channel effects.

A novel double-deck-shaped gate technology for 0.1 micrometer heterojunction field-effect transistors (HJFET) based on dry-etching processes was described. The technology used a T-shaped SiO2-opening and gate-metal filling techniques which cuts into half the external gate fringing capacitance of conventional T-shaped gate HJFETs and allows the fabrication of voidless refractory gate-electrodes which ensure high uniformity. The fabricated HJFETs provided higher performance since the technology was based on an all-dry-etching process.

Findings of a study showed that in high-resistivity silicon bulk generation lifetime and surface generation, velocity can not be measured with acceptable accuracy using a single gated diode unless the gate length is suitably tailored. The accuracy of the evaluation of bulk generation lifetime was limited by nonidealities and contributing extra components to the gated-diode current which were not accounted for in the standard extraction procedure.

The range gate tracking algorithms in the United States' satellite radar altimeters over the past 20 years all use the same waveform estimators: uniformly weighted gates. The generic algorithm is based on a nested family of range intervals, within which the average reflected power is computed. This choice of gate weighting is guided by matching the gate properties to the shape of the flat surface impulse response of the scattering surface. For the case of a conventional, pulse-limited radar altimeter, the flat surface impulse response is a step function, for which uniformly weighted gates are appropriate. In the more general case, nonuniform weights are required. This paper reviews the theory behind the gate tracking algorithm as applied to conventional altimeters and extends this basic method to the recently proposed delay/Doppler altimeter whose impulse response does not have a step-function shape. Furthermore, it is shown that the definition of the tracking gates for either type of altimeter can be modified to account for the impact of the radar antenna beampattern on the altimeter waveform. Index Terms - Radar altimetry, radar tracking, sea measurements.

A 6 kV, 6 kA pnpn-type gate turn-off was developed and its maximum turn-off current was studied. Simulation results revealed that current concentration to the lower on-state voltage segment in the fall period for simulations with segments having various on-state voltages. The use of a homogenous fabrication process results in a decline in the on-state voltage distribution band by a factor of two. Experimental results were found to be in line with the maximum turn-off current predicted by the proposed high-power GTO turn-off limiting model.

A detailed analysis of the various physical mechanisms that could result in the direct proportionality between the gate and the substrate current as the signature of substrate enhanced electron injection (SEEI) is presented. Experiments and simulations are used to substantiate the current interpretation of SEEI in terms of an impact ionization feedback procedure. The experiments bring together the current explanation of SEEI and the phenomenon of photon assisted minority carrier injection in the substrate.

An in-depth analysis of the phenomenon of gate current improvement upon application of a substrate voltage recently seen in deep submicron metal oxide semiconductor field effect transistors is presented. By studying the correlation between the gate and the substrate gate as a function, it is observed that the correlation offers an experimental signature of the onset of a new injection regime. The correlation is also shown to indicate a simple method for separating the substrate gate enhanced gate current component from the conventional channel hot electron one.

The impact of gate recess structure on the device performance of Ga0.51In0.49P/In0.2Ga0.8As doped-channel field effect transistors (DCFET's) is studied. The analysis of single-, double- and triple-recessed gate profiles showed that triple-recessed gate DCFET's had the highest breakdown voltages. These also had high transconductance of 306+-5 mS/mm, f(sub t) of 21.6+-0.3Ghz and f(sub max) of 53.2+- 0.5 GHz. A method for determining the breakdown voltage of MESFET's, high electron mobility transistors and DCFET's is also developed.

A study was conducted to develop double-gate elevated-channel thin-film transistor using polycrystalline silicon. Two-dimensional device simulations were carried out to analyze the electric field reduction mechanism in the structure. Experimental results indicated that the drain electric field reduction influenced the reduction of leakage current and elimination of the kink effect. Findings also showed that the capacitance and area needed for the storage capacitor depended on the pixel size.

A study was conducted to develop a high performance polycrystalline silicon thin film transistor supporting a silicon nitride gate insulator with three stacked layers. Low resistive NiSi silicides were integrated as gate/source/drain electrodes to minimize process steps. Si:H film obtained by plasma enhanced chemical vapor deposition was used as the starting material for laser annealing. The thin film transistor featured a field effect mobility of 2262 cm2/Vs and a threshold voltage of -1 V.

A study was conducted to analyze low frequency noise in gated n+-p silicon diodes based on the trapping and detrapping of holes in defect centers. The HP 4275A multifrequency LCR meter was utilized to determine the gate capacitance as a function of gate-to-substrate voltage. Individual Lorentzians related with local noise sources were identified to examine the physical features of the bulk defects responsible for the noise. Results indicated that thermal pretreatments lowered the defect density in the active area of diodes.

A study was conducted to characterize the fabrication of enhancement-mode high electron mobility transistors' lattice-matched to InP through a buried-Pt gate method. Schottky diodes were fabricated to determine the barrier heights of various gate metals. Results indicated that the transistors can be utilized as drivers in direct coupled field effect transistor technology in the lattice-matched InP material system because of their excellent electrical features.