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MnAs thin films were grown by low-temperature molecular beam epitaxy on semi-insulating GaAs(1 0 0) substrates under varying growth parameters, including the As4/Mn flux ratio and Mn beam equivalent pressure. When the As4/Mn flux ratio was set at 1–1.2, the Mn–As blocks were formed, and an increasing As4/Mn flux ratio resulted in a growth of αMnAs with the growth direction of [1101] and the the mirror-like surface. Under restricted growth conditions, ferromagnetic hexagonal αMnAs layers were first prepared on GaAs(1 0 0) substrates at 250 °C, and orthorhombic Mn3As2 blocks were subsequently formed on the MnAs layers.

We propose a large-signal model that can simulate the power-added efficiency of p-pocket self-aligned gate GaAs MESFET's. This model includes a new drain current model and a gate bias-dependent RF output resistance to express the drain conductance and its frequency dispersion at each gate bias. In addition, gate-source and gate-drain capacitances are modeled by functions of two variables of gate and drain biases so as to fit the measured values of ion implanted channels. The simulated power-added efficiency agreed with the measured value with a maximum error of 5%. The intermodulation distortion was also simulated and the maximum difference between the simulated and measured results was reduced to one-fifth of the results simulated by the conventional model. Practical applications were demonstrated by the load-pull simulation and the /spl pi//4 shift QPSK-modulated signal simulation.

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

The effect of chip-mounting attachment on the thermal resistance of GaAs power field effect transistor (FET) modules has been experimentally investigated. The thermal resistance was evaluated for different GaAs chip thickness of 150 and 250 /spl mu/m through an electrical method utilizing temperature dependence of Schottky-barrier in the GaAs metal semiconductor FETs (MESFETs). The thermal resistance of low-cost epoxy-mounted GaAs chips, suitable for uniplanar monolithic microwave ICs (MMICs), was found not to increase even up to a chip thickness of 250 /spl mu/m, while that of AuSn-mounted GaAs chips increased as was conventionally expected. Numerical simulation has also been presented for the similar case of GaAs power MMICs. The result of simulation suggests that lower thermal conductivity of attachment material, such as epoxy attachment, leads to larger optimum chip thickness that minimizes the total thermal resistance.

An improved GaAs MESFET structure, named a buried p-layer lightly doped deep drain (BP-LD3) structure, is proposed. This structure can be fabricated by the conventional self-aligned gate and selective ion implantation technologies, and the FET characteristics show a high transconductance, a high breakdown voltage, and a low drain-source resistance. The lightly doped deep drain characterizing this structure was introduced on the basis of a two-dimensional numerical analysis including an impact ionization for a buried p-layer lightly doped drain (BP-LDD) structure which has been applied for high-speed digital ICs. The simulated results clarified that a low breakdown voltage of the BP-LDD structure originates from a high rate of carrier generation due to the impact ionization in the lightly doped drain region. The reason is that both electric field and current density become high in the region. In the new BP-LD3 structure, the electron current expands due to the deep formation of lightly doped drain, therefore impact ionization is reduced. This BP-LD3 structure was fabricated and the FET characteristics were compared with those of the conventional BP-LDD structure, and a structure which is now being studied for linear amplifiers of 1.9 GHz personal handy-phone systems. The measured breakdown voltage of 8.1 V, transconductance of 360 mS/mm, and drain-source resistance of 2.5 /spl Omega//mm for the BP-LD3 structure indicate high potentiality for analog applications.

Reliability of 0.8 μm WNx gate GaAs MESFETs with a self-aligned lightly doped drain structure has been investigated by means of high temperature storage life tests at 250, 275 and 300 °C. The observed reduction in threshold voltage followed by drain current increase was just reverse in contrast to those for ‘gate sinking’ effect reported on several Au-based gates. The correlation of the threshold voltage reduction with Shottky barrier height and other MESFET parameter changes during the tests suggested a model related to the short channel effect for the threshold voltage reduction, which was proved true by submitting samples of gate lengths 0.7, 1.0 and 1.5 μm to high temperature storage life tests. The dependence of threshold voltage changes on gate orientation relative to the crystal axis was also evaluated with 1.0 μm gate MESFETs to investigate the model in more detail. MESFETs parallel to [001] axis showed minimum absolute threshold voltage changes, while those parallel to piezoelectrically active [011] and [0 1 1] axes showed decreasing and increasing threshold voltage changes, respectively. From these results, the threshold voltage changes were tentatively ascribed to the relief of the stress caused by poly-imide die bonding process for packaging MESFET chips. In other words, WNx gate GaAs MESFET chips themselves were concluded to show no appreciable degradation up to 1000 hr storage life tests at 250 and 275 °C, except for ohmic contact degradation at 300 °C.

An ultrahigh-speed 8 bit multiplexer (MUX) has been developed for future-generation optical-fiber communication systems having a data rate of 20 Gb/s. This IC was fabricated using a 0.5 /spl mu/m WN/sub x//W-gate GaAs MESFET process based on optical lithography, ion implantation, and furnace annealing for good reproducibility and high throughput. The WN/sub x//W bilayer gate has a low sheet resistance, improving the circuit high frequency performance. To attain 20 GHz operation, advanced circuit techniques for the source-coupled FET logic (SCFL) were introduced. A cross coupled source-follower (CCSF) was developed mainly for the highest speed buffers to enhance the bandwidth. The first-stage T-type flip-flop was designed with optimization techniques and operated up to 21.1 GHz. >

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

The minimum device isolation distance (L/sub min/) applicable to GaAs digital large-scale integrated circuits is presented. The leakage current between two n-type layers formed in a semi-insulating (SI) substrate is simulated using a two-dimensional numerical model, and the results are compared with measurements. It is found that the leakage current is restricted by a potential hump formed by residual acceptors in the SI GaAs substrate when an isolating layer loses its compensated SI property. L/sub min/ is defined as the distance at which there is a leakage current of 1 mA for an isolating layer width of 1 cm. The calculated value of L/sub min/ at room temperature is 1.3 mu m with a bias voltage of 2 V and an acceptor concentration of 10/sup 15/ cm/sup -3/. L/sub min/ decreases to 2/3 of this value when the temperature is reduced from 400 to 100 K, to 1/3 when the acceptor concentration is increased by one order, and to 2/3 when the bias voltage is reduced from 5 to 2 V. >

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50- Omega on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5- mu m WN/sub x/-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230 degrees . >

Gate-voltage-dependent mobility profiles in long-, short-, wide-, and narrow-channel WN/sub x/-BPLDD (buried p-type buffer lightly doped drain region) GaAs MESFETs have been determined (L/sub G/=10, 4, 2, 1, 0.8, 0.5, 0.3 mu m, W/sub G/=20 mu m; W/sub G/-100, 40, 20, 10, 4, 2 mu m, L/sub G/=0.5 mu m). The mobility mainly depends on the channel width, while the gate length has much less influence. Thus, using proper gate dimensions the channel mobility can be tuned. The highest drift mobility values agree quite well with the measured Hall mobilities. Mobility profiles of large-area MESFETs are probably degraded by the WN/sub x/-gate fabrication process. Injected excess charges at gate length below 0.5 mu m distorts the mobility evaluations. >

Asymmetric tilt-angle-implanted lightly doped drain (LDD)-WN/sub x/-GaAs MESFETs with an optimized transconductance performance are discussed. A tilt-angle implantation is used to reduce the parasitic source resistance below the gate sidewall without increasing short- and narrow-channel effects. This leads to a transconductance increase of nearly 25% for submicrometer FETs while the gate-source capacitance increase is almost negligible. The influence of the implantation angle on the threshold voltage transconductance, and Schottky-barrier characteristics is reported. >

The effect of attachment for chip-mounting upon the thermal resistance of GaAs power FET modules has been experimentally investigated. The thermal resistance was evaluated by electrical method, which is related to the temperature dependence of Schottky-barrier in the GaAs MESFETs. The thermal resistance of low-cost epoxy-mounted modules was found to be almost the same as that of AuSn-mounted ones for a chip-thickness of 250 /spl mu/m. Applicable expression has also been presented for optimizing thermal design of power MMICs, suggesting that the optimum chip thickness depends on the thermal conductivity of attachment material.

A large-signal model which can simulate the power-added efficiency of p-pocket self-aligned gate GaAs MESFETs its proposed. This model includes a new drain current model and a gate bias dependent RF output resistance to express the drain conductance and its frequency dispersion at each gate bias. The simulated power-added efficiency agrees with the measured value with a maximum error of 5%. This model is also applicable to the distortion simulation by the introduction of new gate-source and gate-drain capacitance models using two variables for the gate and drain biases.

Ultra-high-speed 2-b multiplexer (MUX) and demultiplexer (DEMUX) ICs have been developed for next-generation optical fiber communication systems in the SONET (synchronous optical network), which will require data bit rates of about 10 Gb/s. The ICs were fabricated using a 0.5- mu m WN/sub x/-gate process and were operated up to 12 Gb/s by adopting a tree-type architecture with a large phase margin and a new on-chip transmission line called the ladder grounded coplanar line. These ICs are applicable to future optical fiber communication systems (STS-192) as key devices. >

An improved symmetric GaAs MESFET structure with a lightly doped deep source/drain is proposed for application to power amplifiers in mobile communication terminals. With lightly doped deep drain, the impact ionization falls as the electron current expands and the current density decreases. Thus, the breakdown voltage rises, while a high transconductance and low parasitic resistance are maintained. Furthermore, the symmetric structure suits for mass production because of its fabrication process without mask alignment precision. This structure was fabricated using the WNx/W self-aligned gate process, and DC and RF characteristics were evaluated. The power-added efficiency was 37% at an adjacent channel leakage power of -55 dBc for 37%-shift QPSK modulated input signals at 1.9 GHz with a single positive supply voltage of 3 V. The efficiency was also high at a lower supply voltage: 34% at 1.2 V.

The combined process of epitaxy and ion implantation has been developed in the fabrication of a buried-channel WNx/W self-aligned heterostructure GaAs FET. This FET comprises an ion implanted channel and an undoped AlGaAs epitaxial surface layer. The ion-implantation technique leads to an IC-oriented process and the epitaxial technique to a buried channel structure. Both ease of isolation and enhanced breakdown voltage were attained, promising MMICs for L-band digital mobile communication systems.

A GaAs SPDT switch IC operating at a low power supply voltage of 2.7 V has been developed for use in Personal Handy-Phone System in the 1.9 GHz band. In combination with MESFETs with low on-resistance and high breakdown voltage, the resonant-type switch IC utilizes stacked FETs and an additional shunt capacitor at the receiver side in order to realize low insertion loss, high isolation and low distortion characteristics. An insertion loss of 0.55 dB and an isolation of 35.8 dB were obtained at 1.9 GHz. The IC also achieved a second order distortion of -54.3 dBc and an adjacent channel leakage power of -66 dBc at 600 kHz apart from 1.9 GHz at 19 dBm output power.

A monolithic GaAs power amplifier IC using refractory WN/sub xW self-aligned gate power MESFETs has been developed for 1.9-GHz digital mobile communication systems, such as the Japanese personal handy phone system. The power amplifier operates with high efficiency and low distortion with a single low voltage supply of 2.7-3.0 V, by virtue of small drain knee voltage, high transconductance and sufficient breakdown voltage of the power MESFET. An output power of 23.7 dBm and a high power-added efficiency of 24.2% were attained at 3 V for 1.9-GHz /spl pi4-shifted QPSK (quadrature phase shift keying) modulated input when adjacent channel leakage power was -58 dBc at 600 kHz apart. >

The authors propose a novel cell-shifting compaction concept for building-cell methodology to realize high-speed GaAs standard-cell LSIs. This compaction reduces the layout-area and stray capacitance and the inductance of routings, and leads to a large degree of freedom for cell placement. The cell-shifting compaction is also a valid approach for Si standard-cell LSIs. >

A GaAs high-speed data transfer network connecting multiple processor units (PUs) has been successfully developed in a module with 8-b slice GaAs bus logic (BL) LSIs, which fully functioned at more than 100 MHz. The GaAs multichip module consists of 12 GaAs BL LSIs in a 3*4 matrix. In the parallel processing system, a 4 Gbit/s data transfer data (32 b*120 MHz) can be realized by four stacked modules of 48 GaAs BLs. >

A novel layout concept of Building-Cell (BC) methodology which realizes high-speed GaAs standard-cell LSIs is introduced. This methodology reduces the layout area and wiring-length, and leads to a large degree of freedom for cell placement. A GaAs data bus LSI, consisting of 3500 gates and a 75-bit register file, was designed to verify the effectiveness of this methodology, which functioned at a fast cycle time of 7 ns. >

A rhodium/gold/rhodium (Rh/Au/Rh) air-bridge interconnection has been developed for applying to ultra-high-speed GaAs LSIs. This structure is suitable for forming a mechanically strong air-bridge interconnection, which enables an interconnection length to be expanded without many support-pillars, compared with a gold air-bridge interconnection. This contribution of the air-bridge interconnection to total propagation delay time in a GaAs LSI chip is quantitively investigated. It is found that applying the air-bridge interconnection to a GaAs LSI with 10 K-gate complexity causes total delay time to be reduced to 65%, compared with the conventional interconnection. >

The possible scaling limits of ion-implanted GaAs MESFETs have been investigated by means of a numerical model which includes interface states at the Schottky barrier. It was found that the scaling limit depends on the interface state density because the barrier height and the threshold voltage are affected by the interface state density. When an E-type FET in DCFL circuits is scaled-down on the basis of the present 0.5- mu m-gate buried p-layer LDD (lightly doped drain) MESFET, the gate length can be reduced to 0.21 mu m at an interface state density of 6.6*10/sup 12/ cm/sup -2/ eV/sup -1/ where the gate length is a minimum. >

A single 2-V operation RF front-end MMIC has been developed using three kinds of self-aligned gate MESFETs. Its transmitter block of a power amplifier with an antenna switch exhibited a power gain of 28.9 dB and a high power-added efficiency of 27.0% at 20.5-dBm output power. The receiver block of a low-noise amplifier with the antenna switch exhibits a noise figure of 3.4 dB and a gain of 11.1 dB.

A low-voltage GaAs power amplifier for 1.9-GHz digital mobile communication applications such as PHS handsets has been developed, using refractory WNx/W self-aligned gate MESFETs with p-pocket layers. This power amplifier operates with a single low 2-V supply, and an output power of 21.0 dBm, a power gain of 22.3 dB, a low dissipated current of 162.9 mA and a high power-added efficiency of 38.5% were attained with a low 600-kHz adjacent channel leakage power of -58.0 dBc for 1.9-GHz /spl pi//4-shifted QPSK modulated input.

A GaAs power amplifier with a low-distortion, 10-dB gain attenuator has been developed for 1.9-GHz personal handy phone system (PHS). Single low 2.4-V supply operation was achieved by using power MESFETs with p-pocket layers. Furthermore, on account of an attenuator with cascaded shunt FET structure, very low 600-kHz adjacent channel leakage power (ACP) with sufficient, constant output power was attained regardless of any controlled gain. An output power of 21.1 dBm, a low dissipated current of 157 mA and a high power-added efficiency of 37.2% were obtained with ACP of -55 dBc.

We have developed a GaAs direct-conversion 1/4/spl pi/ shifted QPSK modulator IC equipped with variable attenuators for controlling the output power level of the 1.9 GHz personal handy phone system (PHS). The IC was successfully demonstrated showing state-of-the-art performance with the image rejection ratio of more than 36 dB at a low input power of -10 dBm in the 1.9 GHz frequency range. By using the "Gate Current Control method by Pull-down FET's" (GCCPF), the equipped attenuators vary the output power from 0 dB to -28 dB by 4 dB step. The IC operates at a 2.7 V supply with the power dissipation of 259 mW. The 2.6/spl times/4.6 mm/sup 2/ chip with about 400 elements was fabricated by a 0.5 /spl mu/m WNx-gate BPLDD GaAs MESFET process.

High-speed multiplexers (MUXs) are key components in optical-fiber communication systems. MUXs with a higher operating frequency are desirable to realize increases in data transmission capacity. Furthermore, MUXs with a higher number of bits are also desirable to reduce the number of high-speed system components. This 20 GHz 8b MUX is based on source-coupled FET logic (SCFL) and fabricated using a 0.5 /spl mu/m GaAs MESFET process based on conventional optical lithography and ion implantation. This is the fastest reported 8b MUX. >

The Schottky barrier of reactively sputtered WN x to p-type GaAs has been investigated. Postdeposition heat treatments above 500°C led to a reduction in the barrier height but for lamp annealing at 740°C the barrier heights are 0.68 eV. Self-aligned p-channel MESFET's were fabricated with WN x gates by a refractory metal process involving the above heat treatment. The Schottky-barrier heights were close to the expected values. K-values of FET's with 2 µm × 24 µm gates were 0.088 mA/V2, consistent with previously reported results. SPICE simulation studies carried out for a variety of complementary-type logic gates, indicate that power dissipation × delay time products of less than 10 fJ may be achievable over the power range 5-50 µW/gate. Thus complementary logic may be useful for applications where low power dissipation is at a premium.

A 2K-gate DCFL GaAs gate array has been successfully fabricated with a WN gate self-alignment GaAs MESFET process. Chip size was 4.59 mm/spl times/4.73 mm. A basic cell, consisting of one DFET and three EFETs, can be programmed as an inverter or a two or three-INPUT NOR gate by personalizing with first- and second-level interconnection and via hole masks. The I/O buffer was implemented with a large DCFL push-pull circuit. The unloaded propagation delay time was 42 ps/gate at a power dissipation of 0.5 mW/gate. The increases in delay time due to various loading capacitance were 11-ps/fan-in. 16-ps/fan-out, 59-ps/1-mm interconnection and 0.95 ps/crossover (area: 2 /spl mu/m/spl times/3 /spl mu/m). An 8/spl times/8-bit parallel multiplier was fabricated on this gate-array chip. A multiplication time of 8.5 ns was achieved at a power dissipation of about 400 mW including I/O buffers.

The transient optogalvanic spectrum of Ne 585.2, 588.2, and 603.0 nm lines was observed using a chopped CW dye laser in the negative glow region of a hollow cathode lamp. The analysis revealed that the signal originates mainly from the vicinity of the cathode surface and that the hitherto utilized model of the effect has to be generalized to include the colisional mixing among nearby levels into the rate equations for the population distribution among atomic levels.

Thermal-wave measurements are a very effective tool in the control of the threshold voltage V/sub th/ of GaAs MESFETS with a very thin (100-nm) active layer. A linear correlation is given between the thermal-wave signals and implantation into semi-insulating (SI) undoped LEC-grown GaAs substrates at 50 keV. In addition, the relation between the threshold voltage of GaAs MESFETs fabricated by direct Si/sup +/ implantation at 50 keV and dosage was experimentally obtained. Using these two results, the threshold voltage is easily predicted just after implantation by thermal-wave measurements and adjusted to the desired value by additional implantation. >

1985 IEEE International Solid-State Circuits Conference (ISSCC 85), Thursday, FEB 14, 1985 at Trianon Ballroom, 4:15 p.m.