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In this paper, we report on the device concepts for high-gain operation of a tungsten diselenide (WSe2) complementary metal-oxide-semiconductor (CMOS) inverter at a low power supply voltage (V dd ), which was realized by developing a doping technique and gate stack technology. A spin-coating with a fluoropolymer and poly(vinyl alcohol) (PVA) results in the doping of both electrons and holes to WSe2. A hybrid self-assembled monolayer/aluminum oxide (AlO x ) gate dielectric is viable for achieving high gate capacitance and superior interfacial properties. By developing the doping technique and gate stack technology, we experimentally realized a high gain of 9 at V dd of 0.5 V in the WSe2 CMOS inverter. This study paves the way for the research and development of transition metal dichalcogenides-based devices and circuits.

We have successfully fabricated chip-level integrated nMISFETs with sputtered molybdenum disulfide (MoS 2 ) thin channel using sulfur-powder annealing (SPA) and molybdenum disilicide (MoSi 2 ) contact which show n-type-normally-off operation in accumulation. SPA intentionally compensated sulfur vacancies of sputtered MoS 2 film. Eventually, we achieved a normally-off operation, which realizes industrial chip-level LSIs with MoS 2 channel.

The annealing temperature dependent electrical characteristics of La2O3 gate dielectrics for W gated AlGaN/GaN high electron mobility transistors (HEMTs) have been characterized. The threshold voltage (Vth) has been found to shift to positive direction with higher temperature annealing, exceeding those of Schottky HEMTs, presumably attributed to the presence of negative fixed charges at the interface between La2O3 and AlGaN layers. At a high temperature annealing over 500 °C, a high dielectric constant (k-value) of 27 has been achieved with poly-crystallization of the La2O3 film, which is useful to limit the reduction in gate capacitance. A high k-value for La2O3 gate dielectrics and the presence of negative charges at the interface are attractive for AlGaN/GaN HEMTs with low gate leakage and normally-off operation.

This study reposts the fabrication of top-gate molybdenum disulfide (MoS2) field-effect transistor (FET) by the transfer printing of a gate dielectric in conjunction with a poly(vinyl-alcohol) (PVA) coating for carrier doping. The spin-coated PVA film increases the carrier concentration in MoS2, while the back-gate MoS2 FET cannot be turned off. The transferred top-gate structure with the PVA coating makes it possible to turn off the fabricated device without permanent damage to MoS2. The results of this study suggest interesting directions for the research and development of two-dimensional material-based functional devices.

Since layered semiconductor tungsten diselenide (WSe2) has no dangling bond and a relatively large band gap, it is expected as a channel material for an application of field effect transistor (FET)[1]. On the other hand, high energy process destroys the crystal structure of the layered semiconductor. In this context, carrier doping by the low energy process is important for improving the electrical characteristics. This study reports that CYTOP (9 wt%) was applied as a doping material on the WSe2 FET for p-type operation by spin coating and the impact of contact doping on the electrical characteristics was investigated. A SiO2 gate dielectric was formed on a heavily-doped p-Si substrate (p+-Si) using thermal oxidation for back-gate structure. Next, a source / drain of Au (40 nm) / Ti (10 nm) was prepared by using photolithography and lift-off. Using a PDMS stamp and a micromanipulator, WSe2, which was mechanically peeled off using Scotch tape, was transferred between the source and drain to fabricate a back-gate WSe2 FET. After measuring the electrical characteristics without CYTOP, CYTOP was applied on the WSe2 FET surface using a spin coating. Then, the electrical characteristics with CYTOP were measured again. In this study, the annealing was performed for 30min at 200 ° C and 250 ° C. Id-Vg characteristics as a function of annealing temperature of the fabricated back gate WSe2 FET are shown in Fig. 1. From the Fig. 1, it can be confirmed that WSe2 FET shows p-type operation. Moreover, it can be confirmed that the drain current increases by applying the CYTOP, while the low drain current was observed without CYTOP. It was found that the drain current was increased with increasing the annealing temperature. [Acknowledgments] The authors would like to thank Professor Y. Kawano, Professor T. Hoshii, Professor I. Muneta, Professor K. Kakushima, Professor K. Tsutsui, and Professor H. Wakabayashi of Tokyo Institute of Technology for their continuous support in the experiments. This study was supported by JST CREST (Grant No. JPMJCR16F4) and a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616). [References] [1] In-Tak Cho et al., Applied Physics Letters 106, 023504 (2015). Figure 1

We demonstrate chip-level integrated n-type metal–insulator–semiconductor field effect transistors with a sputtered molybdenum disulfide (MoS2) thin channel and titanium nitride top-gate electrode, all defined by optical lithography. The devices successfully exhibit a normally-off operation and the highest off-voltage. This is achieved by the single dielectric layer and forming gas annealing, which reduce the positive fixed charges in aluminum oxide (Al2O3) film and interface trap densities between the MoS2 and Al2O3 films, respectively. These normally-off MISFETs are suitable for internet-of-things edge devices with low energy consumption using two-dimensional materials in the future.

Recent progress of nanotechnology has made possible observations of unique characteristic of nano-structure which are not possible in bulk semiconductors. In this talk, novel properties and possible device applications of quantum dots (OD), nanowires (1D) and atomic layer (2D) devices are discussed.

This study reports the impact of interfacial engineering by means of SAM (Self-assembled monolayer)-based gate dielectric on channel mobility in molybdenum disulfide (MoS 2 ) field-effect transistors (FETs). A gated four-probe method was implemented to eliminate the effect of contact resistance on channel mobility. The formation of SAM significantly plays an important role in the improvement of channel mobility as high as 19 cm2/Vs in Mos2FETs because the superior interfacial properties can be realized in MoS 2 /SAM structure. This study opens up interesting direction of interface engineering for research in the applications and developments of 2-dimensional materials-based thin film devices.

This study reports the polarity control in WSe 2 FET using global p+-type Si back gate architecture in conjunction with Al gate. By using WSe 2 as channel material and Au as source and drain contact metal, both hole and electron can be injected into the channel layer. As a result, p-type and n-type operation was experimentally demonstrated by applying appropriate back bias condition.

This study describes the fabrication of hybrid SAM/HfO x gate dielectrics by the radical oxidation in molybdenum disulfide (MoS 2 )field-effect transistors (FETs). The fabrication process involves the radical oxidation to form HfO x at the surface of metallic HfN, SAM formation by immersion, and deterministic transfer of MoS 2 flakes. A subthreshold slope (SS) of 75 mV/dec and small hysteresis were demonstrated with the hybrid SAM/HfO x gate dielectrics accompanied by a low gate leakage current. TEM observation revealed a uniform formation of HfO x at the surface of HfN. This study opens up intriguing possibilities of radical oxidation process for research in the applications and developments for functional electronic devices.

Layered semiconductors of transition metal dichalcogenides (TMDC) have been considerable attention for both scientific interest and practical applications [1]. This paper describes a method to fabricate TMDC field-effect transistors (FETs) with heavily-doped silicon on insulator (SOI) substrate. The FETs are constructed by transfer of TMDC crystals on the surface of pre-patterned SOI substrate. This method can eliminate the deposition of metals and dielectrics on a TMDC surface [2]. In addition, various TMDC can be applied to the fabrication of FETs. The heavily-doped SOI serves as a gate electrode, while an efficient injection of carriers into TMDC can be accomplished because of overlap structure between gate electrode and source/drain contacts. The device characteristics are investigated.

Contributions of gate metal to electrical characteristics in AlGaN/GaN Schottky HEMT are reported. The focus is on the collapse of drain current associated with Schottky metals. Ni and W gate introduce electrically active defects under the gate metal in AlGaN layer. These electrically active defects induce the current collapse, higher gate leakage current, and frequency dispersion in C-V characteristics. Contrarily, TiN metal seems to mitigate the appearance of such electrically active defects. The observed current collapse is not the permanent but the recoverable degradation by means of light exposure irrespectively of the gate metals, suggesting the involvement of electron trapping on defects, particularly at the gate edge on the drain side where the electric field is the highest. The nitrogen vacancies in the AlGaN layer underneath the Schottky gate are plausible origin that is responsible for the electrically active defects based on the dependence of nitrogen concentration in TiN metal on the current collapse, which can be explained in terms of nitrogen diffusion from the AlGaN layer to the gate metal.

This study describes the transfer printing of an Al2O3 gate dielectric for the fabrication of a top-gate MoS2 FET. The transfer printing of the Al2O3 gate dielectric involves the peeling-off process, etching of the sacrificial layer, and stacking on the MoS2. This method eliminates the direct deposition of Al2O3 gate dielectric on fragile MoS2 and provides an abrupt Al2O3/MoS2 interface. The fabricated FET has small hysteresis, low leakage current, a subthreshold slope of 120 mV dec−1, and a carrier mobility of 7.3 cm2 V−1 s−1. The transfer printing approach is applicable to various high-k gate dielectrics and layered materials for constructing functional devices.

The gate leakage current in advanced metal gate/high- K (EOT ≈ 0.6 nm) nMOSFETs with severe gate-to-drain dielectric breakdown is investigated in detail. Even though several models have been proposed in the past to deal with this issue, they are mainly intended to be used in circuit simulation environments. On the contrary, we report in this work an analytic expression for the gate current based on the solution of the generalized diode equation. The model has been tested not only for positive drain and gate voltage conditions but also for negative biases.

This paper reports on the control of the direct-contact La-silicate/Si interface structure with the aim of achieving scaled equivalent oxide thickness (EOT) and small interface state density. The interface state density at the direct-contact La-silicate/Si interface is found to be reduced to 1.6 × 1011 cm-2eV-1 by annealing at 800 °C for 30 min in forming gas ambient, whereas excess silicate reaction concurrently induced a significant increase in EOT. By utilizing metal-inserted poly-Si (MIPS) stacks and their annealing at high temperature, the increase in EOT is drastically suppressed. At the same time, a superior interfacial property is obtained because the Si layer in the MIPS stacks prevents the excess oxygen diffusion from the atmosphere during the annealing process. As a result, the effective electron mobility of 155 cm2/V·s at 1 MV/cm and an EOT of 0.62 nm are successfully achieved by utilizing direct-contact La-silicate/Si structure. This result is comparable with the recorded effective electron mobility achieved by utilizing Hf-based oxides/Si structure. This demonstrates the advantage of our proposed method to realize the scaled EOT with a superior interfacial property for state-of-the-art metal-oxide-semiconductor field-effect transistors.

Effects of a thin metal layer (W, Ta, or Mo) inserted at the interface between La2O3 high-k gate dielectric and TiN gate metal were studied. It was found that the inserted metal layer plays crucial role in determining the electrical characteristics of the TiN/Metal/La2O3/Si gate stack. Our results show that EOT can be scaled to 0.5nm and below by inserting a W layer with optimum thickness at the interface between La2O3 high-k gate dielectric and the TiN gate metal.

Metal-Inserted Poly-Si (MIPS) stacks for gate oxide scaling have been presented with La2O3 gate dielectrics. An equivalent oxide thickness (EOT) of 0.69nm can be achieved with good interfacial property by high temperature annealing. The flatband voltage (VFB) can be modulated by oxygen incorporation in conjunction with Si removal process while EOT degradation is less than 1Aå.

Electrical properties of TiN/W/La2O3 high-k gate stack were studied by fabricating MOS capacitors. Obtained results showed that a W layer inserted at the interface between TiN and La2O3 is the key factor in suppression of the equivalent oxide thickness (EOT) increment during the annealing process. An EOT of 0.43nm was achieved in the gate stack with a 3nm W inserted layer after annealed at 800oC in a forming gas ambient. Our results show that TiN/W/La2O3 gate stack is one of the promising candidates in realizing high-k gate stack with EOT 0.5nm and beyond.

An aggressive equivalent oxide thickness (EOT) scaling with high-k gate dielectrics has been demonstrated by ultra-thin La"2O"3 gate dielectric with a proper selection of rare earth (La-, Ce- and Pr-) silicates as an interfacial layer. Among silicates, Ce-silicate has shown the lowest interface-state density as low as 10^1^1cmv^-^2/eV with a high dielectric constant over 20. n-Type field-effect transistor (FET) with a small EOT of 0.51nm has been successfully fabricated with a La"2O"3 gate dielectric on a Ce-silicate interfacial layer after annealing at 500^oC. Negative shift in threshold voltage and reduced effective electron mobility has indicated the presence of fixed charges in the dielectric. Nonetheless, the high dielectric constant and nice interfacial property of Ce-silicate can be advantageous for the interfacial layer in highly scaled gate dielectrics.

In this paper, we developed a model for remote surface roughness scattering (RSR)-limited electron mobility in the inversion layer of nMOSFETs with high-k dielectrics. A Numerical method is applied to calculate RSR-limited electron mobility. It has been demonstrated that the RSR-limited electron mobility is highly degraded in the high electric field region.

Chemical bonding states and electrical characteristics of a La-silicate formed as a compositional transition layer at La2O3/Si interface has been examined. A direct contact of a high-k gate dielectric with Si substrate has been achieved without forming SiO2-based interfacial layer by forming a compositionally graded La-silicate layer, which is advantageous for equivalent oxide thickness (EOT) scaling. A transistor operation with an EOT of 0.48 nm has been demonstrated with low temperature annealing, however a degradation of effective mobility (μeff) has been observed. A high μeff of 300 cm2/V s with relatively low interfacial state density (Dit) of 1011 cm−2/eV can be achieved when annealed at 500 °C, indicating fairly nice interface properties of silicate/Si substrate. Mobility analysis has revealed an additional Coulomb scattering below an EOT of 1.2 nm, which is in good agreement with the negative shifts in threshold and flatband voltages. Moreover, increase in Dit and subthreshold slope have been observed while decreasing the EOT, suggesting the influence of metal atoms diffused from the gate electrode. A mobility degradation model is proposed using metal induced defects generation.

This study reports the electrical characteristics of La-Sc oxides complex and effect of nitrogen incorporation for applications to high-k gate stack. We found that V"f"b can be controlled by the ScO concentration. Moreover, large bumps in C-V curves, which indicate high interfacial state density, can be suppressed with large ScO concentration. nMOSFETs using the La-Sc oxides complex in the gate stack are fabricated. In addition, nitrogen incorporation into the La-Sc oxide films was fond to be useful to suppress the EOT growth during annealing at high temperatures.

A simple yet accurate model for the postbreakdown output characteristics of advanced n-MOS transistors with metal gate (W) and high-κ (La2O3, equivalent oxide thickness=0.6 nm) gate insulator is reported. The model specifically deals with the so-called linear response regime in which the transistor action is no longer operative after the failure event. By analyzing three particular cases of interest, it is shown that the proposed model is able to account for the conduction characteristics corresponding to failure sites located both at the center of the channel region and close to the source and drain contacts. A compact model for the bulk-drain current is included in order to simulate the departure from linearity occurring at the negative drain bias.

This study reports the control of threshold voltage (Vth) by engineering a gate metal electrode in molybdenum disulfide (MoS2) field-effect transistors (FETs). The fabrication process for gate stacks involves the deposition of aluminum oxides (AlOx) on a high-work-function metal and the subsequent formation of a self-assembled monolayer (SAM) by an immersion method. A positive Vth of 0.15 V was demonstrated using a platinum (Pt) metal as a gate electrode accompanied by a low density of traps at the interface owing to the close-packed SAM. Raman spectroscopy revealed that the transferred MoS2 has a multi-layer structure. The Pt gate electrode exhibits a Vth shift of about 1 V in the positive direction compared with the aluminum (Al) gate electrode. This Vth shift is consistent with the difference in the work function of Pt and Al gate metal electrodes. The low–temperature process employed in this study makes it possible to assemble dissimilar materials including the Pt metal, deposited AlOx, and organic SA...

We experimentally examine the effective mobility in nMOSFETs with La"2O"3 gate dielectrics without SiO"x-based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N"s=5x10^1^1cm^-^2 in the low 10^1^1cm^-^2eV^-^1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT.

Metal induced effects on electrical characteristics in AlGaN/GaN Schottky HEMT are reported. Focus is given to the collapse of drain current attributed to Schottky metal. Of particular interest for discussion is that TiN gate can suppresses the collapse of drain current compared with conventional Ni gate. Nitrogen concentrations in TiN gate are found to be correlated to the current collapse, indicating that the nitrogen vacancy is responsible for the traps in AlGaN/GaN HEMT. The reduction in a concentration gradient of nitrogen should be accomplished for preventing the formation of the traps. Because of the metal dependent collapse of the drain current, the traps are considered to be formed under the gate edge on the drain side in AlGaN layer.

A simple analytic model for the post-breakdown conduction characteristics in W/La2O3/p-type Si MOSFETs is reported. The model is based on the solution of the generalized diode equation and captures the behavior of the gate current (IG) as a function of the gate (VG) and drain (VD) voltages including both positive and negative biases. The devices were subjected to ramped voltage stress so as to induce the dielectric breakdown close to or at the transistor drain region.

Graphical abstractDisplay Omitted We model the effects of an oxide breakdown on the transistor behaviour.We consider the potentiometer model.We show how the relevant feature that characterize the dielectric breakdown affect the transistor's transconductances. In this work, the effects of a gate-to-channel dielectric breakdown on the output characteristics of advanced La2O3-based metal-oxide-semiconductor field-effect transistors (MOSFETs) are investigated. The electrical behaviour is modeled using a potentiometer-like resistor network. It is shown how the relevant features that characterize a breakdown event in an MOS transistor: location of the failure site along the device channel, post-breakdown oxide resistance, and post-breakdown channel resistance, affect the mutual and drain transconductances of the device. The connection with the nonlinear current source model for broken down transistors is also discussed.

This paper reports on detailed comparison between (100)- and (110)-oriented nMOSFETs with direct contact of La-silicate/Si interface structure for expansion to multi-gate architecture including FinFETs, trigate FETs, and nanowire FETs. Scaled EOT of 0.73 nm for (110)-oriented nMOSFETs has been achieved as well as (100)-oriented nMOSFETs. Although the large interface state density originating from (110) orientation was observed, fairly nice interfacial property was obtained from (110)-oriented nMOSFETs at scaled EOT region. Moreover, larger interface state density in (110) orientation did not affect on V th instability. It was found that V th shift of nMOSFETs is mainly caused by bulk trapping of electron in La-silicate as well as Hf-based oxides.

This paper reports device process approach for further EOT scaling with small interface state density based on controlling La-silicate/Si interface. The interface state density of 1.6 × 1011 cm−2 eV−1 can be achieved by annealing at 800 °C for 30min in forming gas while significant increase in EOT has been also observed. EOT increase caused by high temperature annealing has been drastically inhibited with MIPS stacks accompanied by high quality interface. The effective electron mobility of 155 cm2/Vsec at 1MV/cm with an EOT of 0.62 nm has been obtained in direct contact La-silicate/Si structure by combination of MIPS stacks with high temperature annealing.

In this paper, we report our approaches in realizing EOT of 0.5nm and below with rare earth La 2 O 3 high-k gate dielectric. An EOT of 0.43 nm was obtained from a TiN/W/La 2 O 3 (3nm)/n-Si capacitor by optimizing the thickness W layer. Our results show that a proper gate electrode is one of the most important factors for realizing EOT below 0.5nm.

A demonstration of V FB /V th tuning has been conducted by optimized annealing in oxygen ambient for direct contact of high-k with Si gate stacks. The amount of oxygen atoms has been controlled by optimized annealing temperature and the thickness of the gate electrode. The shift in V FB has been confirmed irrespective of gate dielectric materials and the thickness. The V th of pMOSFET can be controlled to positive direction by 520 mV without any EOT penalty. Once a shift in V FB /V th is obtained, the values are found to be stable even after following forming gas annealing.

A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (k av ) of 17.4 has been obtained and an extremely low gate leakage current (J g ) of 0.65 A/cm2. The flatband voltage (V fb ) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate layer can effectively shift the V fb to positive direction.

An aggressive EOT scaling with high-k gate dielectrics has been presented by selection of a rare earth silicate (La, Ce and Pr) as an interfacial layer with La 2 O 3 stacking. Among silicates, La 2 O 3 /Ce-silicate nFET has performed a small EOT of 0.51 nm with a reduced gate leakage current of 102 A/cm2. SrO capping further reduces the gate leakage current also with a smaller EOT with improved subthreshold slope. A guideline for EOT scaling using RE-silicate in combination with SrO capping is proposed.

Evolution of electronic trap generation in the highdielectric constant (Hκ) layer and the interfacial layer (IL) of the Hκ gate stack and their interdependency is examined at nanoscopic resolution using scanning tunnelling microscopy (STM). We observed experimentally (i) trap generation in the dielectric layer next to the cathode is generally mismatched with pre-existing traps in the IL which exhibit stress induced leakage current (SILC) characteristics. (ii) Pre-existing SILC trap can evolve into a percolation path within the dielectric layer. (iii) pre-existing leakage path in the Hκ can accelerate trap generation in the IL due to electric field enhancement. Based on the experimental insight, a model on how BD of the Hκ gate stack is triggered by traps in the Hκ and IL layers is proposed.

Advantage of La2O3 over HfO2 MOSFET has been experimentally examined. Silicate reaction especially observed at La2O3/Si interface has been found to suppress the formation of SiO2 layer to realize direct contact, which is useful for further scaling in equivalent oxide thickness (EOT). Due to the lack of interfacial layer, La2O3 has showed relatively high interfacial state density, however, the effective mobility has exceeded to that of HfO2 MOSFET. Mobility analysis has revealed an additional Coulomb scattering at small EOT, suggesting the influence of metal gate. A simple mobility degradation model is pointed out using metal induced defects.

The effect of remote Coulomb scattering on electron mobility in W/La2O3/Si gate stacked metal-oxide-semiconductor field-effect transistors (MOSFETs) was studied. Experimental results show that scattering caused by the Coulomb charges located near the W/La2O3 interface becomes a dominant factor for the mobility of MOSFETs with an equivalent oxide thickness (EOT) of 1 nm or less.

The authors analyzed the electrical properties of MOS capacitors with thulium oxide (Tm2O3) gate dielectrics and evaluated the thickness-dependent properties. The authors observed that a thin silicate layer (instead of an SiO2 layer) with a thickness of less than 1 nm had formed between the Tm2O3 and Si substrate after an annealing process at 500 °C. The authors obtained an effective oxide thickness of 0.55 nm with dielectric constants of 18 and 12 for Tm2O3 and its silicate, respectively. The leakage current properties with different thicknesses have revealed sufficient suppression by 2 orders of magnitude from the required levels. However, conduction mechanism analyses and a model to explain the flatband voltage (Vfb) behavior on different thicknesses showed the presence of charged defects in the oxides, which were mostly located at the Tm2O3 and silicate interface. The effective mobility of nFET showed degraded properties by Coulomb scatterings, which were consistent with the Vfb shift. The less reacti...

The impact of La2O3 insertion for HfO2 gated MOSFET is presented. The origin of a large negative shift in flat band voltage with La2O3 insertion has been carefully extracted to be the dipole presented at La2O3/SiO2 interface. An improvement in effective electron mobility without degrading the interfacial state density has been performed with thin La2O3 insertion for HfO2 MOSFET.

The tunneling current versus voltage characteristic of the Sc2O3∕La2O3∕SiOx high-κ gate stack is examined using scanning tunneling microscopy in ultrahigh vacuum. Different measurement bias polarities allow information on the location (i.e., in the high-κ or interfacial SiOx layer) of the electronic traps to be extracted. Two types of localized leakage sites may be distinguished. Lowering of the electron barrier height and trap-assisted tunneling are proposed as the two leakage mechanisms.