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In this article, we propose a double-sided electromagnetic bandgap (DS-EBG) structure for glass interposers (GIs) with low substrate loss to suppress power/ground noise. For the first time, we validated wideband power/ground noise suppression in the GI using the proposed DS-EBG structure based on dispersion analysis and experimental verification. We experimentally verified that the proposed DS-EBG structure achieved the power/ground noise suppression (below −40 dB) between 2.5 and 8.9 GHz in the GI. Derived stopband edges, $f_{L}$ and $f_{U}$ based on the dispersion analysis, and 3-D electromagnetic (EM) simulation showed a good correlation with measurements. The effectiveness of the proposed DS-EBG structure on the power/ground noise suppression is verified by analyzing noise propagation in the power distribution network and coupling to the GI channel. Using the 3-D EM simulation, we verified that the proposed DS-EBG structure suppressed the power/ground noise coupling and improved the eye diagram of the GI channel. Finally, we propose a design methodology to broaden the isolation bandgap or miniaturize the dimensions based on the dispersion analysis.

In this paper, we first propose power distribution network (PDN) model of the perforated power and ground (P/G) planes including substrate effects and multiarray through-silicon vias (TSVs) for a silicon interposer. Since it is almost impossible to simulate a high metal density perforated PDN structure, we first suggest a modeling methodology for P/G perforated planes to reduce simulation time significantly with a high accuracy. To obtain the PDN impedance of a silicon interposer faster, we convert the perforated planes to solid planes with a dielectric mixture. The capacitance (C) and conductance (G) component of perforated P/G planes are precisely estimated based on the conformal mapping method. From the estimated C and G, the physical dimension and material properties of the dielectric mixture of solid P/G planes are determined, respectively. Because silicon interposer PDN consists of a periodic structure, we design and analyze the unit cell of a PDN thoroughly. From the unit cell analysis, the electrical characteristic of an entire PDN for a silicon interposer is successfully estimated. The PDN impedance of the proposed solid and perforated P/G planes and simulation time to obtain each PDN impedance are compared and evaluated, respectively. The proposed methodology is validated by a full 3-D electromagnetic (EM) simulation in the frequency range from 0.01 to 20 GHz. We also proposed models of multiarray P/G TSVs that can be applied to the various P/G patterns for a silicon interposer. From the inductance matrix considering current directions, the self- and mutual inductances of TSVs are accurately calculated. Because quasi-transverse electromagnetic mode is propagated through TSVs and the substrate dielectric of a silicon interposer can be regarded as a uniform dielectric, the capacitance and conductance of TSVs can be calculated from the inductance matrix. The proposed model of multiarray TSVs is also analyzed and verified by EM simulations in the frequency range from 0.01 to 20 GHz with a high accuracy.

This paper, for the first time, proposed a novel eye-diagram estimation method for pulse amplitude modulation with N -level (PAM-N) signaling. For verification, a through-silicon via (TSV) channel was fabricated. Because the input of the proposed method is an insertion loss, the loss of the fabricated TSV channel was measured up to 110 GHz. The estimated eye diagrams and measured eye diagrams were compared for the same TSV channel. The proposed method and measurements have nearly the same eye-height and eye-width values at data rates of 2, 4, and 8 Gb/s. Therefore, the proposed method successfully provides PAM-N's eye diagram with the insertion loss. Furthermore, bathtub curves were compared for the proposed method and measurements. The proposed method provides a bathtub curve up to 10–12, but in contrast, the measurements only provide a bathtub curve up to 10–5 due to a limited number of samples. Both of the bathtub curves are nearly the same up to 10–5 in amplitude. In conclusion, the eye-diagram estimation method for PAM-N signaling is successfully proposed and verified.

In this paper, for the first time, we designed and analyzed channels between a graphic processing unit and memory in a silicon interposer for a 3-D stacked high bandwidth memory (HBM). We thoroughly analyzed and verified the electrical characteristics of the silicon interposer considering various design parameters, such as the channel width and space, redistribution layer via, and under bump metallurgy pads. In particular, we also considered the meshed ground planes used for the proposed transmission lines, which are microstrip and strip lines. Signal integrity (SI) of the proposed channels in the silicon interposer was successfully analyzed and verified using a full 3-D electromagnetic solver and circuit simulations. Based on the extracted lumped circuit resistance, inductance, conductance and capacitance parameters, we thoroughly analyzed the channel characteristics and identified the parameters that dominantly affect SI in relation to each frequency range. From the analyzed insertion loss and far end crosstalk, we verified SI of the silicon interposer by eye-diagram simulations in terms of eye-height voltage and timing jitter in the time domain. In the worst case, the eye-height voltage and timing jitter of the proposed microstrip lines are 0.911 V and 36.8 ps, respectively, with 72 mV of signal coupling. The eye-height voltage and timing jitter of the proposed strip line are 0.887 V and 42.1 ps with 34 mV of single couplings. We show that the proposed channels of the silicon interposer can successfully transfer data at a 2-Gb/s data rate. Finally, we propose concepts and solutions for the next-generation HBM interface with higher data rates up to 8 Gb/s.

In this paper, we design and measure 28 GHz band pass filter (BPF) based on glass interposer for 5G applications. We design the parallel coupled resonator BPF based on the glass interposer. To control the even- and odd mode characteristic impedance, we adopt the multi-layer ground. Also, to reduce the channel loss, the wide coupled channels for 28 GHz BPF are designed. Designed 28 GHz glass BPF was verified by simulation using the 3D-EM simulator. Also, Designed 28 GHz glass BPF was fabricated to verify the electrical performance through measurement. Simulated and measured insertion loss of the designed 28 GHz glass BPF is −2.4 dB and −3.4 dB at 28 GHz, respectively.

Advanced RF packages are demonstrate with active (low-noise amplifier, RF switch) and passive integration in ultra-thin 3D glass packages with miniaturization and enhanced performance. The novelty of this RF packages is three-fold: 1) Ultra-thin 100 μm glass, 2) Double-side thinfilm RF circuits interconnected with Through-Package Vias (TPVs), and 3) Direct assembly of the glass-core package to the board with Land Grid Array (LGA) connections. An innovative double-via process, starting from prefabricated vias in bare glass, polymer filling and via drilling, is utilized for a robust and high-yield substrate fabrication process. Scalable and low-cost panel laminate processes are utilized to form the RF circuits on the build-up layers. The performance benefits are demonstrated through interconnect loss, impedance match, electrical gain and noise figure measurements. Compared to existing RF substrates, the glass substrates show 2.5X miniaturization in substrate thickness with extensibility to thinner substrates.

In this paper, for the first time, we propose a processing-in-memory in high bandwidth memory (PIM-HBM) architecture for high bandwidth systems with low dynamic random-access memory (DRAM) access costs. The main concept of the proposed PIM-HBM architecture is to embed processing units into a logic base of high bandwidth memory (HBM) to decrease the energy consumption and latency of interconnections as the physical length between core and DRAM decreases. To verify the proposed PIM-HBM architecture, we designed on-chip and on-interposer I/O channels using a CMOS 0.18 µm process. We extracted channel parasitic using an electromagnetic (EM) solver and performed a SPICE simulation to compare the system performance of the proposed architecture with the conventional HBM. As a result, the performance of the proposed PIM-HBM architecture is successfully verified by reducing energy consumption and latency of interconnections by 77 % and 79 % compared to the conventional HBM system.

In this paper, we propose glass-interposer (GI) electromagnetic bandgap (EBG) structure with defected ground plane (DGP) for efficient and broadband suppression of power/ground noise coupling. We designed, fabricated, measured, and analyzed a GI-EBG structure with DGP for the first time. The proposed GI-EBG structure with DGP is thoroughly analyzed using the dispersion characteristics and estimated stopband edges, $f_{L}$ and $f_{U}$ . We experimentally verified that the proposed GI-EBG structure with DGP achieved power/ground noise isolation bandgap (below −30 dB) between $f_{L}$ of 5.7 GHz and $f_{U}$ of 11 GHz. Estimation of $f_{L}$ and $f_{U}$ using dispersion analysis, full 3-D electromagnetic (EM) simulation results, and measurement results achieved good correlation. Effectiveness of the proposed GI-EBG structure with DGP on suppression of the power/ground noise coupling to high-speed through glass via (TGV) channel is verified with 3-D EM simulation. As a result, the proposed EBG structure successfully and efficiently suppressed the power/ground noise coupling and improved the eye diagram of the TGV channel. Lastly, we embedded thin alumina film in the proposed EBG structure and achieved even broader power/ground noise suppression between 2.1 and 14.7 GHz.

In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f L and f U of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below –40 dB) between f L of 5.8 GHz and f U of 9.6 GHz. Derived f L and f U based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel.

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs $200\;{{\mu \text{m}}}$ away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.

In this paper, we, for the first time, modeled and analyzed through-silicon via (TSV) with an embedded high-density metal-insulator-metal (MIM) capacitor. For 2.5-D/3-D ICs, this technology could be a potential solution to improve electrical performance. We conduct the modeling and the proposed model were compared with an electromagnetic (EM) solver, to evaluate signal and power integrity (SI/PI). The analysis was performed based on the insertion loss and impedance in the frequency range from 0.01 GHz to 20 GHz. The dominant factors to determine the electrical characteristic were analyzed depending on the frequency range. In order to model the TSVs, the concept of loop inductance was applied. Then, the capacitance and conductance between the TSVs were calculated respectively including the MIM capacitance. From the results of modeling and EM simulations, it is predicted that the TSVs are beneficial to improve SI not PI. Because the equivalent capacitance is decreased in the low frequency range under 200 MHz and the equivalent conductance is increased in the high frequency range above 200 MHz

Bias-dependent power distribution network (PDN) impedance is analyzed with respect to MOS capacitor characteristics. The proposed analysis can be used to improve the PDN impedance of 2.5D and 3D ICs.

In this paper, we design and analyze the receiver channel of a glass interposer for a dual band Wi-Fi front end module (FEM). In RF systems, a RF sensitivity is the most important specification for a system performance and reliability. To guarantee a target RF sensitivity of the RF system, it is important to maintain a 50 Ohm impedance matching for RF channels. The 50 Ohm impedance matching of various transmission line structures is completely conducted for each layer of the glass interposer in a low band (2.4GHz – 2.5GHz) and high band (4.9GHz – 5.85GHz) respectively. Channel types for each layer are determined considering design rules and constraints. Moreover, we locate ground TGVs near signal TGVs as close as possible to suppress a ground-ground cavity resonance effect in the low band and high band. In order to test a suppression of the ground-ground cavity resonance, simulations that compare pitches between a ground TGV and signal TGV are conducted. Design considerations of receiver channels were analyzed and characterized by simulation results of channel insertion losses.

Simultaneous switching noise (SSN) occurs when clock synchronized core circuits switch simultaneously. Furthermore, a huge amount of the SSN generated by simultaneous switching current (SSC) with high power distribution network (PDN) impedance at anti-resonance can cause electromagnetic interference (EMI) problems and logic failure. In multi-core processors, the spectrum of SSC is varied by power management techniques such as dynamic voltage and frequency scaling (DVFS). However, conventional PDN cannot respond to these various SSC spectrum due to its passive characteristics. In this paper, an externally controllable on-interposer decoupling capacitance scheme, namely on-interposer active PDN, is proposed to efficiently suppress the SSN in 2.5D IC. The proposed scheme designed on the active silicon interposer can shift the frequency of the PDN anti-resonance peak with on-interposer decoupling capacitors controlled by external switching operation based on monitored SSN voltage. To verify the proposed scheme, it is modeled and analyzed in the frequency and time domain simulations. We have demonstrated that an efficient SSN suppression is achieved by obtaining the optimum on-interposer decoupling capacitance and the maximum ratio of the SSN suppression was 31.3%.

A 3-D stacked high bandwidth memory (HBM) becomes a promising solution to satisfy the memory bandwidth for the processor. Due to its unique memory architecture that consists of tremendous number of input/output (I/O), it is inevitable to employee Silicon based interposer. Therefore, power distribution network (PDN) design and analysis of HBM interposer becomes one of the important step to guarantee the performance of an entire memory interface. Since the back end of line (BEOL) process technology of a semiconductor industry is applied for HBM interposer, the control of a metal density and the management of wafer warpage are required. Therefore, we designed and analyzed meshed and grid type of PDN for HBM interposer because of the limit of a metal density. In addition, we also designed and analyzed PDN both a single- and double-sided interposer. Because, a double-sided interposer has an advantage of a warpage management compared to a single-sided interposer. For the suppression of simultaneous switching noise (SSN), PDN impedance with a decoupling capacitor scheme must be properly analyzed. In this paper, a single- and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV). PDN impedance of HBM interposer is simulated and analyzed in the frequency range from 100 MHz to 20 GHz. Based on the designed HBM interposer, we shows the great potential of HBM interposer in terms of the reduction of PDN impedance to suppress SSN with a metal-insulator-metal (MIM) decoupling capacitor.

In this paper, a bump-less high-speed through silicon via (TSV) channel is proposed for terabyte/s bandwidth 2.5D IC. The signal integrity of the proposed channel is analyzed based on the frequency and time domain simulation. To analyze the signal integrity of the proposed channel minutely, the proposed channel and the conventional channel are simulated and compared respectively. Moreover, unlike the conventional channel, the signal integrity of the proposed channel is significantly affected by the coupling pads capacitance. Therefore, the proposed channel performance is investigated with different coupling pads capacitances.

In this paper, eye-diagrams of coupled microstrip channel on Printed Circuit Board (PCB) are estimated using equivalent circuit model. The equivalent circuit model has RLGC terms which are calculated from the physical dimensions of the coupled microstrip channel. Since the coupled microstrip channel is modeled by physical dimensions, eye-diagrams are estimated without 3D Full EM simulation, which needs long simulation time to extract channel performance. In addition, the equivalent circuit model enhances physical insight of the coupled channel and crosstalk effects. To verify the equivalent circuit model, frequency and time domain simulations are performed. As a result, worst eye-diagrams are estimated and compared with the 3D Full EM simulation.

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

In this paper, we compare and analyze power/ground noise coupling in silicon, organic and glass interposers. We first compare the power/ground noise coupling of each interposer by analyzing transfer impedances of power distribution networks (PDNs). Due to low loss of the organic and glass substrates, at certain frequencies, transfer impedances increase dramatically and. In order to analyze the effects of the power/ground noise propagation in the PDN and coupling to through via channel we induced clock signals to each interposer's aggressor through via channel with data rate corresponds to the PDN (1,0)/(0,1) resonance frequency to load the power/ground noises in the PDN. We monitored the coupled voltages in the PDNs and compared eye-diagrams of the victim through via channels. Due to the low loss of the glass substrate, glass interposers turned out to be most vulnerable to the power/ground noise. We suppressed PDN transfer impedance of the glass interposer using decoupling capacitors and electromagnetic band gap structure.

Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon interposer due to its capability to process narrow signal width and space. Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM interposer successfully, the signal optimization of HBM interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.

Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

Recently, IT trends such as big data, cloud computing, internet of things (IoT), 3D visualization, network, and so on demand terabyte/s bandwidth computer performance in a graphics card. In order to meet these performance, terabyte/s bandwidth graphics module using 2.5D-IC with high bandwidth memory (HBM) technology has been emerged. Due to the difference in scale of interconnect pitch between GPU or HBM and package substrate, the HBM interposer is certainly required for terabyte/s bandwidth graphics module. In this paper, the electrical performance of the HBM interposer channel in consideration of the manufacturing capabilities is analyzed by simulation both the frequency- and time-domain. Furthermore, although the silicon substrate is most widely employed for the HBM interposer fabrication, the organic and glass substrate are also proposed to replace the high cost and high loss silicon substrate. Therefore, comparison and analysis of the electrical performance of the HBM interposer channel using silicon, organic, and glass substrate are conducted.

With the advent of 2.5D and 3D IC, micro bumps has been highlighted as the core technology for realization of 2.5D and 3D IC. However, due to the difficulties about fabrication of reliable and cost-effective micro bumps, resulting in decrease in the final chip yield. In this paper, we propose a bump-less interconnection for high-speed signaling in 2.5D and 3D IC. In the proposed interconnection, high speed signal is transmitted via coupling pads instead of micro bumps. Signal integrity of the proposed interconnection is analyzed by simulation in the frequency- and time-domain. For a more detailed analysis, the proposed interconnection and the interconnection with the micro bumps are compared. In addition, because the silicon, organic and glass interposer have been widely employed for the 2.5D and 3D IC packaging, signal integrity of the proposed interconnection on three types of the interposer is compared and analyzed.