49 results on '"Tuck, Barbara"'
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2. Testing fully diffused blocks embedded in complex ASICs
3. OVI, IEEE meet on standardization of Verilog HDL
4. FPGA vendors turn their attention to tools
5. Analog designers still trail behind their digital counterparts
6. ASIC testability tools force trade-offs in silicon, performance and coverage
7. Technologies move toward hardware/software codesign
8. FPGAs race for the gold in product development
9. Pinouts and performance drive PAL choices
10. What do digital designers need to master the art of analog design?
11. Designers must look beyond the obvious to discover the promise of synthesis
12. High-density ASICs force focus on testability; getting an ASIC of 20,000-plus gates to market on time means building testability into the design flow
13. Network-distributed processing reduces run times for complex designs
14. High-speed PALs keep pace with today's processors
15. High-density gate arrays: products too far ahead of technology?
16. Is synthesis the solution for testing complex ASICs?
17. FPGA, complex PLD vendors rush to support silicon with advanced tools
18. EDA leaders getting serious about automatic test generation
19. ASIC choices increase for mixed 3-V/5-V designs
20. VHDL poised to overtake Verilog as support grows
21. High-level synthesis unlocks potential of FPGAs
22. Chase for process portability prompts advances in cell library tools
23. PLDs catch up to FPGAs in logic capacity and I/O
24. Denser, faster FPGAs encroach further on masked gate arrays
25. Vendor-independent floorplanner links synthesis with ASIC layout
26. Timing-driven partitioning tool splits design into multiple FPGAs after mapping
27. EDA vendors push to boost top-down design productivity
28. Split decision on HDLs forces VHDL/Verilog coexistence
29. Claims by FPGA tool vendors bury reality in noise
30. Fault simulator uses cycle-based algorithm
31. Emphasis shifts from density to I/O in low-density arrays
32. 1.25-GHz ECL array has on-chip phased-lock loop
33. Hardware accelerator speeds mixed-level simulation
34. Windows 3.0 extends PC-based PLD design limits
35. Verilog HDL simulator targets deep submicron ASIC designs
36. Behavioral synthesis tool generates state machine controller, datapath and memory
37. Floorplanner supports multiple place-and-route tools, block generators
38. FPGA tool features architecture-specific optimization
39. Low-cost VHDL synthesis tool for programmable logic line
40. 0.6-(micron) CMOS ASICs offer system performance solutions
41. Blox eliminates gate-level design for FPGAs
42. VHDL PLD compiler for state-machines
43. Mask-programmed device integrates up to 40 EPLDs
44. FPGA synthesis tool has architecture-specific optimizers
45. Single-chip decoder PLDs give users freedom of choice
46. Valid integrates PLD and FPGA synthesis within system design
47. Software lets ASIC designers compare FPGAs up front
48. Users want migration path
49. ASIC designers get first Japanese EDA supplier
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