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This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital). [ABSTRACT FROM AUTHOR]

Probabilistic computing can solve complex combinatorial optimization problems more efficiently than conventional deterministic computing. A probabilistic bit (p‐bit) with an n‐p‐n bistable resistor (biristor) is demonstrated for probabilistic computing. It is fabricated on an 8‐inch wafer with complementary metal–oxide–semiconductor (CMOS) compatible technologies. Its stochastic behavior of threshold switching, which is based on the phenomenon of a single transistor latch, provides output with a Boltzmann distribution. The p‐bit is composed of a biristor, a serial resistor, and a comparator. The output probability of the biristor‐based p‐bits shows a sigmoidal relationship with the input voltage, showing typical p‐bit characteristics. Invertible Boolean logic operations with p‐bits are demonstrated, and weighted maximum Boolean satisfiability problems are solved with high energy efficiency and accuracy. The biristor‐based p‐bits with perfect CMOS compatibility show sufficient device stability, demonstrating the possibility of large‐scale integration with a p‐bit array for complex optimization solvers. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

This paper presents CMOS and CNFET based hysteresis voltage comparators for low-voltage applications. The proposed CMOS and CNFET hysteresis comparators require merely 1.6 and 0.26 µW of power, respectively, which is less than one tenth of the power dissipated by the other advanced hysteresis comparators designs available in literature. The propagation delay observed in the proposed CMOS and CNFET hysteresis comparators are 162 and 47 ps, respectively, which is almost half the delay exhibited by the other hysteresis comparators. Overall, a 93–99% reduction in Power Delay Product (PDP) can be achieved. Furthermore, the proposed design requires only nine transistors compared to the 11–17 transistor requirement in conventional hysteresis comparators, thus saving up to 47% of chip area. [ABSTRACT FROM AUTHOR]

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

An energy-efficient, low-noise, and high-speed dynamic comparator is proposed in this work. The comparator uses two pre-amplifiers to have a two-stage operation for reduced kickback noise. It also incorporates the adaptive current reuse (ACR) technique for reduced latency and high-speed operation. The proposed comparator is designed and simulated in a 65-nm UMC CMOS process using a 1.2-V power supply. The performance of the design is verified using post-layout simulation and also through Monte Carlo simulations. The resultant offset standard deviation of 8 mV is observed, which is 3 times less compared to the conventional design. The maximum operating frequency of the comparator is 1 GHz. The worst-case energy consumption is 67 fJ with an average latency of 70 ps. The kickback noise of 5.5 mV is observed for the entire working range, which is almost 10 times less compared to the conventional dynamic comparator at 500 MHz clock frequency. [ABSTRACT FROM AUTHOR]

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive-approximation register (SAR) analogue-to-digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high-resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor-resistor (C-R) hybrid digital-to-analogue converters (DACs). The prototype ADC implemented in a 28-nm CMOS process demonstrates measured differential and integral non-linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal-to-noise-and-distortion ratio (SNDR) and spuriousfree dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm² and consumes 3.98 mW at a 1.1-V supply voltage. [ABSTRACT FROM AUTHOR]

Localized data conversions for sensors placed under harsh environmental conditions often require Analog to Digital Converters (ADC) capable of working under wide operating temperature range. Even though the fastest analog to digital converter, flash ADC is omitted from the high temperature regime due to the requirements of reference voltage source, reference voltage divider and a comparator array capable of providing stable operation under wide operating temperatures. A CMOS Schmitt inverter-based internal reference comparator array for flash ADC which is efficient in terms of area and power consumption, capable of working under wide temperature range is presented in this paper. The proposed idea replaces the reference voltage source, resistive reference voltage divider and differential comparator array of a conventional flash ADC by an array of suitably sized Schmitt inverters. The circuit was simulated for static and dynamic characteristics with gpdk 180 nm library using cadence virtuoso simulation suite. The voltage transfer characteristic curve (VTC) of the proposed comparator array was found invariable when a temperature sweep in the range of −40 to 170 degree Celsius was performed. Each of the comparator in the proposed array consumes a silicon area of 40.68 u m 2 and the average dynamic power consumption per cycle is estimated as 103.1 uW. [ABSTRACT FROM AUTHOR]

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

We present a highly robust 12-bit, 100 kS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that excels in mitigating the effects of mismatch, temperature variations and process corners. A modified hybrid switching method is developed in design of the Capacitive Digital-to-Analog Converter (C-DAC) that saves 17 % of the DAC power consumption. Furthermore, we utilize a switched local feedback loop in the pre-amplifier circuit of the comparator that significantly minimizes the offset. Using this technique, the 3-sigma offset is reduced from 11.33 mV to 0.37 mV. Moreover, a high performance latched-based Bit Slice Unit (BSU) is proposed to preserve the successive codes during each conversion. Designed in 65 nm CMOS technology, the ADC operates in −55 °C to +125 °C temperature range, consuming only 1.55 μW with a 0.7V supply voltage and occupying a 0.6 mm2 area. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoM A) of 25.12 fJ*mm2/conversion-step. [ABSTRACT FROM AUTHOR]

This work describes a 4-bit Flash ADC with low power consumption. The performance metrics of a Flash ADC depend on the kind of comparator and encoder used. Hence openloop comparator and mux-based encoder are used to obtain improved performance. Simulation results show that the simulated design consumes 0.265mW of power in 90nm CMOS technology using cadence-virtuoso software. The circuit operates with an operating frequency of 100MHz and a supply voltage of 1V. [ABSTRACT FROM AUTHOR]

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35 μ m CMOS AMS process technology with 3. 3 V supply voltage and an input common-mode range of 1. 1 5 – 2. 1 5 V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of 3 2. 3 2 mV with 2. 4 9 mV 3 σ deviation, a slew rate of 8. 2 9 V/ns with 0. 4 5 V/ns 3 σ deviation, and a propagation delay of 4. 1 6 ns with 0. 1 5 ns 3 σ deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of 6 3. 0 1 ∘ , and a high-gain of 7 9. 2 2 dB with 1. 9 2 ∘ and 4. 8 6 dB 3 σ , respectively, by using 1 pF load capacitance. [ABSTRACT FROM AUTHOR]

The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1– σ input offset voltage and average input voltage error due to kickback noise are 2.48 mV and 0.824 μ V, respectively at 0.8 V power supply with 34.32 μ m2 active area. [ABSTRACT FROM AUTHOR]

Comparator is an essential building block in many digital circuits such as biometric authentication, data sorting, and exponents comparison in floating-point architectures among others. Quantum-dot Cellular Automata (QCA) is a latest nanotechnology that overcomes the drawbacks of Complementary Metal Oxide Semiconductor (CMOS) technology. In this paper, novel area optimized 2n-bit comparator architecture is proposed. To achieve the objective, 1-bit stack-type and 4-bit tree-based stack-type (TB-ST) comparators are proposed using QCA. Then, two tree-based architectures of 4-bit comparators are arranged in two layers to optimize the number of quantum cells and area of an 8-bit comparator. Thus, this design can be extended to any 2n-bit comparator. Simulation results of 4-bit and 8-bit comparators using QCADesigner 2.0.3 show that there is a significant improvement in the number of quantum cells and area occupancy. The proposed TB-ST 8-bit comparator uses 2.5 clock cycles and 622 quantum cells with area occupancy of 0.49 µm2 which is an improvement by 10.5% and 38%, respectively, compared to existing designs. Scaling it to a 32-bit comparator, the proposed architecture requires only 2675 quantum cells in an area of 2.05 µm2 with a delay of 3.5 clock cycles, indicating 9.35% and 28.8% improvements, respectively, demonstrating the merit of the proposed architecture. Besides, energy dissipation analysis of the proposed TB-ST 8-bit comparator is simulated on QCADesigner-E tool, indicating average energy dissipation reduction of 17.3% compared to existing works. [ABSTRACT FROM AUTHOR]

This study describes a novel bidirectional current shunt monitor (CSM) circuit operating at both positive and negative common-mode (CM) voltages. The proposed CSM circuit mainly consists of two comparators, three error amplifiers, several current-mirror transistors and a few resistors. One comparator is used to detect current flowing direction, and the other one is utilized to ensure good operation of CSM circuit with both positive and negative CM voltages. The proposed CSM circuit has been implemented in SMIC 0.18 μ m standard CMOS process and its performances have been verified by simulations. The simulated results show that the proposed CSM circuit, at a supply voltage of 5 V and with an input CM voltage range from − 4 to 4 V, can sense a voltage difference of 4–40 mV and keep a constant scaled gain of 100 V/V. The gain error is less than 0.65% and the common-mode rejection ratio (CMRR) is higher than 130 dB at 1 kHz. Simulation results show that the output voltage of CSM circuit varies linearly with the CSM input sense voltage. [ABSTRACT FROM AUTHOR]

In-memory computing based on multivalued memristive device opens the vision of building computing system with less resource and high performance. In this article, we achieved three distinguishable resistance states in mature one-transistor-one-resistor (1T1R) memristor. Furthermore, based on a single multivalued 1T1R device, for the first time, we successfully demonstrated an area-efficient in-memory digital comparator, which will cost five logic gates in complementary metal oxide semiconductor (CMOS) approach. The method is also easily expanded to multibit. Our work could be a representative of using multivalued nonvolatile memory device in digital information processing with improved performance. [ABSTRACT FROM AUTHOR]

This paper presents a power and area efficient pseudo single ended switching ADC for portable biomedical signal monitoring applications. The switching method features an 8-bit binary-weighted DAC array with a novel layout method called limited bottom-plate routing (LBPR) maintaining both feasibility and symmetry, a dynamic biased comparator and dynamic control logic. As a result, the proposed ADC saves 96.7% power consumption and 87.5% area occupation compared with conventional SAR ADC. Also, a novel DAC array layout method is promoted maintaining both feasibility and symmetry. A prototyped chip including a proposed ADC is fabricated in a 0.13 μm CMOS process. On condition of 0.6 V supply voltage and 10 kS/s sampling rate, the measured signal-to-noise-distortion (SNDR) and spurious free dynamic range (SFDR) are 57.8 dB and 64.3 dB, respectively. Besides, the ADC consumes only 40 nW power and 0.053 mm2 area achieving a figure-of-merit (FoM) of 6.26 fJ/conversion-step. Low power and low area occupation make it a good candidate for biomedical signal monitoring applications. [ABSTRACT FROM AUTHOR]

In this paper, an active CMOS rectifier with new delay compensation technique for wireless power transmission system is proposed. In order to reduce the delays of the comparators employed in the proposed rectifier, a new low-power common-gate comparator is proposed which presents higher speed compared with the conventional counterpart. Moreover, a negative feedback loop changes the bulk voltage of PMOS transistors in the comparator to compensate the remaining turn-off delay of the circuit and its variation against all process, voltage, and temperature variations. Therefore, due to the reduction in the delay and consequently the reverse current of the active diodes, power conversion efficiency and voltage conversion ratio (VCR) of the proposed rectifier are increased considerably. Besides, since the feedback signal is applied to the bulk terminal of transistors in the comparator, it does not need any extra circuitry for generating the required offset current. The proposed circuit is simulated in a standard 0.13-µm CMOS technology. Post-layout simulation results show that, with ± 1.2 V input amplitude, the proposed circuit presents a maximum efficiency of 86.7% with 200 Ω loading, a peak VCR of 97%, and a minimum voltage ripple of 6.5 mV with 2 kΩ loading. [ABSTRACT FROM AUTHOR]

A low-noise, high-speed, low-input-capacitance switched dynamic comparator (SDC) CMOS image sensor architecture is presented in this paper. The comparator design occupying less area and consuming lesser power is suitable for bank of comparators in CMOS image readouts. The proposed dynamic comparator eliminates the stacking issue related to the conventional comparator and reduces the offset noise further. The need for low-noise, low-power, area-efficient and high-speed flash analog-to-digital converters (ADCs) in many applications today motivated us to design a comparator for ADC. The rail-to-rail output swing is also improved. The input capacitance is reduced by using shared first-stage technique. The comparator is designed with constant I d / g m biasing to suppress the environmental drift. The simulation results from 45-nm and 65-nm CMOS technologies confirm the analysis results. It is shown that in the proposed dynamic comparator both the power consumption and delay time are significantly reduced. The maximum clock frequency of the proposed comparator can be increased to 3.5 GHz and 2.2 GHz at supply voltages of 1 V and 0.6 V, respectively. Simulations are carried out using predictive technology models for 45 nm and 65 nm in HSPICE. [ABSTRACT FROM AUTHOR]

Abstract A 10-bit 10-KS/s asynchronous successive approximation register (SAR) analogue-to-digital converter (ADC) in 180 nm CMOS process is proposed for low energy wireless senor network chip. Nanowatt power consumption magnitude can be achieved benefiting from the novel switch scheme which can reduce the average switching energy and area of the capacitive digital-to-analog converter (DAC) by 97.66% and 50% without reset energy compared to the conventional approach, respectively. Meanwhile, a cascode current is employed in the subthreshold dynamic comparator to suppress the total offset voltage (mean+3std) variation with the bulk-driven differential pair. As a consequence, the fluctuation of total offset voltage is only 0.28 mV when the input common-mode voltage operates from 200 mV up to 400 mV at 0.4 V supply. Simulation results indicate that a signal-to-noise-plus-distortion ratio (SNDR) of 58.75 dB and a power consumption of 30.4 nW can be achieved at 0.4 V supply voltage and a near Nyquist rate input, resulting in Walden's figure-of-merit (FOM w) of 4.32fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper proposes a current mode hysteretic buck converter with auto-selectable frequency locking. In this work, the hysteresis of the hysteretic comparator and the resistance of the feedback network are adjusted simultaneously to fix the switching frequency. The proposed switching frequency locking scheme can improve the power efficiency and fix the spectral components of the output at specific frequencies by suitably lowering the switching frequency under light load conditions. Implemented in a 65 nm complementary metal oxide semiconductor (CMOS), the proposed converter achieves peak efficiency of 96.5% for a 3.3 V input with less than 1.2% frequency error while locking at 1, 0.5, and 0.25 MHz. [ABSTRACT FROM AUTHOR]

A novel approach is proposed and discussed for designing CMOS double-tail dynamic comparator using the bulk-driven method. The bulk-driven method proposed thus far for low-power circuits result in reduced transconductance. The proposed technique uses the gate driven method to drive the inputs with bulk-driven loads. For the proposed comparator, mathematical analysis of delay and offset due to mismatch is presented. Additionally, a new optimized architecture of control unit is proposed to control both, offset voltage and kickback noise. To verify the outcomes, it is simulated in SPECTRE at 0.8 V of the supply voltage at 45 nm CMOS technology node. The proposed comparator achieves over 87% reduction in latch delay and 27% reduction of energy consumption over a conventional design. Monte-Carlo simulation is done to obtain the offset voltage, the result shows that the offset voltage is reduced by 62% using optimization technique. [ABSTRACT FROM AUTHOR]

A fully integrated RC oscillator is presented. A current-capacitor-based voltage average feedback(IC-VAF) technique is proposed to improve frequency stability. A trip voltage adjustable invert technique(TVAI) is proposed to avoid using comparators, thus saving power and area. The simulation results show that the power consumption is 24. 72 μ W at 1.2 V power supply, and the temperature coefficient is 25 ppm/°C from −40 °C to 125 °C, The calculated figures of merits(FOMs) F O M 1 and F O M 2 are 1. 24 nW / kHz and 157. 2 dBc / Hz , respectively. The oscillator occupies an active area of 0. 027 mm 2 in a 55 nm standard CMOS process. [ABSTRACT FROM AUTHOR]

A fast transient digital low-dropout regulator (LDO), in which the sampling clock is adaptively generated by a voltage-controlled oscillator, is proposed in this paper. In steady state, the LDO operates at a fine-regulation mode and the oscillator generates a low-frequency clock for low power consumption. When the output voltage exceeds the boundaries of overshoot or undershoot, the LDO switches into a coarse-regulation mode with a higher clock frequency and a shorter response time. To enhance the transient performance at near-threshold region, a three-stage high-speed comparator is further introduced. The designed digital LDO was fabricated in standard 180 nm CMOS process. Measured results show that the maximum variation of transient output voltage is 120 mV while the load steps from 2 to 22 m A with a 10 ns edge time. The proposed LDO obtains a low quiescent current of 14.5 μA with a 0.0587 ps figure of merit. [ABSTRACT FROM AUTHOR]

Purpose This paper aims to propose a low-power complementary MOS (CMOS) current sensor for control circuit in an integrated DC-DC buck converter.Design/methodology/approach The integrated DC-DC converter, which is composed of feedback control circuit and power block, is designed with 0.35-µm CMOS process. Current sensor in the control circuit is integrated with sense-FET and voltage-follower circuits to reduce power consumption and improve its sensing accuracy. In the current-sensing circuit, the size ratio of the power metal oxide semiconductor field effect transistor (MOSFET) to the sensing transistor (K) is 1,000, and a current-mirror is used for a voltage follower. N-channel MOS acts as a switching device in the current-sensing circuit, where the sensing FET is in parallel with the power MOSFET. The amplifier and comparator are designed to obtain a high gain and a fast transient time.Findings Experiment shows that the current sensor is operated with accuracy of more than 85 per cent, and the transient time of the error amplifier is controlled within 100 µs. The sensing current is in the range of a few hundred µA at a frequency of 0.6-2 MHz and an input voltage of 3-5 V. The output voltage is obtained as expected with the ripple ratio within 5 per cent.Originality/value The proposed current sensor in DC-DC converter provides an accurately sensed inductor current with a significant reduction in power consumption in the range of 0.2 mW. High-accuracy regulation is obtained using the proposed current sensor. As the sensor utilizes simple switch-type voltage follower and sense-FET, it can be widely applied to other low-power applications such as high-frequency oscillator and over-current protection circuit. [ABSTRACT FROM AUTHOR]

Circuit intricacy, high-speed, low-power, small area requirement, and high resolution are crucial factors for high-speed and low-power applications like analog-to-digital converters (ADCs). The delay analysis of classical dynamic latch comparators is presented to add more insight of their design parameters, which effects the performance parameter. In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and requires smaller die area. The proposed comparator benefits from a new shared charge logic based reset technique to achieve high-speed with low-power consumption. It is shown by simulation and analysis that the delay time is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 90 nm CMOS technology. The results show that, for the proposed comparator, the delay is 51.7 p s and consumes only 33.62  μ W power, at 1  V supply voltage and 1 GHz clock frequency. In addition, the proposed dynamic latch comparator has a layout size of 7.2μm × 8.1μm. [ABSTRACT FROM AUTHOR]

In this paper, a low-power DC voltage limiter is designed for radio frequency identification tags. In this design, the low-power bandgap reference (BGR) circuit, which is insensitive to temperature, and also the comparator are used for the voltage limiter circuit. To make the I-V curve approach the ideal one, four inverter stages are employed to the output of the comparator. The structure of the BGR and comparator use only MOSFET transistors that work in subthreshold region when the limiter is inactive. These two blocks have power consumption of 220 pW and 1300 pW, respectively. The limited output voltage is 1.5 V and the current consumption when the tag and the reader are far from each other is 31.56 nA, which is very insignificant compared with the total current consumption of the tag. The chip area of the voltage limiter circuit is 1936 μm2 . The simulation is done in 0.18 μm CMOS technology and the operational frequency is 960 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a new low-power and area-efficient parallel binary comparator design based on prefix tree structure. Due to its wide usage in central processing units, optimizing binary comparator for low power applications are need of the hour. A novel EX-OR-NOR gate is used in proposed binary comparator as pre-encoder to reduce area, power and delay. The simulation results performed using CADENCE for CMOS 180 nm – technology. The paper proposes two binary comparator architectures with improved performance. The proposed architecture result in a power reduction upto 25%, area (number of transistors) reduces upto 36% and improves the delay performance 27% compared to existing technique. [ABSTRACT FROM AUTHOR]

Low-power circuits are highly in demand in this power-hungry world of batteries and portable devices. Though many low-power techniques are prevalent at various stages of a VLSI design cycle, but most of them have retained their own domain. A novel, digital-in-concept, fully differential voltage comparator circuit has been implemented in this paper. This provides substantial reduction in the power consumption. It is highly cost-effective, both in terms of time and efforts as an analog circuit is being designed on digital basis. The proposed voltage comparator has been designed and simulated in Cadence Virtuoso Analog Design Environment using UMC 180nm CMOS technology at 1.8V supply. [ABSTRACT FROM AUTHOR]

Gain and offset represent two important measures to determine the accuracy of a comparator. Thus, analysis on these parameters is very important as they offer designers better understanding of the circuit and allow exploring trade-offs during design. In this paper, two methods were presented to derive a set of design equations that describe the gain, sensitivity, offset, and systematic mismatches observed in typical comparator circuits. A three-stage, fast complementary metal-oxide semiconductor (CMOS) comparator structure is analysed and simulated in order to validate the proposed methods. A 0.13 μm CMOS technology is used for simulations with 1.5 V supply voltage. Bisection theorem was used for gain and sensitivity analysis. Simulation results show that high gain improvement can be possible by using the design equations. The input offset voltage, due to mismatch in the width of the metal oxide semiconductor field-effect transistors (MOSFET) (W) and mismatches in the threshold voltages of the N and P type MOSFETs(VTHN, VTHP), is analysed using a proposed balanced method. The same comparator structure is used for the input offset voltage analysis. Simulations show that an offset improvement can be achieved following the design equations found through the proposed method. [ABSTRACT FROM PUBLISHER]

A low-power constant charging-current relaxation oscillator that outputs a frequency-tunable sawtooth signal and a pulse signal is proposed and implemented in 0.5-μm CMOS process. At the architecture level, two comparators with 10 times difference in power consumption are proposed to break up the tight tradeoff between power consumption and oscillation performance. Most of the time, only the low-power auxiliary comparator works to save power. The high-power main comparator is controlled by the auxiliary comparator output and only works when a ramping voltage is close to a reference voltage. At the circuit level, an adaptive current control technique that makes current adversely proportional to input voltage differences is used to further reduce the power consumed in the low-power comparator. The measured clock phase noise at the offset frequency of 100 kHz is −115.07 dBc/Hz at the output frequency of 1 MHz. The measured output frequency variations are 124 ppm/°C over temperatures from −55 °C to 125 °C, and −0.13%–0.18% over power supplies from 3 V to 5.5 V. The frequency range from 200 kHz to 1350 kHz is achieved. The power consumption at the 1 MHz output frequency is 9.5 μW, which is comparable with state-of-the-art designs in the literature. [ABSTRACT FROM AUTHOR]

In this paper, a fully differential charge-pump comparator-based pipelined analog-to-digital converter (ADC) is presented. The fully differential capacitive gain doubler is used in the first stage as multiplying digital-to-analog converter (MDAC). Since the first stage cannot drive large capacitive loads, therefore a topology with high input impedance is chosen for the second, third and following stages. This topology does not require the common-mode feedback (CMFB) circuit. Besides, it employs the cascode current source to minimize the overshoot at the output of stages. The proposed ADC has been designed and simulated in a 90 nm CMOS technology. Simulation results show that the ADC achieves SNDR of 55.6 dB and SFDR of 64.5 dB at sampling frequency of 100 MS/s and consumes 2.8 mW from a 1 V power supply. [ABSTRACT FROM AUTHOR]

This paper discusses challenges of implementing embedded dosimeters into larger CMOS systems-on-chip (SoCs) in deep-scaled CMOS technologies (with gate lengths smaller than 90 nm) where the high level of intrinsic radiation hardness and limited availability of floating gate structures prohibit realizing a highly sensitive radfet-type dosimeter. We therefore propose a novel Logic-I/O Threshold Comparison Dosimeter, which offers compatibility with advanced CMOS technology nodes and co-integration with other circuitry. The proposed dosimeter estimates dose level by directly comparing threshold voltages between I/O and logic devices. Furthermore, through carefully sizing the logic and I/O devices and designing the vital comparator circuitry, we can also achieve required temperature independence for deep-space applications. A prototype is then fabricated in 65-nm CMOS, and measured up to 75 Mrad(Si) of total ionized dose at a Cobalt 60 ($\gamma $) facility. [ABSTRACT FROM AUTHOR]

This paper presents an evolutionary approach to design CMOS Two-Stage Comparator (TSC) and CMOS Folded Cascode Operational Trans-conductance Amplifier (FCOTA) using simplex particle swarm optimization (Simplex-PSO) method. The simplex particle swarm optimization (Simplex-PSO) is a swarm intelligent based evolutionary computation method. Simplex-PSO is the hybridization of Nelder–Mead Simplex method (NMSM) and Particle Swarm Optimization (PSO) without the velocity term. The Simplex-PSO has fast optimizing capability and high computational precision for high-dimensionality functions. This work has focused on the optimization of the area, power and has improved all other performance parameters of the CMOS TSC and CMOS FCOTA with minimum computational time. The proposed Simplex-PSO based circuit optimization technique is relieved from the inherent drawbacks of premature convergence and stagnation, unlike Differential Evolution (DE), Harmony Search (HS). The simulation results prove that Simplex-PSO yields the optimized result with improved functionality. Simulation results obtained for CMOS TSC and CMOS FCOTA prove the effectiveness of the proposed Simplex-PSO method based approach over the reported DE, HS, and PSO in terms of convergence speed, design specifications and design objectives. The optimally designed TSC and FCOTA circuits, individually, occupy the least MOS areas and dissipate the least powers. The simulation plots and results are shown to have the improved performance parameters compared with those of other reported literature. Validation of the design is carried out by Cadence version 5 (IC 5.10.41) of TSMC 0.35 μm technology. [ABSTRACT FROM AUTHOR]

This work describes an ultra low voltage, low power and self biased comparator with wide input common-mode range. The proposed comparator consists of a preamplifier followed by a regenerative back-to-back inverter latch, where two push pull NMOS and PMOS pairs are exploited to bias the preamplifier and adjust its output common mode voltage. This leads to a wide input common mode voltage range (from 0 V to 390 mV). Furthermore, the operation of proposed structure is relatively insensitive to process and temperature variations due to the push pull transistors, and low power consumption is achieved through sub-threshold region operation. The comparator circuit is designed using 65-nm CMOS technology with minimum supply voltage of 0.4 V. Simulation results show an average power consumption ranging from 141 nW to 188 nW for different input common mode voltage levels, where a simple power gating technique is employed to further reduce the power consumption. The Monte Carlo simulation shows an average offset of 450 μV with standard deviation of 3.3 mV. In addition, the comparator shows a kickback noise range of 0.3-2.4 mV (with input common mode range from 0 V to 390 mV) and input referred noise of 0.9 mV. The proposed comparator operates up to clock frequency of 1 MHz in most process corners and temperature range of 0-100°C which is suitable for most of the biomedical sensing applications. [ABSTRACT FROM AUTHOR]

We report on a novel, two-stage 8-bit trimming solution dedicated for multichannel systems with reduced trim DAC area occupancy. The presented design was used for comparator offset correction in a 128-channel particle tracking, self-triggering readout system and manufactured in 180 nm CMOS process. The 8-bit trim DAC has a range of ±165 mV, current consumption of 3.2 µA and occupies an area of 37 µm×17 µm in each channel, which corresponds to a 6-bit conventional current steering DAC with similar linearity. [ABSTRACT FROM AUTHOR]

This paper describes the design of a high speed min/max architecture based on a new current comparator. The main advantage of the proposed circuit which employs a novel preamplifier-latch comparator is the higher operating frequency feature in comparison with previous works. Because the comparator can work in voltage mode, the min/max structure can be redesigned either in voltage or current mode. The designed comparator is refreshed without any external clock. Therefore, it does not degrade the speed performance of proposed min/max structure. These features along with low power consumption qualify the proposed architecture to be widely used in high speed fuzzy logic controllers (FLCs). Post-layout simulation results confirm 3.4 GS/s comparison rate with 9-bit resolution for a 0.9 V peak-to-peak input signal range for the comparator and 800 MHz operating frequency for min/max circuit. The power consumption of whole structure is 912 μW from a 1.8 V power supply using TSMC 0.18-μm CMOS technology. [ABSTRACT FROM AUTHOR]

A preamplifier for comparators of precision low-power consumption analog-digital converters is presented. In order to lower the average consumption current of amplifier cascades, the capacitors, which fulfill the function of current sources during charging at the comparison stage, are used in them as the dynamic load. A correction circuit of the zero bias error for amplifiers of this type is developed. Modeling of the device using CMOS elements with a design rule of 0.35 μm from library XA035 of factory XFAB showed that the average current consumption at an operating frequency of 1 MHz is about 7 μA. [ABSTRACT FROM AUTHOR]

This paper presents a boost converter with variable output voltage and a new maximum power point tracking (MPPT) scheme for biomedical applications. The variable output voltage feature facilitates its usage in a wide range of applications. This is achieved by means of a new low-power self-reference comparator. A new modified MPPT scheme is proposed which improves the efficiency by 10%. Also, to further increase the efficiency, a level converter circuit is used to lower the V dd of the digital section. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. Using this approach, a thermoelectric energy harvesting circuit has been designed in a 180 nm CMOS technology. According to HSPICE Simulation results, the circuit operates from input voltages as low as 40 mV and generates output voltages ranging from 1 to 3 V. A maximum power of 138 μW can be obtained from the output of the boost converter which means that the maximum end-to-end efficiency is 52%. [ABSTRACT FROM AUTHOR]

In this paper, the optimization and analysis of threshold configurable regenerative comparators (TC) for use in ultra-low power consumption ADCs is introduced (TC-ADC). Using a 90 nm CMOS technology, the obtained comparator achieves a 77% improvement in terms of power consumption ( 3 μ W ) when compared with previously published TC comparators, while maintains the same full scale specification (±160 mv). The proposed design exhibits a delay time of 1.31 ns — a 20% of improvement — which allows achieving for a 6-bit TC-ADC up to 25 MS/s for a sampling period of 40 ns. Furthermore, offset, gain and non-linearity errors of a 6-bit TC-ADC is also analyzed for both perfectly matched devices and under the presence of manufacturing dependent device mismatch scenarios. The higher energy efficiency of the optimized comparator increases the linearity of the TC-ADC by a 50% in offset, gain, DNL and INL. Although, a mismatch analysis of 30 MonteCarlo simulations and 3 σ device parameter variations exhibits a higher non-linearity for the threshold comparators, the gain, offset and DNL errors for the optimized one are diminished in a 37%, 12% and 17%, respectively. [ABSTRACT FROM AUTHOR]

The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2. [ABSTRACT FROM AUTHOR]

A 13-bit analog-to-digital converter (ADC) is designed in 0.35 ¡im CMOS technology that reduces the power consumption through sharing the resources between pipeline stages. Using a dummy sample-and-hold (S/H) and recirculating concept the requirements for the first stage are relaxed and the design restrictions are resolved. This ADC does not use a dedicated S/H and reaches a speed of 50 MS/s. The design is tested with TSMC mixed-signal 0.35 /¿m technology and post layout simulations shows over 75 dB Signal-to-Noise and Distortion-Ratio (SNDR) and over 85 dB Spurious Free Dynamic Range (SFDR) at the Nyquist frequency. The designed chip occupies an area of 1.3 mm-0.7 mm and consumes 164 mW power at Nyquist from a 3.3 V supply. [ABSTRACT FROM AUTHOR]

In this article, we proposed a high-speed, high fan-in dynamic CMOS comparator with low transistor count. Our approach is to construct the dynamic comparator based on the prior superiority of dynamic CMOS comparator and to further enhance its operating speed. Constructing the comparator with dynamic CMOS architecture, we can save 63.2% transistor count as compared with the conventional static CMOS design. The main contribution to accelerate the speed of dynamic comparator is to solve the problem of ‘weak 0’ existing in the PMOS of pull-down network. Instead, as an alternate to PMOS in the pull-down network, we use NMOS combined with an additional inverter in the front of the NMOS input gate. In this way, we can perform the same function as PMOS, but transmitting with both ‘good 1’ and ’good 0’. As a result, the proposed dynamic comparator can operate with lower propagation delay in the pull-down network. Finally, the proposed 64-bit dynamic comparator circuit can operate correctly under a clock frequency of 450 MHz with 0.18 µm technology while the prior circuit can only operate under 250 MHz at the same time. [ABSTRACT FROM PUBLISHER]

The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator's circuit. This article presents the results of a CMOS comparator with hysteresis design -- the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. [ABSTRACT FROM AUTHOR]