Search

The implementation of true random number generators is of vital importance to preserve the reliability of cryptographic systems. The lack of entropy can compromise their integrity, affecting the security of the entire chain of applications. Ensuring the effectiveness of a random number generator can be understood as reducing the risk of information loss due to possible attacks by third parties. This paper presents a novel approach for a true random number generator based on a Ring Oscillator-Physical Unclonable Function. Since the principle of operation of physical unclonable functions is based on the physical properties of each device, they can be used for security applications such as device identification, counterfeit prevention, and increase the robustness of cryptographic functions. In addition, increasing the versatility of the design to use them as a source of entropy, they can also fulfill tasks such as generation of initialization vectors or nonces and keys for symmetric cryptography. The system incorporates multiple operating configurations, which allows a complete analysis of its performance to adapt it to different application scenarios. The randomness and correct operation of the proposed design have been evaluated online, by incorporating it into a hybrid HW/SW embedded system able to run the official test suite published by the National Institute of Standards and Technology without any need for post-processing. The architecture has been designed for Xilinx Zynq-700 family devices and implemented on the Pynq-Z2 development board., SPIRS Project with Grant Agreement No. 952622 under the EU H2020 research and innovation program, ARES Project PID2020-116664RB-100 funded by MCIN/AEI/10.13039/501100011033 and the EU NextGenerationEU/PRTR., M.C.M.R. holds a Postdoc fellowship from the Andalusia Government with support from PO FSE of EU.

Hard learning problems are important building blocks for the design of various cryptographic functionalities such as authentication protocols and post-quantum public key encryption. The standard implementations of such schemes add some controlled errors to simple (e.g., inner product) computations involving a public challenge and a secret key. Hard physical learning problems formalize the potential gains that could be obtained by leveraging inexact computing to directly generate erroneous samples. While they have good potential for improving the performances and physical security of more conventional samplers when implemented in specialized integrated circuits, it remains unknown whether physical defaults that inevitably occur in their instantiation can lead to security losses, nor whether their implementation can be viable on standard platforms such as FPGAs. We contribute to these questions in the context of the Learning Parity with Physical Noise (LPPN) problem by: (1) exhibiting new (output) data dependencies of the error probabilities that LPPN samples may suffer from; (2) formally showing that LPPN instances with such dependencies are as hard as the standard LPN problem; (3) analyzing an FPGA prototype of LPPN processor that satisfies basic security and performance requirements.

This paper focuses on the FPGA implementation of a slew-rate reduction (SR) shaping function for envelope tracking (ET) power amplifiers (PAs). The SR envelope has been proved effective to trade-off power efficiency and linearity in ET PA systems where the envelope tracking modulator (ETM) is bandwidth limited. However, the implementation issues need to be addressed when targeting high clock rates to cope with current 5G new radio wide-band signals. This paper shows the FPGA implementation of the SR envelope generation. We explore the use of high-level synthesis (HLS) for the SR envelope generation to evaluate the performance and resource usage of the hardware architecture. The HLS design is also compared with a hand-written hardware description language (HDL) version. An in-depth analysis shows strengths and limitations of the HLS design to meet the timing constraints when considering a throughput of 614.4 MSa/s. © 2022 IEEE.

Computing paradigm based on von Neuman architectures cannot keep up with the ever-increasing data growth (also called "data deluge gap"). This has resulted in both the academic and industrial community investigating novel computing paradigms and design approaches at all levels from materials, devices, circuits, architectures, and all the way to system-level implementations and applications. For example, to improve performance, the community has been investigating solutions through massively parallel and distributed systems that are a rupture from von Neumann architectures. As artificial neural networks (ANN) and deep neural networks (DNN) that are trained over hundreds of graphic processing units (GPU)-accelerated servers where each GPU can have thousands of cores. The limitations of data processing through the memory wall in von Neumann architectures have been overcome with bringing computing to the data inspired by biological brainlike computing. An alternative computing approach based on ANNs uses oscillators to compute or oscillatory neural networks (ONNs). Such an approach differs from classical CMOS and classical von Neumann where building blocks are analog and perform computations efficiently. Moreover, data is encoded on the oscillator signals phase, which is a departure from the classical voltage level-based data encoding (such as amplitude voltage to represent a logical bit '1' or '0'). ONNs can perform computations efficiently and can be used to build a more extensive neuromorphic system. How should a designer choose to optimally implement ONNs in analog is the focus of many ongoing research efforts. But here, we address a more fundamental problem, can we efficiently perform AI applications (such as image/pattern recognition) with ONNs? In other words, what are the advantages and limitations of the ONN computing paradigm for practical AI applications? Here, we present a digital ONN implementation to show a proof-of-concept of the ONN approach of "computing-in-phase" for pattern recognition applications. To the best of our knowledge, this is the first attempt to implement an FPGA-based fully-digital ONN. We report ONN accuracy, training, inference, memory capacity, operating frequency, hardware resources based on simulations and implementations of 5x3 and 10x6 ONNs. We present the digital ONN implementation on FPGA for pattern recognition applications such as performing digits recognition from a camera stream. We discuss practical challenges and future directions in implementing digital ONN.

Agile hardware design strategies have shown a fast adoption in academia and industry by bringing ideas from the software development side. However, adopted design methodologies exhibit traditional verification scenarios based on handmade testbenches. Here we describe a verification methodology for RISC-V-based processors with human-independent testbenches creation, employing high-effort verification methods throughout all processor design cycle. We demonstrated the methodology by performing verification tests in a single-issue in-order (SIIO) 32-bit RISC-V ISA based processor described in Chisel. In contrast to standard verification methods, the proposed methodology can detect bugs hard to isolate even after final FPGA implementations in-field. The generated test programs show higher coverage metrics, and χ 30 fewer instructions compared to official RISC-V torture unit tests.

The spread of epidemics and diseases is known to exhibit chaotic dynamics; a fact confirmed by many developed mathematical models. However, to the best of our knowledge, no attempt to realize any of these chaotic models in analog or digital electronic form has been reported in the literature. In this work, we report on the efficient FPGA implementations of three different virus spreading models and one disease progress model. In particular, the Ebola, Influenza, and COVID-19 virus spreading models in addition to a Cancer disease progress model are first numerically analyzed for parameter sensitivity via bifurcation diagrams. Subsequently and despite the large number of parameters and large number of multiplication (or division) operations, these models are efficiently implemented on FPGA platforms using fixed-point architectures. Detailed FPGA design process, hardware architecture and timing analysis are provided for three of the studied models (Ebola, Influenza, and Cancer) on an Altera Cyclone IV EP4CE115F29C7 FPGA chip. All models are also implemented on a high performance Xilinx Artix-7 XC7A100TCSG324 FPGA for comparison of the needed hardware resources. Experimental results showing real-time control of the chaotic dynamics are presented.

In this work, the implementations of the LBlock, Piccolo, Twine, and Klein lightweight ciphers in FPGA technology are studied in terms of area, frequency, throughput, and throughput/area. To accomplish this, loop unrolling and pipelining were employed in two phases. In the first phase, different loop unrolling factors were used to implement the round function of each cipher, while in the second phase, 2-stage pipelining with loop unrolling per stage was applied. The produced designs were implemented in Xilinx (Kintex-7) FPGA technology. Based on the implementation results, a detailed study on the above-mentioned design metrics was performed and important outcomes were derived.

Lightweight cryptography is a vital and fast growing field in today&rsquo, s world where billions of constrained devices interact with each other. In this paper, two novel compact architectures of the Enocoro-128v2 stream cipher are presented. The Enocoro-128v2 is part of the ISO/IEC 29192-3 standard. The first architecture has an 8-bit datapath while the second one has a 4-bit datapath. The proposed architectures were implemented on the BASYS3 board (Artix 7 XC7A35T) using the VERILOG hardware description language. The hardware implementation of the proposed 8-bit architecture runs at a 189 MHz clock and reaches a throughput equal to 302 Mbps, while at the same time, it utilizes only 254 Look-up Tables (LUTs) and 330 Flip-flops (FFs). Each round of computations requires 5 clock cycles. The 4-bit implementation has an operating frequency of 204 MHz and reaches a throughput equal to 181 Mbps, with each round requiring 9 clock cycles. The 4-bit implementation utilizes 249 LUTs and 343 FFs. To our knowledge, this is the first time that such implementations of the Enocoro-128v2 are presented. Both implementations utilize a very low number of resources (only 78 FPGA slices are required for the 8-bit architecture and only 83 for the 4-bit one) and the results demonstrate that they are sustainable for area constrained embedded devices.

Support vector machine (SVM) is a robust machine learning model with high classification accuracy. SVM is widely utilized for online classification in various real-time embedded applications. However, implementing SVM classification algorithm for an embedded system is challenging due to intensive and complicated computations required. Several works attempted to optimize performance and cost by implementing SVM in hardware, especially on field-programmable gate array (FPGA) as it is a promising platform for meeting challenging embedded systems constraints. This article presents a comprehensive survey of hardware architectures used for implementing SVM on FPGA over the period 2010–2019. We performed a critical analysis and comparison of existing works with in-depth discussions around limitations, challenges, and research gaps. We concluded that the primary research gap is overcoming the challenging trade-off between meeting critical embedded systems constraints and achieving efficient and precise classification. Finally, some future research directions are proposed, aiming to address such research gaps.

The recently uncovered problem of multi-point progressive blocking (MPB) has significantly increased the complexity of schedulability analysis of priority-preemptive wormhole networks-on-chip. While state-of-the-art analysis is currently deemed safe, there is still significant inherent pessimism when it comes to considering backpressure issues caused by downstream indirect interference. In this paper, we attempt to simplify the problem by considering a novel flow control protocol that can avoid backpressure issues, enabling simpler schedulability analysis approaches to be used. Rather than construct the analysis to fit the protocol, we modify the protocol so that effective analysis applies. We describe the changes to a baseline wormhole router in order to implement the proposed protocol, and comment on the impact on hardware overheads. We also examine the number of routers that actually require these changes. Comparative analysis of FPGA implementations show that the hardware overheads of the proposed NoC router are comparable or lower than those of the baseline, while analytical comparison shows that the proposed approach can guarantee schedulability in up to 77% more cases.

This paper proposes audio signal processing implementation on two different multimedia FPGA board (Zybo and Zed Board). The audio signal coming from audio codec is adaptive filtering using LMS algorithm and it is implemented on FPGA. The comparative study has been done in terms of hardware resource utilization, static and dynamic power dissipation and speed of the system. The interesting result we have found is that hardware resource utilization and delay are less in ZYBO as compare to Zed multimedia board and also, we have found that the static power dissipation is less and dynamic power dissipation is more in ZYBO multimedia board.

Binarized neural networks (BNNs) have shown exciting potential for utilising neural networks in embedded implementations where area, energy and latency constraints are paramount. With BNNs, multiply-accumulate (MAC) operations can be simplified to XnorPopcount operations, leading to massive reductions in both memory and computation resources. Furthermore, multiple efficient implementations of BNNs have been reported on field-programmable gate array (FPGA) implementations. This paper proposes a smaller, faster, more energy-efficient approximate replacement for the XnorPopcountoperation, called XNorMaj, inspired by state-of-the-art FPGAlook-up table schemes which benefit FPGA implementations. Weshow that XNorMaj is up to 2x more resource-efficient than the XnorPopcount operation. While the XNorMaj operation has a minor detrimental impact on accuracy, the resource savings enable us to use larger networks to recover the loss., 4 pages

Through parallelization, field programmable gate array (FPGA) can achieve unprecedented speeds in large-scale parallel Monte Carlo (LPMC) simulations. FPGA presents both new constraints and new opportunities for the implementations of random number generators (RNGs), which are key elements of any Monte Carlo (MC) simulation system. Using empirical and application based tests, this study evaluates all of the four RNGs used in previous FPGA based MC studies and newly proposed FPGA implementations for two well-known high-quality RNGs that are suitable for LPMC studies on FPGA. One of the newly proposed FPGA implementations: a parallel version of additive lagged Fibonacci generator (Parallel ALFG) is found to be the best among the evaluated RNGs in fulfilling the needs of LPMC simulations on FPGA.

The increasing complexity of new digital signal processing (DSP) applications is forcing the use of floating point (FP) numbers in their hardware implementations. In this brief, we investigate the advantages of using half-unit biased (HUB) formats to implement these FP applications on field-programmable gate arrays (FPGAs). These new FP formats allow for the effective elimination of the rounding logic on FP arithmetic units. First, we experimentally show that HUB and standard formats provide equivalent signal-to-noise ratio on DSP application implementations. We then present a detailed study of the improvement achieved when implementing FP adders and multipliers on FPGAs by using HUB numbers. In most of the cases studied, the HUB approach reduces resource use and increases the speed of these FP units while always providing statistically equivalent accuracy as that of conventional formats. However, for some specific sizes, HUB multipliers require far more resources than the corresponding conventional approach.

International audience; We present various FPGA implementations of protections against SCAs for RLWE-based PKE. We implemented the main solutions from the state of the art with improved variants. We also propose a new protection based on a redundant representation of the ring elements to randomize computations. We compare the implementation results of all these solutions.

Convolutional neural networks have been widely used in many deep learning applications. Convolutional neural networks have a large number of convolution operations, which poses a huge challenge to real-time performance. In recent years, FPGA implementations of convolutional accelerators have received much attention due to their high performance and energy efficiency. In this paper, we implement an accelerator for convolution operations through the systolic array architecture on Xilinx ZedBoard device. The experimental results show that ours designed accelerators achieving performance density of up to 0.032 Gop/s/DSP.

As redes reguladoras de genes são modelos baseados em grafos muito utilizadas para estudar o comportamento de células, processos de diferenciação celular ou tratamento e evolução de doenças. Uma rede pode ser implementada por um grafo com equações booleanas. Os algoritmos usados nas simulações das redes avaliam estas equações várias vezes ao longo da execução. Este artigo propõe um estudo das implementações em CPU, GPU e FPGA da operação básica que é o cálculo do próximo estado. Exploramos as técnicas de vetorização e paralelização com AVX e OpenMP para os processadores e uma nova arquitetura dinâmica é proposta para simplificar o uso das soluções com FPGA. Além do modelo booleano, mostramos como as redes podem ser transformadas em equações com somas de peso e limiares. Finalmente, 16 redes biológicas usados na literatura foram avaliadas, onde as implementações em CPU com OMP apresentaram uma aceleração de 3x em comparação com a CPU, as implementações em GPU foram em média 57,3x mais rápidas que a CPU e finalmente as implementações em FPGA foram em média 86,7x mais rápidas que a CPU. ∗

Central Pattern Generator (CPG) has an important role in controlling the locomotion part of the animals. Bio-inspired Central Pattern Generators can find application areas in robotic and control applications. FPGA implementations of Central Pattern Generators have already been studied in literature. Not all institutes have FPGA systems. In this paper, it is shown that like STM32F103 devices which use the Cortex-M3, a Hindmarsh-Rose (HR) neuron model can be made using a cheap microcontroller board. The experimental results verify that the system is successfully able to reproduce the original Central Pattern Generator patterns.

This research investigates the use of FPGAs to create a fully autonomous system to detect hotspots on high voltage insulators by processing infrared videos. Initial algorithm development was conducted with MATLAB. The algorithm was automated by the addition of automatic temperature tracking and arc detection giving a sixtyfold speed increase (85 Hz). Explored two FPGA implementations of the algorithm: Verilog only; an embedded processor running compiled C++ code. Applications include post processing and live stream processing where alerts can be fed to maintenance teams of transmission system operators.

In this work, we propose a high-level synthesis approach for hardware sandboxes in system-on-chip. Using interface formalism to capture interactions between non-trusted IPs and trusted parts of a system on chip, along with the properties specification language to specify non-authorized actions of non-trusted IPs, sandboxes are generated and made ready for inclusion as IP in a system-on-chip design. The concepts of composition, compatibility, and refinement are used to capture illegal actions and optimize resources across the boundary of single IPs. We have designed a tool that automatically generates the sandbox and facilitates their integration into system-on-chip. Our approach was validated with benchmarks from trust-hub.com and FPGA implementations. All our results showed 100% Trojan detection and mitigation, with only a minimal increase in resource overhead and no performance decrease.

This paper presents a new technique that dynamically estimates and updates the coefficients of a digital predistorter (DPD) for power amplifier (PA) linearization. The proposed technique is dynamic in the sense of estimating, at every iteration of the coefficient’s update, only the minimum necessary parameters according to a criterion based on the residual estimation error. At the first step, the original basis functions defining the DPD in the forward path are orthonormalized for DPD adaptation in the feedback path by means of a precalculated principal component analysis (PCA) transformation. The robustness and reliability of the precalculated PCA transformation (i.e., PCA transformation matrix obtained off line and only once) is tested and verified. Then, at the second step, a properly modified partial least squares (PLS) method, named dynamic partial least squares (DPLS), is applied to obtain the minimum and most relevant transformed components required for updating the coefficients of the DPD linearizer. The combination of the PCA transformation with the DPLS extraction of components is equivalent to a canonical correlation analysis (CCA) updating solution, which is optimum in the sense of generating components with maximum correlation (instead of maximum covariance as in the case of the DPLS extraction alone). The proposed dynamic extraction technique is evaluated and compared in terms of computational cost and performance with the commonly used QR decomposition approach for solving the least squares (LS) problem. Experimental results show that the proposed method (i.e., combining PCA with DPLS) drastically reduces the amount of DPD coefficients to be estimated while maintaining the same linearization performance.

With the increasing need for highly secure systems, Physical Unclonable Functions (PUFs) have emerged within the last decade. Ordering based Ring Oscillator (RO) PUFs are one of the best performing structures with their robustness and suitability to FPGA implementations. Even though the performance of the ordering based RO-PUFs have been analyzed in detail, effects of aging have not been studied before. In this work, we present the results of an accelerated aging test applied to analyze the effects of aging on ROs. Then, the effects of aging on ordering based RO-PUFs are examined. Finally, a compensation method to protect the 100% robustness claim of the PUF structure is proposed and its influence on the circuit performance is presented. HighlightsResults of an accelerated aging test applied on ROs are presented.The effects of aging on ordering based RO-PUFs are examined.A compensation method to protect the 100% robustness of the PUF structure is proposed.

[EN] A method for the implementation of the atan2 operator based on the coordinate rotation digital computer algorithm is described. In the proposal, the computation of the z-path takes advantage of the look-up table-based FPGA resources to reduce by between 17 and 25%, without performance deterioration, the overall area of the unrolled architecture., This work was funded by the Spanish Ministerio de Economia y Competitividad and FEDER under the grant TEC2015-70858-C2-2-R.

In this paper, three eSTREAM Portfolio 2 ciphers: Grain v1, Mickey 2.0 and Trivium, and two Grain-like stream ciphers: Lizard and Plantlet are implemented in three versions aimed at different hardware application purposes. The hardware platform adopts Xilinx’s Spartan7 serial, and the simulations, syntheses and implementations are conducted in Vivado using the Verilog hardware design language. These implementations are compared with each other and those presented in existing literature in terms of performance metrics including: throughput, area consumption and throughput-area ratio. The basic version of Trivium achieves the highest frequency reaching a maximum of 416 Mbps and the serial version consumes the smallest area of 13 slices. In the parallel version, the maximum throughput-area ratio is 165.5 Mbps/Slice achieved by Trivium. At the same time, the basic version of the Mickey 2.0 algorithm achieved the second highest frequency of 384 Mbps, and the serial version of the Grain v1 algorithm achieved the second smallest area with 26 slices.

Authenticated ciphers potentially provide resource savings and security improvements over the joint use of secret-key ciphers and message authentication codes. The CAESAR competition aims to choose the most suitable authenticated ciphers for several categories of applications, including a lightweight use case, for which the primary criteria are performance in resource-constrained devices, and ease of protection against side channel attacks (SCA). In March 2018, two of the candidates from this category, ACORN and Ascon, were selected as CAESAR contest finalists. In this research, we compare two SCA-resistant FPGA implementations of ACORN and Ascon, where one set of implementations has area consumption nearly equivalent to the defacto standard AES-GCM, and the other set has throughput (TP) close to that of AES-GCM. The results show that protected implementations of ACORN and Ascon, with area consumption less than but close to AES-GCM, have 23.3 and 2.5 times, respectively, the TP of AES-GCM. Likewise, implementations of ACORN and Ascon with TP greater than but close to AES-GCM, consume 18% and 74% of the area, respectively, of AES-GCM.

Proyecto CESAR TEC2013-45523-R Proyecto INTERVALO TEC2016-80549-R Proyecto LACRE CSIC 201550E039 La información intercambiada diariamente en las redes de comunicación crece de forma exponencial y gran parte de ella está constituida por información sensible, por lo que debe estar protegida para prevenir su uso fraudulento. Una correcta aplicación de la Criptografía evita el acceso no deseado, de forma que esta información pueda ser protegida. Estudiar la fragilidad/robustez de la seguridad es, pues, una tarea esencial para garantizar esa protección. Por otra parte, el ámbito de uso es tan amplio (desde la seguridad gubernamental, como por ejemplo secretos militares del Pentágono, hasta la doméstica) que resulta necesario concretarlo, en este caso, para entornos de pocos recursos (lightweight cryptography) y centrados en implementaciones con dispositivos electrónicos programables de alta densidad. El Trabajo Fin de Máster que se presenta tiene como principal objetivo analizar el funcionamiento de implementaciones FPGA de cifradores de flujo en presencia de ataques laterales activos, en concreto de ataques que intenten introducir fallos en el funcionamiento del Trivium aumentando la frecuencia del reloj. A través del análisis de las técnicas de ataques laterales activos, se presenta un sistema cuyo objetivo es analizar la vulnerabilidad y comportamiento del cifrador Trivium, implementado sobre FPGA, frente a dichos ataques laterales activos. The large amount of information exchanged grows exponentially and a lot of it is constituted by sensitive data, it must be protected to prevent its fraudulent use. A correct application of Cryptography prevents malicious access, so that information can be protected. Studying the vulnerability/robustness of the security is, then, an essential aim in order to guarantee that protection. On the other hand, the field of use is so wide that it is necessary, in this case, for low resource environments and focused on device implementations with high density programmable electronic. The aim of this TFG is to analyze the behaviour of stream ciphers implemented on FPGAs against active attacks, that is inyecting faults in the clock line during the operation of Trivium stream ciphers. Through the analysis of active attack techniques, an attack system is presented with the aim of analyzing the Trivium cipher vulnerability and behavior, implemented on FPGA, against active fault attacks. Universidad de Sevilla. Grado en Ingeniería Electrónica Industrial

We describe two innovative low latency centroiding algorithms implemented in an FPGA, exploiting the parallel processing features of these devices, and showing low values in latency and real estate, which eases their integration with complete adaptive optics systems.

This paper explores error-correcting codes for fuzzy extractor applications with Physical Unclonable Functions. We investigate BCH codes and compare them to convolutional codes using criteria of remaining entropy, probability of decoder failure, and hardware requirements. Parallel BCH coding is analyzed with a comprehensive search performed to find the smallest BCH code which satisfies the criteria in a parallel design to produce 128, 192, and 256-bit keys. A convolutional code is selected for comparison against the BCH codes found in this analysis. Application of the selected codes to a fuzzy extractor design is analyzed. Hardware requirements for FPGA implementations of each code is compared, with a BCH decoder design implemented for Artix-7 and Spartan-6 FPGA families. We find that a (127, 22, 47) parallel BCH code or (2, 1, 12) convolutional code is capable of performing as well as a single large BCH code, while requiring fewer FPGA resources when block RAMs can be leveraged. The convolutional code additionally requires the least amount of PUF ID bits.

Deep neural networks (DNNs) have gained popularity for their state-of-the-art accuracy and relative ease of use. DNNs rely on a growing variety of matrix multiply operations (i.e., dense to sparse, FP32 to N-bit). We propose an OpenCL-based matrix multiply design template, which enables automated design exploration to generate optimized FPGA matrix accelerators for DNN applications. Given the desired matrix operations (e.g., sparsity, data types), our template rapidly produces performance and area estimates for a variety of design variants and/or FPGA platforms. Upon identifying compelling design points and target platforms, FPGA implementations can then be generated automatically using the Intel® OpenCL™ FPGA SDK. We show the effectiveness of the template with a comparison to hand-tuned RTL, a design space exploration, and a DNN case study.

Hardware applications in an industrial context often have tight area, latency and throughput requirements or a specific combination thereof. This paper presents a method to improve area and throughput figures for folded circuits generated during a model-based hardware design process. The method targets FPGA implementations and is based on the automatic combination of isomorphic subgraphs and the detailed consideration of pipelined primitive operations for folding core scheduling. In the course of a design space exploration, the user is provided with fine-grain control over the area/throughput trade-off.

The growing trend toward heterogeneous platforms is crucial to meet time and power consumption constraints for high-performance computing applications. The OpenCL parallel programming language and framework enable programming CPU, GPU and recently FPGAs using the same source code. This eases software developers to implement applications on various devices supported by heterogeneous HPC platforms. This work presents two very different FPGA implementations of a database join operation, one using a direct O(n2) algorithm, and the other using a bitonic sort network to speed up the join operation. Comparison of performance and energy consumption for both FPGA and GPUs is provided which suggests a 40% performance/watt improvement by using an FPGA instead of a GPU.