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Though GaN HEMTs have primarily been used for power amplification, they are also well suited for receiver applications. In the front-end of receivers, non-linearities, in particular third-order intermodulation products lead to in-band signal distortion. The intermodulation distortion is primarily dominated by transconductance and its derivatives. In this paper, we report on N-polar GaN MIS-HEMTs able to simultaneously achieve high gain (12.7 dB) and excellent linearity performance (OIP3/PDC of 15 dB) for low-power receiver application at 30 GHz. With a two-tone load-pull input-bias sweep, we demonstrate that the linearity of high performance HEMTs is sensitive to bias, and we present our measurement methodology to accommodate this. [ABSTRACT FROM AUTHOR]

Two $K_{u}$ - to V-band distributed amplifiers (DAs) based on nMOS and nMOS/pMOS gain stages and a distributed transceiver front end (DTFE) are presented for ultra-wideband power and low-noise amplification in a 45-nm RF CMOS silicon-on-insulator (SOI) technology. Supply scaling of gain stages through high-pass filter sections achieves high efficiency while maintaining a broadband 50- $\Omega $ match. The nMOS DA has a gain of 13 dB over a 3-dB bandwidth of 10–82 GHz and a minimum noise figure (NF) of 5.3 dB. The measured peak output power is 17.2 dBm with a peak power-added efficiency (PAE) of 17.4% at 50 GHz. The hybrid DA allows higher operating voltage and distortion cancelation of scaled pMOS devices to an achieve output power of 17.5 dBm with PAE of 20.2% and low third-order intermodulation and amplitude–phase nonlinearities. The DTFE utilizes time-domain duplexing to drive a shared antenna port for transmit (TX) and receive (RX) modes. It achieves TX gain of 11.7 dB from 12–76 GHz with peak output power of 17 dBm and PAE of 14.2%. RX gain is 9 dB from 11–77 GHz with a minimum NF of 6.2 dB. The 5-GHz wideband 16-QAM is demonstrated in the amplifier circuits for data rates exceeding 20 Gb/s. [ABSTRACT FROM AUTHOR]

A 70-GHz two-element bidirectional frontend is demonstrated with linear coupled oscillators in a 90-nm silicon–germanium BiCMOS process. The transmitter has a measured peak output power of 7.2 dBm and a peak conversion gain of 14.5 dB while consuming 47 mA from a 1.8-V supply. The receiver has a peak conversion gain of 9.9 dB and a minimum noise figure of 8.6 dB with a nominal current consumption of 18 mA from a 1.5-V supply. The frontend is integrated with a two-element linear coupled oscillator array and achieves a maximum phase scanning of ±80°. [ABSTRACT FROM PUBLISHER]

A channel-selecting low-noise amplifier (CS-LNA) with blocker filtering is presented for a SAW-less diversity path receiver (RX) in frequency-division duplexing cellular systems. A hybrid N-path bandpass filter/band-reject filter (BPF/BRF) feedback network is applied to the LNA to create close-in reject bands around the passband to suppress transmit leakage and improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). Control of the frequency and depth of the reject bands is demonstrated with analysis and simulation. A gm2{\mathchar"702D}gm3 cancellation linearization is applied to improve the in-band (IB) linearity. Adaptive LO swing and silicon-on-insulator (SOI) thick-oxide devices are demonstrated to improve the power-handling capability. The proposed CS-LNA is implemented in 32-nm CMOS SOI and operates from 0.4 to 6 GHz with the maximum rejection larger than 60 dB and power-handling capability up to 17 dBm. The prototype demonstrates an OOB IIP3 of 36 dBm and IB IIP3 of 10 dBm at 1 GHz. To the authors’ knowledge, this is the highest blocker rejection, power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. [ABSTRACT FROM PUBLISHER]

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5\,\times\,4.5 \mm^2) containing eight-unit PAs was developed and its output was fed to a 2\,\times\,2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2\,\times\,8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the \2\,\times\,\2 and the 2\,\times\,8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%. [ABSTRACT FROM PUBLISHER]

The analysis and implementation of a dual-band direct-conversion millimeter-wave transmitter is presented. The proposed dual-band modulator uses high-impedance loads at two frequencies for the local oscillator driving amplifiers and power amplifier (PA) pre-amplifiers. To correct the amplitude and phase imbalance of the in-phase and quadrature channels at Q- and W-bands, the paper suggests a digitally controlled quadrature error correction stage to finely calibrate these errors and lower the error vector magnitude (EVM) without increasing the baseband digital-to-analog converter resolution. The transmitter is fabricated in 0.12- μm silicon-germanium BiCMOS process and occupies an area of 5.5 mm2. At 45-GHz carrier frequency, error correction improves the sideband suppression ratio (SSR) by 10 dB at 2.4-MHz IF frequency. The EVM is lowered from 3.21% to 2.38% for a 64-QAM constellation at a 2.4-Ms/s symbol rate. At 94-GHz carrier frequency, the SSR is improved from 24 to 41 dBc at 2.4-MHz IF frequency, and the EVM is lowered by more than 1% for a 16-QAM constellation at 3-Ms/s symbol rate. A dual-band PA breakout measurement indicates the peak power-added efficiency of 15% with 14-dBm maximum saturated power (Psat) at 43 GHz and 9-dBm Psat at 82 GHz is achieved. [ABSTRACT FROM AUTHOR]

A power amplifier (PA) topology is presented that incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The PA is fabricated in a 120-nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power-added efficiency of 20% at 38 GHz. This is the highest reported output power from a single PA at Q-band in silicon. [ABSTRACT FROM PUBLISHER]

The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for Q- and W-bands and a push–pull amplifier is investigated at Q-band. The Q-band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The W-band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process. [ABSTRACT FROM PUBLISHER]

A broadband amplifier is realized with cascaded stagger-tuned stages that are equalized for high bandwidth and low gain ripple. The staggered frequency response is demonstrated to improve the transimpedance limit of active circuits. The staggered response is demonstrated with a Darlington feedback amplifier and a constructive wave amplifier, which achieves low group delay. The broadband amplifier is implemented in a 0.12-\mu\ m SiGe BiCMOS process and achieves a 3-dB bandwidth of 102 GHz. The gain is 10 dB with 1.5-dB gain-ripple and group-delay variation under \pm6 ps over the entire 3-dB bandwidth. The chip occupies an area of 0.29 \ mm^2 including the pads and consumes 73 mW from a 2-V supply. [ABSTRACT FROM PUBLISHER]

A dual-channel CMOS distributed amplifier (DA) is proposed for a highly linear receiver front-end. Proper choice for the number of stages and cutoff frequency of the distributed circuit realizes isolation between amplifier channels. Analysis of the distributed circuit describes the role of reverse gain in minimum noise figure (NF) and intermodulation distortion. The chip is fabricated in a \0.13-\mu\ m CMOS process, occupies an area of \ 0.60 mm^2, and consumes 18 mW from a 1.2-V supply. Measurements of the DA show an NF of 5.7 dB, an output P1~{dB} of 4.9 dBm, and a forward gain of 9.6 dB at 24 GHz. [ABSTRACT FROM AUTHOR]

A W-band, cascaded constructive wave amplifier realizes high gain and bandwidth in a 0.12 \mum SiGe BiCMOS process. The amplifier achieves 37.5 dB gain at 90 GHz with a 3 dB bandwidth of 14.6 GHz. Consequently, this amplifier demonstrates a gain-bandwidth product as high as 1,095 GHz. At nominal bias condition, input and output return losses are better than 11 dB over the entire 3 dB bandwidth and the output-referred P1 dB is -5.5 dBm. The amplifier consumes 65 mW from a 1.8 V at a nominal bias condition and 130 mW from a 2 V at a high-gain bias condition. The chip occupies an area of 0.39 mm^2 including the pads. [ABSTRACT FROM PUBLISHER]

This letter presents a loss-compensated, varactor- loaded transmission line for a W-band analog phase shifter in a 0.12 \mum SiGe BiCMOS process. To compensate for distributed varactor losses, a variable gain amplifier is distributed along the transmission line. A phase shift of 65^\circ over eight stages (8^\circ per stage) is introduced from 70–110 GHz. A maximum gain of 16.7 dB or (2.1 dB per stage) at 94 GHz is measured. The output-referred P1 dB is typically -7 dBm with a total current consumption of 20 mA from a 1.8 V supply voltage. The chip occupies an area of 0.2 mm^2 including the pads. This is the first phase shifter at 94 GHz in silicon/silicon-germanium reported to date. [ABSTRACT FROM PUBLISHER]