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High peak and average efficiency is an important feature of power amplifiers (PAs) for 5G millimeter-wave communication. This article reviews the challenges of conventional outphasing approaches in CMOS technologies and demonstrates a low-loss outphasing combiner for low loadline impedance. Undesirable characteristics of CMOS devices for outphasing are compensated with neutralization, unilaterization, and stabilization networks for the outphasing PA (OPA). The OPA is realized in 45-nm CMOS silicon on insulator (SOI) and demonstrates 40% 6-dB backoff drain efficiency (DE) while providing 17-dBm peak output power with a peak 50.5% DE. For 64-QAM, a 31.3% average DE and 10.1-dBm average output power are measured. The OPA demonstrates less than 1.5% error vector magnitude (EVM) with 64-QAM waveform using a phase-based lookup table (LUT). With 16-QAM, the bit rate reaches 20 Gb/s with 12% EVM. To the best of our knowledge, this is the highest bit rate for a high-efficiency PA. The adjacent channel leakage ratio (ACLR) is under −25 dBc. [ABSTRACT FROM AUTHOR]

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ($\lambda /4$) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

This paper presents an explicit analysis of the bandwidth and port imbalance of a subquarter-wavelength transmission-line (t-line) transformer and verifies this with the design of a two-stage D-band power amplifier (PA). Series power combining techniques incorporate both stacked heterojunction bipolar transistors (HBTs) and power combining using an 8-way sub-quarter-wavelength t-line transformer above 100 GHz. The extremely compact power combining methodology leads to a small die area of 0.62 mm2 and a record 254-mW/mm2 output power per unit die area. The PA has been fabricated in a 90-nm silicon germanium BiCMOS technology and produces more than 21-dBm output power over the frequency range of 114–130 GHz with a peak output power of $160~{\mathrm{mW}}\approx 22~{\mathrm{ dBm}}$ at 120 GHz and a 3-dB small-signal bandwidth of 35 GHz. This output power is 32% higher than the highest prior art, while the chip area is 77% smaller. [ABSTRACT FROM AUTHOR]

A 70-GHz two-element bidirectional frontend is demonstrated with linear coupled oscillators in a 90-nm silicon–germanium BiCMOS process. The transmitter has a measured peak output power of 7.2 dBm and a peak conversion gain of 14.5 dB while consuming 47 mA from a 1.8-V supply. The receiver has a peak conversion gain of 9.9 dB and a minimum noise figure of 8.6 dB with a nominal current consumption of 18 mA from a 1.5-V supply. The frontend is integrated with a two-element linear coupled oscillator array and achieves a maximum phase scanning of ±80°. [ABSTRACT FROM PUBLISHER]

Quadrature oscillators (QOs) based on parallel or series coupling mechanisms produce ambiguous phase relationships between the coupled oscillators. Deterministic mode selection is presented and analyzed for a series-coupled LC quadrature oscillator (LC-QO) and leveraged to increase the tuning range of the QO. Series-coupled LC-QOs have been implemented in a 90-nm CMOS technology. Measured results show a frequency tuning range of 94% for a center frequency of 1.3 GHz, 60% for the oscillator operating at 3.7 GHz, and 52% for the oscillator operating at 4.4 GHz. [ABSTRACT FROM PUBLISHER]

A tunable N-path filter with more than one decade tuning range is demonstrated to address transmit (TX) leakage in a surface-acoustic-wave-less diversity path receiver for frequency-division duplexing cellular systems. The proposed filter simultaneously creates a reject band and passband anywhere from 0.2 to 3.6 GHz to suppress TX leakage while minimizing insertion loss of the receive signal and is implemented in 45-nm CMOS silicon-on-insulator. Measurements show the 3-dB bandwidth of the passband is greater than 80 MHz with an independently tunable reject band, providing the ultimate rejection is from 33 to 41 dB while the passband insertion loss is between 2.6 dB and 4.3 dB over the tuning range. The proposed filter offers 29-dBm out-of-band (OOB) third-order input-intercept power (IIP3) and 22-dBm in-band (IB) IIP3 with a 10-dBm blocker 1-dB compression point (B1dB). To the authors’ knowledge, this is the highest B1dB, IB IIP3, and OOB IIP3 for a CMOS tunable filter. [ABSTRACT FROM PUBLISHER]

The analysis and implementation of a dual-band direct-conversion millimeter-wave transmitter is presented. The proposed dual-band modulator uses high-impedance loads at two frequencies for the local oscillator driving amplifiers and power amplifier (PA) pre-amplifiers. To correct the amplitude and phase imbalance of the in-phase and quadrature channels at Q- and W-bands, the paper suggests a digitally controlled quadrature error correction stage to finely calibrate these errors and lower the error vector magnitude (EVM) without increasing the baseband digital-to-analog converter resolution. The transmitter is fabricated in 0.12- μm silicon-germanium BiCMOS process and occupies an area of 5.5 mm2. At 45-GHz carrier frequency, error correction improves the sideband suppression ratio (SSR) by 10 dB at 2.4-MHz IF frequency. The EVM is lowered from 3.21% to 2.38% for a 64-QAM constellation at a 2.4-Ms/s symbol rate. At 94-GHz carrier frequency, the SSR is improved from 24 to 41 dBc at 2.4-MHz IF frequency, and the EVM is lowered by more than 1% for a 16-QAM constellation at 3-Ms/s symbol rate. A dual-band PA breakout measurement indicates the peak power-added efficiency of 15% with 14-dBm maximum saturated power (Psat) at 43 GHz and 9-dBm Psat at 82 GHz is achieved. [ABSTRACT FROM AUTHOR]

A 10 bit current-steering, digital-to-analog converter (DAC) is presented that delivers 6 VPP into a 100 Ω differential load. To realize high-voltage swings using fineline CMOS, a stacked-FET buffer is used to isolate the current source from the output load. The stacked-FET buffer degrades the linearity of the DAC. This work presents a Volterra analysis to capture the frequency-dependent behavior of the stacked-FET circuit that can be cascaded to quantify the linearity of an N-device stack. The power DAC is implemented in 45 nm CMOS SOI and the measured differential nonlinearity (DNL) and integral nonlinearity (INL) is better than 0.4 and 0.6 LSB, respectively. The DAC consumes 476 mW and achieves a peak SFDR of 73 dB and a minimum IM3 of -69 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a high-resolution (>8 bit), high-speed (>100 MS/s) DAC. [ABSTRACT FROM PUBLISHER]

Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage Q-band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 \mum\,\times\,500 \mum including pads. [ABSTRACT FROM AUTHOR]

A power amplifier (PA) topology is presented that incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The PA is fabricated in a 120-nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power-added efficiency of 20% at 38 GHz. This is the highest reported output power from a single PA at Q-band in silicon. [ABSTRACT FROM PUBLISHER]

A fully-integrated Q-band (40–45 GHz) bidirectional transceiver is demonstrated in a 0.12-\mu\m SiGe BiCMOS technology. The RF front-end design eliminates the need for transmit/receive switches by demonstrating a novel PA/LNA circuit. The transceiver has a transmit conversion gain of 35 dB with a 3-\dB bandwidth of 4 GHz. The OP1dB is 8.5 dBm and Psat is 9.5 dBm. The transceiver has a receive conversion gain of 34 dB with a 3-\dB bandwidth of 3 GHz. The noise figure is 4.7 dB and OP1dB is -5 dBm at 43 GHz. The chip consumes 119.4 mW when transmitting and 54 mW when receiving, and overall chip size is 1.6 mm\times 0.8 mm including pads. To the author's knowledge, this work represents the first switchless millimeter-wave bidirectional transceiver in a CMOS or BiCMOS process. [ABSTRACT FROM PUBLISHER]

A broadband amplifier is realized with cascaded stagger-tuned stages that are equalized for high bandwidth and low gain ripple. The staggered frequency response is demonstrated to improve the transimpedance limit of active circuits. The staggered response is demonstrated with a Darlington feedback amplifier and a constructive wave amplifier, which achieves low group delay. The broadband amplifier is implemented in a 0.12-\mu\ m SiGe BiCMOS process and achieves a 3-dB bandwidth of 102 GHz. The gain is 10 dB with 1.5-dB gain-ripple and group-delay variation under \pm6 ps over the entire 3-dB bandwidth. The chip occupies an area of 0.29 \ mm^2 including the pads and consumes 73 mW from a 2-V supply. [ABSTRACT FROM PUBLISHER]