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The stitch wire configuration is widely adopted for large-area IGBT chips. However, an inhomogeneous wire current density introduces uneven self-heating and nonuniform chip heating, which exacerbates the chip thermal stress. In this article, a multicellular electro-thermal model considering the stitch-bonding wires is derived to optimize the wire layout parameters. Furthermore, the current density alleviation of wire bonds is investigated to be the most sensitive and effective method to comprehensively mitigate the thermal nonequilibrium and local overheating. Consequently, an improved multitier layout is proposed to further achieve thermal stress suppression without any additional components and advanced materials. Finally, a triple-tier-bonded IGBT module with optimal design parameters is fabricated to validate the thermal mitigation performance. The prototype experimental results demonstrate that the modeling error is less than 3.0%. The multitier layout decreases the current density by 57.6%, hence, the maximum and average chip temperature are reduced by 21.8% and 12.4%, respectively. [ABSTRACT FROM AUTHOR]

Three-level converters typically feature low switching loss and small filter size. In order to realize a high-power-density design for three-level converters, SiC MOSFETs may be selected instead of using Si insulated-gate bipolar transistors. However, all-SiC-MOSFET-based converters suffer from extremely high total cost. In this paper, a SiC MOSFET and Si device hybrid active neutral-point-clamped (ANPC) converter is proposed. It consists of four Si active switches and only two SiC MOSFETs. Thus, it has lower total cost compared to the all-SiC-MOSFET-based ANPC converter. Furthermore, a dedicated modulation scheme is proposed to completely move all the switching events from Si devices to SiC MOSFETs by using redundant switching states. As a result, the switching losses are significantly reduced and extremely high efficiency is achieved. The proposed converter has fully utilized the low-switching-loss advantage of SiC MOSFETs and the low-cost advantage of Si devices, which shows significant superiority in high-end grid-connected inverter and rectifier applications. [ABSTRACT FROM AUTHOR]

This paper proposes the adoption of the inherent emitter stray inductance $L_{{\rm{eE}}}$ in high-power insulated gate bipolar transistor modules as a new dynamic thermo-sensitive electrical parameter (d-TSEP). Furthermore, a family of 14 derived dynamic TSEP candidates has been extracted and classified in voltage-based, time-based and charge-based TSEPs. Accordingly, the perspectives and the implementation challenges of the proposed method are discussed and summarized. Finally, high-power test platforms are designed and adopted to experimentally verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

Insulated-gate bipolar transistor (IGBT) short-circuit failure modes have been under research for many years, successfully paving the way for device short-circuit ruggedness improvement. The aim of this paper is to classify and discuss recent contributions about IGBT short-circuit failure modes, in order to establish the current state of the art and trends in this area. First, the concept of 3-D safe operating area is proposed as the IGBT's operational boundary to divide the device short-circuit failure modes into short-circuit $V_{{\rm{DC}}}/ V_{{\rm{rated}}}\hbox{--} I_{{\rm{SC}}}$ SOA limiting and short-circuit endurance time limiting groups. Then, the discussion is centered on currently reported IGBT short-circuit failure modes in terms of their relationships with the device 3-D short-circuit safe operating area (3D-SCSOA) characteristics. In addition, further investigation on the interaction of 3D-SCSOA characteristics is implemented to motivate advanced contributions in future dependence research of device short-circuit failure modes on temperature. Consequently, a comprehensive and thoughtful review of where the development of short-circuit failure mode research works of IGBT stands and is heading is provided. [ABSTRACT FROM AUTHOR]

This paper presents a high-power IGBT testing platform for uneven temperature conditions and its design criteria. Considering the influence of layout parasitic parameters on the measurement results, commutation rules and independent junction temperature control, a universal high-power switching characterization platform is built and operated. Importantly, it is capable of 3.6 kA current level test requirement, which can cover the largest current level for the state-of-the-art IGBT modules. To improve the test accuracy of double pulse test method, a compensation algorithm is proposed to eliminate the circuit power loss under high current test conditions. Moreover, in order to simulate the uneven junction temperature effects occurring in real life, the junction temperatures of inspected IGBT and freewheeling diode are controlled independently. Quantitative analyses of the switching characteristics for junction temperatures up to 125 °C are performed. [ABSTRACT FROM AUTHOR]

In this paper, a dynamic thermo-sensitive electrical parameter (DTSEP) for extracting the junction temperature of the trench gate/field-stop insulated gate bipolar transistor (IGBT) modules by using the maximum collector current falling rate is proposed. First, a theoretical model of the transient collector current during turn-off process is developed in terms of the behavior characteristics of the inside storage carriers. Then, the inherent linear relationship between the maximum collector current falling rate dIC/dt and junction temperature Tj is demonstrated and investigated. Fortunately, benefitting from the presence of the intrinsic parasitic inductance LeE between the Kelvin and power emitters of IGBT modules, the maximum dIC/dt can be easily measured to validate the theoretical analysis. Consequently, the maximum dIC/dt during turn-off process is a promising DTSEP for IGBT module junction temperature estimation. Moreover, the physical device parameters that affect the temperature sensitivity of the maximum dIC/dt are also discussed with the derived transient collector current falling model. [ABSTRACT FROM AUTHOR]

This paper proposes a method to extract the junction temperature of high-voltage and high-power p-i-n diodes. It is investigated that the swept-out charge during reverse recovery current fall time is affected by junction temperature variation, which makes the swept-out charge a possible thermo-sensitive electrical parameter (TSEP). Thanks to the specific package of high-power IGBT modules with p-i-n diodes, the swept-out charge of a p-i-n diode can be measured by the induced voltage $v_{{eE}}$ on the parasitic inductor $L_{{eE}}$ between Kelvin and power emitter terminals. In typical inductive half-bridge circuit, the comprehensive analysis of commutation between the upper p-i-n diode and lower enabled IGBT discloses the monotonic relationship among the reverse recovery charge, reverse current fall time, and junction temperature. A double pulse chopper circuit is used to validate the theoretical analysis. The experimental results show that the dependence between diode junction temperature and charge during the reverse recovery current fall time is approximately linear. A three-dimensional lookup table is calibrated and can be used to estimate the p-i-n diode junction operating temperature. Finally, an experimental comparison of four TSEPs for p-i-n diode is presented to verify the feasibility of the implementation of proposed TSEP. [ABSTRACT FROM AUTHOR]

Thermo-sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature extraction and prediction of power semiconductor devices. In this paper, the turn-off delay time is explored as an indicator of a TSEP to extract the junction temperature from high-power insulated gate bipolar transistor (IGBT) modules. The parasitic inductor LeE between the Kelvin and power emitter terminals of an IGBT module is utilized to extract the turn-off delay time. Furthermore, the monotonic dependence between the junction temperature and turn-off delay time is investigated. The beginning and end point of the turn-off delay time can be determined by monitoring the induced voltage veE across the inductor LeE. A dynamic switching characteristic test platform for high-power IGBT modules is used to experimentally verify the theoretical analysis. The experimental results show that the dependency between IGBT junction temperature and turn-off delay time is near linear. It is established that the turn-off delay time is a viable TSEP with good linearity, fixed sensitivity, and offers nondestruction on-line IGBT junction temperature extraction. [ABSTRACT FROM AUTHOR]

In this paper, a non-contact degradation evaluation method for insulated gate bipolar transistor (IGBT) modules is proposed based on eddy current pulsed thermography approach. In non-contact heat excitation procedures, a high-power induction heater is introduced to generate heat excitation in IGBT modules. The thermographs of the whole temperature mapping are recorded non-invasively by an IR camera. As a result, the joint degradation of IGBT modules can be evaluated by the transient thermal response curves derived from the recorded thermographs. Firstly, the non-destructive evaluation principle of the eddy current pulsed thermography (ECPT) system for an IGBT module with a heat sink is introduced. A 3D simulation module is built with physical parameters in ANSYS simulations, and then thermal propagation behavior considering the degradation impact is investigated. An experimental ECPT system is set up to verify the effectiveness of the proposed method. The experimental results show that the delay time to peak temperature can be extracted and treated as an effective indicative feature of joint degradation. [ABSTRACT FROM AUTHOR]

In this paper, the impact of a double-sided press-pack insulated-gate-bipolar-transistor (PP IGBT) cooling structure on its thermal impedance distribution is studied and explored. A matrix thermal impedance network model is built by considering the multi-chip thermal coupling effect for the collector side of the PP IGBT. Moreover, a verification has been made by comparing the proposed matrix thermal network model and the conventional lumped RC network model provided by the manufacturer. It is concluded that the collector side has lower thermal resistance and dissipates about 88% of the heat generated by the IGBT chips inside the module. Then, a modular-multilevel-converter high-voltage-direct-current (MMC-HVDC)-based type test setup composed of the press-pack IGBT stacks is established and the junction temperature is calculated with the proposed thermal model and verified by temperature measurements. [ABSTRACT FROM AUTHOR]

This paper presents a survey of existing gate driving approaches for improving reliability of Insulated Gate Bipolar Transistors (IGBTs). An extensive and various lists of techniques are introduced and discussed, including fast detection, identification and protection against IGBT failures, also considering cost-effective solutions. Gate-driver circuit solutions to improve short-circuit robustness, overload, voltage and current overshoots withstanding capability are first introduced to cope with abnormal conditions severely affecting lifetime expectation. Later, some advanced, state-of-the-art control techniques are discussed to minimize the real-mission-profile stresses in terms of voltage and current stresses to the device, together with, not least, temperature variations. Future challenges and perspectives are finally discussed at the end of the paper. [ABSTRACT FROM AUTHOR]