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In this article, we first measured through glass via (TGV) noise coupling and the effectiveness of shielding structures in a glass interposer. To analyze the noise coupling between signal TGVs, an open-ended structure is adopted. Glass interposer test vehicles were fabricated to verify the noise coupling between signal TGVs. With these test vehicles, noise transfer functions between signal TGVs were measured. Based on these measurement results and the equivalent circuit model, the noise coupling between signal TGVs was analyzed. To suppress this TGV noise coupling, shielding structures for the TGV noise coupling were proposed and verified. The proposed shielding structures include the variation of signal TGV pitches and the number of grounded shield TGVs, ground pads, and guard rings, respectively. The effectiveness of the proposed shielding structures was verified up to 20 GHz in frequency-domain measurements. Using the proposed shielding structures, the noise transfer function decreased by 9.4 dB at 5 GHz. Also, the effectiveness of the proposed guard ring structure was verified by a time-domain coupling noise simulation with clock signals at frequencies of 1 GHz. The proposed guard ring successfully suppressed the clock noise coupling between signal TGVs by 60.5% and 69.2% when a signal TGV pitchis 300 and 900 $\mu {\text{m}}$ , respectively.

In this article, we propose a double-sided electromagnetic bandgap (DS-EBG) structure for glass interposers (GIs) with low substrate loss to suppress power/ground noise. For the first time, we validated wideband power/ground noise suppression in the GI using the proposed DS-EBG structure based on dispersion analysis and experimental verification. We experimentally verified that the proposed DS-EBG structure achieved the power/ground noise suppression (below −40 dB) between 2.5 and 8.9 GHz in the GI. Derived stopband edges, $f_{L}$ and $f_{U}$ based on the dispersion analysis, and 3-D electromagnetic (EM) simulation showed a good correlation with measurements. The effectiveness of the proposed DS-EBG structure on the power/ground noise suppression is verified by analyzing noise propagation in the power distribution network and coupling to the GI channel. Using the 3-D EM simulation, we verified that the proposed DS-EBG structure suppressed the power/ground noise coupling and improved the eye diagram of the GI channel. Finally, we propose a design methodology to broaden the isolation bandgap or miniaturize the dimensions based on the dispersion analysis.

In this paper, we first propose and demonstrate a novel on-interposer active power distribution network (PDN) scheme to efficiently suppress simultaneous switching noise (SSN) in a 2.5-D/3-D integrated circuit (IC). The on-interposer active PDN can change the PDN impedance by controlling on-interposer decoupling capacitors. The SSN in a 2.5-D/3-D IC is suppressed by optimal control of the on-interposer active PDN scheme. The active interposer is a silicon interposer including active circuits in its silicon substrate to enhance the electrical performance of the 2.5-D/3-D IC. A test interposer of the proposed on-interposer active PDN is fabricated with a 0.18- $\mu \text{m}$ CMOS process and assembled on a printed circuit board for measurement and analysis. The active circuits of the proposed scheme and hierarchical PDN are modeled with a distributed RLGC -lumped model for fast simulation. The modeling of the proposed scheme is experimentally verified in the frequency and time domains. We successfully demonstrate that an optimum on-interposer decoupling capacitance for the minimized SSN peak-to-peak voltage was obtained by using the proposed scheme. The proposed scheme efficiently suppressed the SSN in 2.5-D/3-D IC by preventing the SSN generation at antiresonance of the hierarchical PDN. In addition, the proposed scheme is compared with a conventional passive PDN scheme, and the maximum ratio of SSN suppression against the conventional scheme was 17.2%.

In this paper, we design and measure 28 GHz band pass filter (BPF) based on glass interposer for 5G applications. We design the parallel coupled resonator BPF based on the glass interposer. To control the even- and odd mode characteristic impedance, we adopt the multi-layer ground. Also, to reduce the channel loss, the wide coupled channels for 28 GHz BPF are designed. Designed 28 GHz glass BPF was verified by simulation using the 3D-EM simulator. Also, Designed 28 GHz glass BPF was fabricated to verify the electrical performance through measurement. Simulated and measured insertion loss of the designed 28 GHz glass BPF is −2.4 dB and −3.4 dB at 28 GHz, respectively.

Insatiable increase of power consumption of high performance computing, various types of workloads, and lowering supply voltage require a stable and rapidly responding power supply. Integrated voltage regulators (IVR) are considered and studied as a promising solution for the fine grain power supply. In this paper, we introduce an IVR on active interposer for high performance 2.5D/3D ICs and analyze the proposed IVR by comparison with off-chip and on-chip voltage regulators (VRs). The efficiency, transient response and power noise suppression effects of each VR are evaluated. By optimal design of 2-stage VR, the IVR scheme shows higher efficiency. As closer distance from VR to load, improved transient response and power noise suppression can be achieved. In addition, due to the integration of voltage regulator circuit on active interposer, the effective footprint of module with the proposed IVR is the smallest.

In this paper, we propose glass interposer electromagnetic bandgap (EBG) structure to efficiently suppress power/ground noise coupling. We designed, fabricated, measured, and analyzed a glass interposer EBG structure for the first time. Glass interposer EBG structure test vehicles were fabricated using a thin-glass substrate, low-loss polymer layers, and periodic metal patches with through glass vias (TGVs) in glass interposer power distribution network. Using the dispersion characteristics, we thoroughly analyzed and derived f L and f U of the glass interposer EBG structure. We experimentally verified that the proposed glass interposer EBG structure achieved power/ground noise suppression (below –40 dB) between f L of 5.8 GHz and f U of 9.6 GHz. Derived f L and f U based on dispersion analysis, full three-dimensional electromagnetic (3-D-EM) simulation and measurement achieved good correlation. In the glass interposer EBG structure, tapered structure of the TGV and thickness of the low-loss polymer used for metal-layers lamination affected the noise suppression bandgap significantly. The effectiveness of the proposed glass interposer EBG structure on suppression of the power/ground noise propagation and coupling to high-speed TGV channel was verified with 3-D-EM simulation. As a result, the proposed glass interposer EBG structure successfully and efficiently suppressed the power/ground noise propagation and improved eye-diagram of the high-speed TGV channel.

In this paper, we measured and analyzed glass interposer power distribution network (PDN) resonance effects on a high-speed through glass via (TGV) channel for the first time. To verify the glass interposer PDN resonance effects on the TGV channel, glass interposer test vehicles were fabricated. With these test vehicles, glass interposer PDN impedance, channel loss, far-end crosstalk, and eye diagram are measured. Based on these measurements, glass interposer PDN resonance effects on the signal integrity of the high-speed TGV channel are analyzed. Due to low loss of the glass substrate, sharp high PDN impedance peaks are generated at the resonance frequencies. High PDN impedance peaks at the PDN resonance frequencies, which affect return current of the TGV channel, increase channel loss, crosstalks, and PDN noise coupling in the frequency domain and degrade eye diagram in the time domain. To suppress these glass interposer PDN resonance effects, a ground shielded-TGV scheme is proposed. The proposed ground shielded-TGV scheme includes two ground TGVs $200\;{{\mu \text{m}}}$ away from the signal TGV considering the design rules and includes package ground underneath the glass interposer. Effectiveness of the suggested grounding scheme on the resonance effects suppression is verified with three-dimensional electromagnetic simulation. The proposed shielded-TGV design successfully suppressed the glass interposer PDN resonance effects that results in the suppression of insertion loss, shielding of the crosstalk, and improvement of the eye diagram of the high-speed TGV channel.

In this paper, we propose an interposer-level integrated voltage regulator (IIVR) scheme to suppress the power noise in next-generation high bandwidth memory (HBM) input and output (I/O) interface. The proposed IIVR is a CMOS switching voltage regulator consisting of active circuits and inductors fabricated on an active interposer and a package substrate respectively. To verify the proposed IIVR, it is analyzed by time and frequency domain simulations. The proposed IIVR can suppress internal simultaneous switching noise and isolate external broadband power noise. We have verified that the proposed IIVR successfully enables the 4 Gbps signal transfer of the next generation HBM.

In this paper, we emphasize superiority of glass interposers and address challenges with proper solutions. Electrical performance of the glass interposer channels is superior to other interposers such as silicon and organic. However, glass interposers are vulnerable to noises generated in power distribution network (PDN). We propose decoupling solutions for glass interposers to solve the PDN noise issues.

In this paper, we design and analyze receiver channels of a glass interposer for a 5G small cell front end module (FEM). In RF systems, a 50 ohm impedance matching is important for RF channels to guarantee the target RF sensitivity of the RF system. Receiver channels of glass interposers for the 5G small cell FEM are designed, analyzed and characterized up to 40 GHz considering the impedance matching. Using the designed receiver channels, the glass interposer based the 5G small cell FEM is designed and analyzed up to 40 GHz.

In this paper, we design and analyze the receiver channel of a glass interposer for a dual band Wi-Fi front end module (FEM). In RF systems, a RF sensitivity is the most important specification for a system performance and reliability. To guarantee a target RF sensitivity of the RF system, it is important to maintain a 50 Ohm impedance matching for RF channels. The 50 Ohm impedance matching of various transmission line structures is completely conducted for each layer of the glass interposer in a low band (2.4GHz – 2.5GHz) and high band (4.9GHz – 5.85GHz) respectively. Channel types for each layer are determined considering design rules and constraints. Moreover, we locate ground TGVs near signal TGVs as close as possible to suppress a ground-ground cavity resonance effect in the low band and high band. In order to test a suppression of the ground-ground cavity resonance, simulations that compare pitches between a ground TGV and signal TGV are conducted. Design considerations of receiver channels were analyzed and characterized by simulation results of channel insertion losses.

Simultaneous switching noise (SSN) occurs when clock synchronized core circuits switch simultaneously. Furthermore, a huge amount of the SSN generated by simultaneous switching current (SSC) with high power distribution network (PDN) impedance at anti-resonance can cause electromagnetic interference (EMI) problems and logic failure. In multi-core processors, the spectrum of SSC is varied by power management techniques such as dynamic voltage and frequency scaling (DVFS). However, conventional PDN cannot respond to these various SSC spectrum due to its passive characteristics. In this paper, an externally controllable on-interposer decoupling capacitance scheme, namely on-interposer active PDN, is proposed to efficiently suppress the SSN in 2.5D IC. The proposed scheme designed on the active silicon interposer can shift the frequency of the PDN anti-resonance peak with on-interposer decoupling capacitors controlled by external switching operation based on monitored SSN voltage. To verify the proposed scheme, it is modeled and analyzed in the frequency and time domain simulations. We have demonstrated that an efficient SSN suppression is achieved by obtaining the optimum on-interposer decoupling capacitance and the maximum ratio of the SSN suppression was 31.3%.

In this paper, eye-diagrams of High-Bandwidth Memory (HBM) interposer channel with crosstalk reduction schemes on 2.5D / 3D IC are estimated and analyzed. As data rate increases and metal-to-metal space decreases to achieve higher system bandwidth, crosstalk effects degrade the signal integrity. Therefore, estimation and reduction of the crosstalk effects are essential on HBM interposer channel. In order to estimate crosstalk effects in short time with high accuracy, PDA-based estimation method is proposed. In addition to the proposed method, wide space and guard trace with ground vias structures are suggested and compared based on the estimated eye-diagrams. With the estimated eye-diagrams, voltage fluctuation on DC levels due to the crosstalk effects can be analyzed. Worst and statistical eye-diagrams of interposer channels including crosstalk effects are estimated. Since the proposed method needs only output and crosstalk response of the channel, the proposed method can be applied to multiple wide I/O channels.

A 3-D stacked high bandwidth memory (HBM) becomes a promising solution to satisfy the memory bandwidth for the processor. Due to its unique memory architecture that consists of tremendous number of input/output (I/O), it is inevitable to employee Silicon based interposer. Therefore, power distribution network (PDN) design and analysis of HBM interposer becomes one of the important step to guarantee the performance of an entire memory interface. Since the back end of line (BEOL) process technology of a semiconductor industry is applied for HBM interposer, the control of a metal density and the management of wafer warpage are required. Therefore, we designed and analyzed meshed and grid type of PDN for HBM interposer because of the limit of a metal density. In addition, we also designed and analyzed PDN both a single- and double-sided interposer. Because, a double-sided interposer has an advantage of a warpage management compared to a single-sided interposer. For the suppression of simultaneous switching noise (SSN), PDN impedance with a decoupling capacitor scheme must be properly analyzed. In this paper, a single- and double-sided HBM interposer is designed with the five layers and six layers respectively to analyze PDN impedance including though-Silicon-via (TSV). PDN impedance of HBM interposer is simulated and analyzed in the frequency range from 100 MHz to 20 GHz. Based on the designed HBM interposer, we shows the great potential of HBM interposer in terms of the reduction of PDN impedance to suppress SSN with a metal-insulator-metal (MIM) decoupling capacitor.

A semiconductor industry has been encountered a memory bandwidth bottleneck toward a high density and high bandwidth system. In order to overcome those limitations, a 3D stacked high bandwidth memory (HBM) based on a through silicon via (TSV) and fine pitch interposer technology is lately introduced. By adopting this structure, thousands numbers of input/output (I/O) channels with a fine pitch can be integrated on HBM interposer which enables a terabyte/s bandwidth system. On the HBM interposer, significant numbers of I/O are integrated and they tend to operate at the same time which leads to severe simultaneous switching noise (SSN). When SSN occurs, the performance of system can be heavily degraded. Total SSN is strongly related to the self-noise and transfer-noise. In this point of view, a proper PDN design to manage transfer noise which is closely related to transfer-impedance must be taken into account. The analysis of power distribution network (PDN) impedance of HBM interposer must be performed since it generally affects power supply to the chips as well as signal integrity (SI). In this paper, HBM interposer with five layers is designed to analyze PDN. For PDN impedance analysis, Z-parameters depending on the various physical dimensions are simulated and compared. PDN impedance of HBM interposer is simulated and analyzed in the interest of frequency range dominated by interposer PDN. In order to suppress SSN, we suggest a metal-insulator-metal (MIM) de-cap scheme which can be commonly available for HBM interposer to reduce PDN impedance. Based on the designed physical dimension and material properties of HBM interposer, we successfully shows the suppression of SSN.

In this paper, we compare and analyze power/ground noise coupling in silicon, organic and glass interposers. We first compare the power/ground noise coupling of each interposer by analyzing transfer impedances of power distribution networks (PDNs). Due to low loss of the organic and glass substrates, at certain frequencies, transfer impedances increase dramatically and. In order to analyze the effects of the power/ground noise propagation in the PDN and coupling to through via channel we induced clock signals to each interposer's aggressor through via channel with data rate corresponds to the PDN (1,0)/(0,1) resonance frequency to load the power/ground noises in the PDN. We monitored the coupled voltages in the PDNs and compared eye-diagrams of the victim through via channels. Due to the low loss of the glass substrate, glass interposers turned out to be most vulnerable to the power/ground noise. We suppressed PDN transfer impedance of the glass interposer using decoupling capacitors and electromagnetic band gap structure.

Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

As total system bandwidth increased, memory industry has been imposed to satisfy its requirements. At last, innovative next generation memory named high bandwidth memory (HBM) with extremely fine micro-bump pitch of its bottom die is introduced for terabytes/s bandwidth graphics module. To establish HBM based graphics module, it becomes essential to fabricate silicon interposer due to its capability to process narrow signal width and space. Silicon based HBM interposer becomes the key solution to mitigate bandwidth bottleneck of graphics module for high computing system. To design HBM interposer successfully, the signal optimization of HBM interposer channels must be preceded thoroughly. In this paper, design optimization of top metal signals of HBM interposer considering routing feasibility is proposed. In order to analyze channel performance to determine optimal line width and space, frequency domain and time domain simulation are conducted respectively. All the proposed signals in HBM interposer are analyzed by comparing eye-opening voltage and timing jitter with 3D electromagnetic (EM) simulation results. Based on this proposed optimization design, not only HBM interposer can be applied to achieve high bandwidth with a less signal distortion but also it can be designed on the basis of a limited routing area.

Spurred by the industrial demands for terabyte/s bandwidth graphics module, high bandwidth memory (HBM) has been emerged to overcome the limitations of conventional DRAMs. Additionally, due to the fine pitch and high density interconnect routing between GPU and 4 HBMs in 2.5D terabyte/s bandwidth graphics module, HBM interposer has also been to the force. However, several signal integrity issues of the HBM interposer occur due to the manufacturing process constraints. In this paper, we design the HBM interposer using 6 layers redistribution layer (RDL) and TSVs in 2.5D terabyte/s bandwidth graphics module. And then, in the designed HBM interposer, electrical performance of the HBM interposer channels using M1, M3, and M5 layer is analyzed by simulation in the frequency-and time-domain. With the simulation results, it is observed that the designed HBM interposer shows good signal integrity.

Recently, IT trends such as big data, cloud computing, internet of things (IoT), 3D visualization, network, and so on demand terabyte/s bandwidth computer performance in a graphics card. In order to meet these performance, terabyte/s bandwidth graphics module using 2.5D-IC with high bandwidth memory (HBM) technology has been emerged. Due to the difference in scale of interconnect pitch between GPU or HBM and package substrate, the HBM interposer is certainly required for terabyte/s bandwidth graphics module. In this paper, the electrical performance of the HBM interposer channel in consideration of the manufacturing capabilities is analyzed by simulation both the frequency- and time-domain. Furthermore, although the silicon substrate is most widely employed for the HBM interposer fabrication, the organic and glass substrate are also proposed to replace the high cost and high loss silicon substrate. Therefore, comparison and analysis of the electrical performance of the HBM interposer channel using silicon, organic, and glass substrate are conducted.

With the advent of 2.5D and 3D IC, micro bumps has been highlighted as the core technology for realization of 2.5D and 3D IC. However, due to the difficulties about fabrication of reliable and cost-effective micro bumps, resulting in decrease in the final chip yield. In this paper, we propose a bump-less interconnection for high-speed signaling in 2.5D and 3D IC. In the proposed interconnection, high speed signal is transmitted via coupling pads instead of micro bumps. Signal integrity of the proposed interconnection is analyzed by simulation in the frequency- and time-domain. For a more detailed analysis, the proposed interconnection and the interconnection with the micro bumps are compared. In addition, because the silicon, organic and glass interposer have been widely employed for the 2.5D and 3D IC packaging, signal integrity of the proposed interconnection on three types of the interposer is compared and analyzed.