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In this paper, we experimentally demonstrate, for the first time, gate-all-around (GAA) nanosheet transistors with a record number of stacked channels. Seven levels stacked nanosheet (NS) GAA transistors fabricated using a replacement metal gate process, inner spacer and self-aligned contacts show an excellent gate controllability with extremely high current drivability $(3\mathrm{mA}/\mu \mathrm{m}\ \mathrm{at}\ \mathrm{V}_{\mathrm{DD}}=1\mathrm{V})$ and a 3 x improvement in drain current over usual 2 levels stacked- NS GAA transistors.

International audience; This paper presents recent progress on Gate-All-Around (GAA) stacked-NanoWire (NW) / NanoSheet (NS) MOSFETs. Key technological challenges will be discussed and recent research results presented. Width-dependent carrier mobility in Si NW/NS and FinFET will be analyzed, and intrinsic performance and design considerations of GAA structures will be discussed and compared to FinFET devices with a focus on electrostatics, parasitic capacitances and different layout options. The results show that more flexibility can be achieved with stacked-NS transistors in order to manage power-performance optimization.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

We have evaluated various Cyclic Selective Epitaxial Growth/Etch (CSEGE) processes in order to grow “mushroom-free” Si and SiGe:B Raised Sources and Drains (RSDs) on each side of ultra-short gate length Extra-Thin Silicon-On-Insulator (ET-SOI) transistors. The 750 °C, 20 Torr Si CSEGE process we have developed (5 chlorinated growth steps with four HCl etch steps in-between) yielded excellent crystalline quality, typically 18 nm thick Si RSDs. Growth was conformal along the Si3N4 sidewall spacers, without any poly-Si mushrooms on top of unprotected gates. We have then evaluated on blanket 300 mm Si(001) wafers the feasibility of a 650 °C, 20 Torr SiGe:B CSEGE process (5 chlorinated growth steps with four HCl etch steps in-between, as for Si). As expected, the deposited thickness decreased as the total HCl etch time increased. This came hands in hands with unforeseen (i) decrease of the mean Ge concentration (from 30% down to 26%) and (ii) increase of the substitutional B concentration (from 2 × 1020 cm−3 up to 3 × 1020 cm−3). They were due to fluctuations of the Ge concentration and of the atomic B concentration [B] in such layers (drop of the Ge% and increase of [B] at etch step locations). Such blanket layers were a bit rougher than layers grown using a single epitaxy step, but nevertheless of excellent crystalline quality. Transposition of our CSEGE process on patterned ET-SOI wafers did not yield the expected results. HCl etch steps indeed helped in partly or totally removing the poly-SiGe:B mushrooms on top of the gates. This was however at the expense of the crystalline quality and 2D nature of the ∼45 nm thick Si0.7Ge0.3:B recessed sources and drains selectively grown on each side of the imperfectly protected poly-Si gates. The only solution we have so far identified that yields a lesser amount of mushrooms while preserving the quality of the S/D is to increase the HCl flow during growth steps.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives in terms of heterogeneous integration. We will review the opportunities brought by CoolCube™ and will present the most advanced technological demonstration of 3D CMOS over CMOS CoolCube™ integration.

In 3D sequential integration, the top transistor thermal budget must be reduced to preserve bottom MOSFET performance. In order to relax this thermal budget limitation, the thermal stability of the bottom level must be increased, especially for the silicide. In that purpose, Ni0.9Co0.1 alloy is proposed to replace the current Ni0.85Pt0.15 silicide. For the first time, this Ni0.9Co0.1 salicide has been integrated on pMOS FDSOI transistors with state of the art process leading to performance improvements compared to the standard Ni0.85Pt0.15 salicide. In this study, the cobalt incorporation into the salicide has been investigated to enhance its thermal stability.

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650^oC). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

For the first time the maximum thermal budget of in-situ doped source/drain State Of The Art (SOTA) FDSOI bottom MOSFET transistors is quantified to ensure transistors stability in Sequential 3D (CoolCube™) integration. We highlight no degradation of Ion/Ioff trade-off up to 550°C. Thanks to both metal gate work-function stability especially on short devices and silicide stability improvement, the top MOSFET temperature could be relaxed up to 500°C. Laser anneal is then considered as a promising candidate for junctions activation. Based on in-depth morphological and electrical characterizations it demonstrates very promising results for high performance Sequential 3D integration.

Using a novel process flow, we managed to cointegrate several devices on the same wafer; single gate (SG), ground plane (GP), perfectly aligned double gate (DG), misaligned DG and oversized back-gate DG. This paper reports the experimental evaluation of the gate architectures influence on the performance of silicon-on-insulator MOSFETs. DG MOSFETs, with gate lengths down to 40 nm, are experimentally compared to SG and GP MOSFETs. Short-channel effect (SCE) control, static performance and mobility are quantified for each architecture. When compared to SG and GP transistors, the DG transistor shows the best SCE control and performance as predicted by simulations. Gate coupling is demonstrated to be a sensitive and a nondestructive method to evaluate the real on-wafer alignment. Using this method, we report an experimental analysis of gate misalignment influence on DG MOSFETs' performance and SCE. It is found that misalignment primarily affects the subthreshold parameters due to an electrostatic control loss. The DG MOSFET with a slightly oversized back gate (10 nm on each side of the top gate) is a promising solution, if a 10% loss in dynamic performance can be tolerated.

Thanks to ultimate Si nMOSFETs with physical gate length down to 16 nm, the main challenges related to conventional transistors have been estimated. Short channel effect control is difficult below 40 nm due to the large TED of BF 2 halos. Nevertheless drain current higher than 800 μA/μm @ V d =1.5 V can be reached. Such performance is not a consequence of non-stationary effects since these are limited by the degradation of the low longitudinal field mobility on conventional short transistor. Ultimate transport is also analysed thanks to short and narrow devices. At low temperature, these MOSFETs are shown to operate like single electron transistors.

Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

This paper reviews how the evolution of FDSOI planar architecture towards Trigate Nanowires leads to a natural Single Electron Transistor and Field Effect Transistor convergence at room temperature. On one hand, this convergence sets up technological specifications to preserve CMOS operation. On the other hand it opens the path to room temperature hybrid circuits based on single electron transistors and MOSFETs. Further on, single electron effects can be downscaled to the ultimate single atom transistors and we demonstrate the practical performance of electron pumps for metrologic applications.

Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presnts “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

Full chemical mechanical polishing (CMP) process integration of a W/TiN damascene metal gate has been optimized and is demonstrated to be compatible with ULSI circuit fabrication. Highly uniform and reliable electrical characteristics are achieved for widely ranged MOS pattern structures (from 0.1-/spl mu/m gate transistors up to 0.6-mm/sup 2/ capacitors). CVD TiN film as a damascene gate electrode shows excellent properties for MOS performances and gate oxide integrity even on ultrathin gate oxide (2-nm SiO/sub 2/).

We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

Thanks to a well-controlled CMOS FDSOI technology we have recently been able to demonstrate breakthroughs in the combined use of field effect and Coulomb blockade phenomena. On one hand, we have demonstrated room temperaturehybrid circuits based on single electron transistors and MOSFETs. On the other hand, we have shown the practical performance of electron pumps designed with a single silicided Coulomb island and MOSFETs as tunable barriers for metrologic applications.

In this letter, we report the fabrication and characterization of self-aligned double-gate MOSFETs with gate length down to 6 nm. Based on molecular bonding, the interest of this original process relies on the fact that, for the first time, technological options such as planar process, independently biasable gates, and metallic source and drain are integrated all together to address critical issues for sub-22-nm node, such as variability, short channel effect control, and access resistance decrease. Good electrical performance of pMOS transistors is demonstrated. Short channel effects are very well controlled down to 30 nm. The independent biasing of the two gates allows tuning of the characteristics, depending on the targeted applications.

Thanks to bonding, metal-gate etching without any out-of-gate Si consumption, and self-aligned transfer of alignment marks, we have processed the first 10-nm-gate-length DG MOS transistors with metal gates. These devices exhibit excellent short-channel effects control and high-performance characteristics. Their saturation current is very sensitive to the access resistance increase caused by film thinning required to respect the scaling rules. Moreover, their electrical properties can be tuned between LSTP and HP by independently biasing the two gates.

For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for L G =20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked I D -V G 's. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at V D =±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.

3D monolithic integration, thanks to its high vertical density of interconnections, is the only available option for applications requiring connections at the transistor scale. However to achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low thermal budget top FET still have to be solved. In this work, a 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given. Significant breakthroughs have been obtained using a full wafer molecular bonding with thin interlayer dielectric and an original salicidation process stabilized up to 650°C enabling to reach high performance for the top and bottom transistor. With such technology, we demonstrate functional top and bottom transistors as well as 3D structures such as invertors and SRAMs.

We report a patterning strategy for building the first monoelectronic device complementary metal oxide semiconductor (CMOS)-compatible platform, including a single-electron transistor (SET) and multiple coupled quantum dots. Aggressive hybrid lithography (e-beam and deep UV are combined) and plasma etching are used to form adapted silicon active areas and gates, with a minimum size of 14 nm and a pitch of 80 nm after etching. These aggressive dimensions enable the study of double dots, a key structure for the more complex quantum circuits emerging now.

Although single dopant signatures have been observed at low temperature [1–2], the impact on transistor performance of a single dopant atom at room temperature is not yet well understood. Here, for the first time, we provide an in-depth understanding of single dopant influence on NMOSFETs characteristics by linking low and room temperature transport. We demonstrate that, for gate length of 30 nm and below (channel length down to 10 nm), the presence of a single dopant dramatically alters the subthreshold behaviour when the dopant is located in the middle of the channel. Moving the dopants away from the channel leads to enhanced variability above the threshold voltage V t .

International audience; For the first time, low temperature (LT) anneal at 625°C has been demonstrated for dopants activation enabling similar ION/IOFF trade-off as standard spike anneal (>;1000°C), down to 30nm gate length (LG) for both n&p FETs. Similar short channel effect control has been achieved in LT n&p FETs as its high temperature (HT) counterparts. Influence of dopant implant tilt on LT device performance is analyzed and guidelines for device performance optimization are proposed. This demonstration paves the way to 3D sequential integration with equal performance for stacked transistors and for bottom transistors.

We hereby report the fabrication, electrical characterization and TCAD simulation of planar Single and Double Gate n-and p-MOSFETs with metallic Dopant Segregated Source and Drain (DSS) on SOI, with gate lengths down to 20nm. A wide range of experimental data for various device architectures (Single Gate, Single Gate on Ultra Thin Buried Oxide, Double Gate), S/D metallizations (Pt, Ni, Er, Yb), and doping conditions at the S/D-channel interfaces are analyzed in order to evaluate the trade-off between performance and Short-Channel Effects (SCE) control of metallic S/D MOSFETs for the sub-22nm nodes. We demonstrate pFET devices with promising electrical behavior (ION=790µA/µm; I OFF =60nA/µm @ V DS =-1.2V; L g =30nm), suitable for high performance applications. Excellent SCE control is also reported down to 30nm (DIBL=50mV/V), through the use of Double Gate transistors.

We design and fabricate single-electron transistors and electron pumps within an industrial CMOS platform. Based on silicon nanowire transistors, these devices allow very simple and stable single-electron control thanks to doping modulation along the wire.

7th International Conference on Ultimate Integration on Silicon, Grenoble, FRANCE, APR 20-21, 2006; International audience; With the constant reduction of the transistor dimensions, new transport mechanisms in the conduction channels must be taken into account, as the quasi-ballistic transport. To realize how close to the ballistic limit a nanoFET operates, calculating the ratio of the mean-free-path to the critical length at the top of the source-to-channel barrier becomes an interesting investigation. After an introduction concerning the ballistic transport into the current devices, we will present the electrically characterized architectures and the methodology used to extract the backscattering coefficient (r(SAT)) for different gate lengths (10, 20 and 70 nm) and with temperatures ranging from 100 K to 290 K. We found that although the gate length is very small, the Double-Gate MOSFETs (DGMOSFETs) are not so close to the ballistic frontier (r(SAT) = 0). (c) 2007 Elsevier Ltd. All rights reserved.

Symposium on VLSI Technology 2007, Kyoto, JAPAN, 2007; International audience; For the first time, we have extracted the ballisticity rates of strained and unstrained n-Fully Depleted Silicon On Insulator devices with gate lengths down to 10nm. Thanks to a new fully experimental extraction methodology taking into account multi-subband population, we demonstrate that strain takes actively part in quasi-ballistic drain current improvement thanks to a 22% injection velocity enhancement, which will become the predominant transport parameter for the next generation of CMOS devices. In addition, we find that strained channel ballisticity rates are slightly greater than unstrained ones whatever the considered temperature and gate length. This rate improvement can be closely related to the mobility gain for short channel architectures.

For the first time, we report fully depleted SOI MOS transistors with WSix gate on HfO2. Gate work function, dielectric properties and channel mobility are presented in terms of Si/W ratio and compared to TiN gate devices. A 35% electron mobility gain was obtained with a WSix gate device as compared to a TiN gate transistor. It was found that both mobility and dielectric characteristics were drastically improved by decreasing the Si/W ratio of WSix films.

For the first time, we report ultra-thin fully depleted silicon-on-insulator MOS transistors with WSix metal gate on HfO2 gate dielectric down to 40nm gate length. Gate work function, short channel performance and carrier mobility are presented and compared to TiN gate devices. Higher mobility values are obtained with a WSix metal gate device in comparison with a TiN metal gate transistor.

We demonstrate ultra-thin SOI nMOSFETs with silicon thinned down to 8 nm and gate length as short as 10 nm. TTSD (to control access resistance) and pocket implantation (to extend scaling limits) are validated down to 10 nm. This performance, reported on different devices, evidences the possibility of UTSOI devices.

It is very important to study variability of nanodevices because the inability to produce large amounts of identical nanostructures is eventually a bottleneck for any application. In fact variability is already a major concern for CMOS circuits. In this work we report on the variability of dozens of silicon single-electron transistors (SETs). At room temperature their variability is compared with the variability of the most advanced CMOS FET i.e. the ultra thin Silicon-on-Insulator Multiple gate FET (UT SOI MuGFET). We found that dopants diffused from Source –Drain into the edge of the undoped channel are the main source of variability. This emphasizes the role of extrinsic factors like the contact junctions for variability of any nanodevice.

In this study, we propose an accurate method for electrical extraction of thin silicon film thickness, based on an analytical modelling of the subthreshold inversion charge valid from front to back channel conduction and including quantum confinement effects. This method has been validated on both numerical simulation and experimental results and can be used for low-doped channel FDSOI or double gate devices.

This paper explores a novel 3D one transistor / one RRAM (1T1R) memory cube. The proposed architecture integrates HfO 2 -based OxRAM with select junctionless (JL) transistors based on low-voltage Gate-All-Around (GAA) stacked NanoSheet (NS) technology. A bitcell size of 23.9×F2/N is achieved (‘N’ being the number of stacked-NS) as well as a very high write and read parallelism. Extensive characterization of JL transistors and OxRAMs is performed to show their ability to be co-integrated inside a same 1T1R memory cell. Electrical characterization of 4kbits OxRAM arrays shows a large memory window (HRS/LRS=20) up to 104 cycles with a current compliance of 150µA, compatible with the performances of our JL transistors. Then, we experimentally demonstrate scouting logic operations capability with 2 operands, which should be extended to 4 operands thanks to an original two cells/bit “double coding” scheme assessed by SPICE simulations. Finally, we evidenced that this computing scheme is 2 times more energy efficient than a write-verify approach.