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High-quality homogeneous junctions are of great significance for developing transition metal dichalcogenides (TMDs) based electronic and optoelectronic devices. Here, we demonstrate a lateral p-type/intrinsic/n-type (p-i-n) homojunction based multilayer WSe2 diode. The photodiode is formed through selective doping, more specifically by utilizing self-aligning surface plasma treatment at the contact regions, while keeping the WSe2 channel intrinsic. Electrical measurements of such a diode reveal an ideal rectifying behavior with a current on/off ratio as high as 1.2 × 106 and an ideality factor of 1.14. While operating in the photovoltaic mode, the diode presents an excellent photodetecting performance under 450 nm light illumination, including an open-circuit voltage of 340 mV, a responsivity of 0.1 A W-1, and a specific detectivity of 2.2 × 1013 Jones. Furthermore, benefiting from the lateral p-i-n configuration, the slow photoresponse dynamics including the photocarrier diffusion in undepleted regions and photocarrier trapping/detrapping due to dopants or doping process induced defect states are significantly suppressed. Consequently, a record-breaking response time of 264 ns and a 3 dB bandwidth of 1.9 MHz are realized, compared with the previously reported TMDs based photodetectors. The above-mentioned desirable properties, together with CMOS compatible processes, make this WSe2p-i-n junction diode promising for future applications in self-powered high-frequency weak signal photodetection.

Two-dimensional heterojunctions exhibit many unique features in nanoelectronic and optoelectronic devices. However, heterojunction engineering requires a complicated alignment process and some defects are inevitably introduced during material preparation. In this work, a laser scanning technique is used to construct a lateral WSe2 p-n junction. The laser-scanned region shows p-type behavior, and the adjacent region is electrically n-doped with a proper gate voltage. The laser-oxidized product WOx is found to be responsible for this p-type doping. After laser scanning, WSe2 displays a change from ambipolar to unipolar p-type property. A significant photocurrent emerges at the p-n junction. Therefore, a self-powered WSe2 photodetector can be fabricated based on this junction, which presents a large photoswitching ratio of 106, a high photoresponsivity of 800 mA W-1, and a short photoresponse time with long-term stability and reproducibility. Therefore, this selective laser-doping method is prospective in future electronic applications.

Heterostructures with built-in electric fields are crucial for charge separation and lateral photovoltaic effect in current position-sensitive detectors (PSDs), which have to be produced by combining semiconductors with metal or other semiconductors to form various vertical junctions (e.g. Schottky junctions) via complicated and high-cost manufacture processes. In the present work, it was found that vertical junctions can be directly written and patterned inside graphene oxide (GO) films with gradient C/O ratios by laser scribing due to the optical filter effect of the films and the formation of reduced GO (rGO) layers. Such junctions were verified to show the capability for high-precision position sensing on the micrometer scale, owing to the lateral photovoltaic effect. These self-powered laser-scribed PSDs can exhibit a small nonlinearity of

In this investigation, we experimentally demonstrated a high-speed Gbps long-distance real-time visible light communication system based on non-return-to-zero on-off keying modulation by using a high-bandwidth Gallium nitride-based micro-LED with a modulation bandwidth of ∼230 MHz and a size of 40 μ m $ \times $ 40 μ m. The maximum real-time data rate obtained is up to 1.3 Gbps at a 3 m free-space transmission distance with a bit-error rate (BER) of 3.4 $ \times $ 10 –3 and 1 Gbps at a 10 m distance with a BER of 3.2 $ \times $ 10–3, both of which are underneath the forward error correction threshold of 3.8 $ \times $ 10–3 required for free-error operation. In addition, when the transmission distance is increased to 16 m in free space through reflecting the emission light beam by blue reflectors mounted on the wall, a data rate of 0.87 Gbps with a BER of 3.5 $ \times $ 10–3 is achieved successfully.

Microwave annealing (MWA) and furnace annealing are compared for their low thermal budget capability to improve the characteristics of ZnO-based thin-film transistors (TFTs). Both the ZnO channel and the Al2O3 gate dielectric are fabricated using atomic layer deposition. Using Si-wafer-susceptor assisted MWA with a substantial reduction of both annealing temperature and duration, significant improvements of the characteristics of the ZnO TFTs can be attained. A multi-step MWA process is found to further improve the characteristics of the TFTs. For the same microwave power and total duration, the field-effect mobility of the multi-step MWA TFT is 42% greater than that of the one-step MWA TFT with a similar sub-threshold swing. The multi-step MWA process can serve the purpose at temperatures as low as 220 °C.

In this study, we have realized controllable fabrication of gold nanopatterns on pristine monolayer graphene by using nanosphere lithography, in which polystyrene (PS) spheres are used as templates. With this method, periodically ordered triangular Au nanopatterns are uniformly formed on graphene surface. Micro-Raman spectroscopy shows that these sacrificial PS templates have no obvious effect on graphene surface structure while the subsequently formed Au nanopatterns are found to enhance Raman intensity of G and 2D bands by surface plasmon resonance. The compressive stress introduced in the metal deposition process leads to an obvious blue shift of 2D band. Besides, the metal-induced doping effect reduces the intensity ratio between 2D and G bands. This uniform arrangement of metal nanostructure is expected to grow other nanomaterials or used as Raman enhancement substrate in biomedicine, catalyzer and optics areas.

In this report, an anomalous time-evolution of electrical current in organic thin-film transistors, OTFTs, is revealed by employing a specially tailored semiconductor composite channel. The composite is designed by controlling the density of carbon nanotubes dispersed in a host semiconducting polymer below electrical percolation. The current anomaly, which, to the best of our knowledge, has never been observed before, is directly correlated to strong many-body interactions instantaneously occurring in the system under investigation. In essence, two on-chain positively charged polarons are fused with an electrochemically generated negative hydroxyl ion, OH−, in the H2O/O2 redox reaction to form a trion. The trion, which is characteristic of the polymer, is intrinsically metastable and can dissociate to mobile polarons under the influence of electric field, temperature and/or light illumination. The rate of trion formation is almost three orders of magnitude higher than that of trion dissociation. The fast formation and slow dissociation of the trions is the cause responsible for the observed current anomaly. The metastable trion is, hence, of fundamental importance in the operation of OTFTs. Understanding the fundamentals pertaining to the anomalous phenomenon not only is crucial for design of more efficient devices but also can guide development of future, emerging applications of OTFTs.

Charge carriers in graphene exhibit distinct characteristics from those in other two-dimensional materials because of their chiral nature. Additionally, multiple Dirac cones that emerge in graphene superlattices have been regarded as an interesting point in condensed-matter physics in recent years. Here, we report an investigation of the magneto-conductance in graphene encapsulated on the top and bottom by aligned h-BN. The bottom h-BN is precisely aligned with graphene, while the top h-BN is rotated a very small angle relative to it. Such a heterostructure could spoil the commensurate state existing in precisely aligned graphene while the giant moiré superlattice remains. A clear signature of weak localization and weak anti-localization is observed at multiple Dirac cones. Both the weak (anti)localization and the universal conductance fluctuations exhibit strong dependencies on the carrier density, temperature and channel length. This artificial heterostructure allows one to explore quantum interference in graphene with a wide spectrum of electronic properties.

Dopant-segregated source/drain contacts in a p-channel Schottky-barrier metal-oxide semiconductor field-effect transistor (SB-MOSFET) require further hole Schottky barrier height (SBH) regulation toward sub-0.1 eV levels to improve their competitiveness with conventional field-effect transistors. Because of the solubility limits of dopants in silicon, the requirements for effective hole SBH reduction with dopant segregation cannot be satisfied using mono-implantation. In this study, we demonstrate a potential solution for further SBH tuning by implementing the dual implantation of boron (B) and aluminum (Al) in combination with microwave annealing (MWA). By using such a method, not only has the lowest hole SBH ever with 0.07 eV in NiSi/n-Si contacts been realized, but also the annealing duration of MWA was sharply reduced to 60 s. Moreover, we investigated the SBH tuning mechanisms of the dual-implanted diodes with microwave annealing, including the dopant segregation, activation effect, and dual-barrier tuning effect of Al. With the selection of appropriate implantation conditions, the dual implantation of B and Al combined with the MWA technique shows promise for the fabrication of future p-channel SB-MOSFETs with a lower thermal budget.

We successfully thinned multilayer MoS 2 flakes to monolayer by a simple and low-cost fabrication using thermal annealing in air. Optical microscopy, Raman microscopy and atomic force spectroscopy were used to characterize the process of thermal thinning. Our results demonstrate a satisfactory uniformity of annealed monolayer MoS 2 . This process might show advantages in fabrication of nano-electronic devices based on thermally thinned MoS 2 .

Poly(vinylidene difluoride) (PVDF) blends with single-walled carbon nanotubes (SWNTs) have been prepared to investigate the interaction between nanotubes and polymer. The SWNTs are observed to form a good dispersion in the fluoropolymer matrix. Raman measurements showed sizable changes in the frequencies and intensities of SWNTs and PVDF in the composites compared with the values in pristine SWNTs and neat PVDF. This originates from the polymer's preferential interaction with metallic SWNTs (m-SWNTs), especially with small-diameter tubes, due to non-vanishing Fermi electrons and increased curvature-induced strain energy. In addition, the selective dispersion of m-SWNTs induced remarkable enhancement in the β-ferroelectric phase of PVDF as demonstrated by Fourier transform infrared spectroscopy (FTIR).

Graphene based field effect transistors (GFETs) are quite sensitive to surface effects, such as the influence from surface adsorbents. In this work, it demonstrates the meta/ferroelectric [P(VDF-TrFE)]/graphene(MFG) configuration can realize the novel nonvolatile memories where competition between the ferroelectric polarization and charging / discharging of graphene / interface traps has been addressed.

The future electronic application of graphene highly relies on the production of large-area high-quality single-crystal graphene. However, the growth of single-crystal graphene on different substrates via either single nucleation or seamless stitching is carried out at a temperature of 1000 °C or higher. The usage of this high temperature generates a variety of problems, including complexity of operation, higher contamination, metal evaporation, and wrinkles owing to the mismatch of thermal expansion coefficients between the substrate and graphene. Here, a new approach for the fabrication of ultraflat single-crystal graphene using Cu/Ni (111)/sapphire wafers at lower temperature is reported. It is found that the temperature of epitaxial growth of graphene using Cu/Ni (111) can be reduced to 750 °C, much lower than that of earlier reports on catalytic surfaces. Devices made of graphene grown at 750 °C have a carrier mobility up to ≈9700 cm2 V-1 s-1 at room temperature. This work shines light on a way toward a much lower temperature growth of high-quality graphene in single crystallinity, which could benefit future electronic applications.

Hysteresis-free logic gates capable of operation at 100 kHz are fabricated basing on local-gate thin-film transistors with their channel featuring solution-processed composite films of single-walled carbon nanotubes (SWCNTs) and poly(9,9-dioctylfluorene-co-bithiophene) (F8T2). Using dip-coating for deposition of composite films, high-density SWCNTs are found to be embedded in an F8T2 layer and thus being kept from the underlying AlOx gate dielectric by a certain distance. The presence of the F8T2 interlayer effectively suppresses hysteresis although it also weakens the gate electrostatic control. The fabricated transistors are characterized by nil hysteresis, high carrier mobility, large ON/OFF current ratio, low operation voltage, small subthreshold swing, and remarkable scalability. These properties are crucial for the realization of the well-performing logic circuits.

In the field of electronic gas sensing, low-dimensional semiconductors such as single-walled carbon nanotubes (SWCNTs) can offer high detection sensitivity owing to their unprecedentedly large surface-to-volume ratio. The sensitivity and responsivity can further improve by increasing their areal density. Here, an accelerated gas adsorption is demonstrated by exploiting volumetric effects via dispersion of SWCNTs into a percolating three-dimensional (3D) network in a semiconducting polymer. The resultant semiconducting composite film is evaluated as a sensing membrane in field effect transistor (FET) sensors. In order to attain reproducible characteristics of the FET sensors, a pulsed-gate-bias measurement technique is adopted to eliminate current hysteresis and drift of sensing baseline. The rate of gas adsorption follows the Langmuir-type isotherm as a function of gas concentration and scales with film thickness. This rate is up to 5 times higher in the composite than only with an SWCNT network in the transistor channel, which in turn results in a 7-fold shorter time constant of adsorption with the composite. The description of gas adsorption developed in the present work is generic for all semiconductors and the demonstrated composite with 3D percolating SWCNTs dispersed in functional polymer represents a promising new type of material for advanced gas sensors.

Layered two-dimensional semiconductors have attracted tremendous attention owing to their demonstrated excellent transistor switching characteristics with a large ratio of on-state to off-state current, Ion/Ioff. However, the depletion-mode nature of the transistors sets a limit on the thickness of the layered semiconductor films primarily determined by a given Ion/Ioff as an acceptable specification. Identifying the optimum thickness range is of significance for material synthesis and device fabrication. Here, we systematically investigate the thickness-dependent switching behavior of transistors with a wide thickness range of multilayer-MoS2 films. A difference in Ion/Ioff by several orders of magnitude is observed when the film thickness, t, approaches a critical depletion width. The decrease in Ion/Ioff is exponential for t between 20 nm and 100 nm, by a factor of 10 for each additional 10 nm. For t larger than 100 nm, Ion/Ioff approaches unity. Simulation using technical computer-aided tools established for silicon technology faithfully reproduces the experimentally determined scaling behavior of Ion/Ioff with t. This excellent agreement confirms that multilayer-MoS2 films can be approximated as a homogeneous semiconductor with high surface conductivity that tends to deteriorate Ion/Ioff. Our findings are helpful in guiding material synthesis and designing advanced field-effect transistors based on the layered semiconductors.

Small-hysteresis, high-performance thin-film transistors (TFTs) are readily realized simply by dip-coating of a solution-processable composite. The composite consists of single-walled carbon nanotubes (SWCNTs) embedded in semiconducting polymer used as the channel material. The resultant TFTs simultaneously exhibit large on/off current ratio, high on-current level, high mobility in the range 10-20 cm(2)V(-1)s(-1), and good uniformity and scalability.

Nanoscale PZT gratings are successfully transferred to a Pt substrate using reversal nanoimprint technique without any chemical etch processes. The transfer process is preliminarily studied by measuring the surface topography of PZT coated on templates before transferring as well as the transferred patterns on substrates. Piezoelectric force microscopy (PFM) and Raman spectroscopy are used to investigate the transferred PZT nanostructures after annealing. Good ferroelectric and structural properties have been demonstrated by the transferred PZT nanostructures, indicating that this reversal imprint technique is applicable for forming nanoscale PZT domains, which may lead to the manufactures of high density data storage devices at economic cost.

This paper focuses on different silicidation schemes toward a controllable NiSi-based metallic source/drain (MSD) process with restricted lateral encroachment of NiSi. These schemes include thickness control of Ni, Ni-Pt alloying, and two-step annealing. Experimental results show that all the three process schemes can give rise to effective control of lateral encroachment during Ni silicidation. By controlling tNi, NiSi-based MSD metal-oxide-semiconductor field-effect transistors (MOSFETs) of gate length LG = 55 nm are readily realized on ultrathin-body silicon-on-insulator substrates with 20-nm surface Si thickness. With the aid of dopant segregation (DS) to modifying the Schottky barrier heights of NiSi, both n- and p-type MSD MOSFETs show significant performance improvement, compared to reference devices without DS.

Graphene is characterized by demonstrated unique properties for potential novel applications in photodetection operated in the frequency range from ultraviolet to terahertz. To date, detailed work on identifying the origin of photoresponse in graphene is still ongoing. Here, scanning photocurrent microscopy to explore the nature of photocurrent generated at the monolayer-multilayer graphene junction is employed. It is found that the contributing photocurrent mechanism relies on the mismatch of the Dirac points between the monolayer and multilayer graphene. For overlapping Dirac points, only photothermoelectric effect (PTE) is observed at the junction. When they do not coincide, a different photocurrent due to photovoltaic effect (PVE) appears and becomes more pronounced with larger separation of the Dirac points. While only PTE is reported for a monolayer-bilayer graphene junction in the literature, this work confirms the coexistence of PTE and PVE, thereby extending the understanding of photocurrent in graphene-based heterojunctions.

Transition metal dichalcogenides (TMDCs) in monolayer form have attracted a great deal of attention for electronic and optical applications. Compared to mechanical exfoliation and chemical synthesis, laser thinning is a novel and unique “on-demand” approach to fabricate monolayers or pattern desired shapes with high controllability and reproducibility. Its successful demonstration motivates a further exploration of the dynamic behaviour of this local thinning process. Here, we present an in-situ study of void formation by laser irradiation with the assistance of temporal Raman evolution. In the analysis of time-dependent Raman intensity, an empirical formula relating void size to laser power and exposure time is established. Void in thinner MoS2 flakes grows faster than in thicker ones as a result of reduced sublimation temperature in the two-dimensional (2D) materials. Our study provides useful insights into the laser-thinning dynamics of 2D TMDCs and guidelines for an effective control over the void formation.

Graphene-based optoelectronic devices, including reduced graphene oxide (RGO) devices, commonly exhibit a large dark current and low on/off ratio with high dark-power consumption and a small responsivity. In this study, semi-RGO-based infrared photodetectors were directly "written" by using lasers, which can exhibit a small dark current of approximately 12 µA/cm2 with a high responsivity of approximately 0.18 A/W at 1,550 nm. Both the dark current and response speed can be tuned with GO as the gate dielectric in a field-effect transistor structure. These findings suggest the possibility of the three-dimensional "writing" of a micro-optoelectronic device or system with a low cost and high performance.

In this paper, capacitive-type humidity sensors were prepared by sequentially drop-coating the aqueous suspensions of zinc oxide (ZnO) nanopowders and polyvinyl pyrrolidone–reduced graphene oxide (PVP-RGO) nanocomposites onto interdigitated electrodes. Significant improvements in both sensitivity and linearity were achieved for the ZnO/PVP-RGO sensors compared with the PVP-RGO/ZnO, PVP-RGO, and ZnO counterparts. Moreover, the produced ZnO/PVP-RGO sensors exhibited rather small hysteresis, fast response-recovery time, and long-term stability. Based on morphological and structural analyses, it can be inferred that the excellent humidity sensing properties of the ZnO/PVP-RGO sensors may be attributed to the high surface-to-volume ratio of the multilayer structure and the supporting roles of the PVP-RGO nanocomposites. The results in this work hence provide adequate guidelines for designing high-performance humidity sensors that make use of the multilayer structure of semiconductor oxide materials and PVP-RGO nanocomposites.

As a finite-energy-bandgap alternative to graphene, semiconducting molybdenum disulfide (MoS2) has recently attracted extensive interest for energy and sensor applications. In particular for broad-spectral photodetectors, multilayer MoS2 is more appealing than its monolayer counterpart. However, little is understood regarding the physics underlying the photoresponse of multilayer MoS2. Here, we employ scanning photocurrent microscopy to identify the nature of photocurrent generated in multilayer MoS2 transistors. The generation and transport of photocurrent in multilayer MoS2 are found to differ from those in other low-dimensional materials that only contribute with either photovoltaic effect (PVE) or photothermoelectric effect (PTE). In multilayer MoS2, the PVE at the MoS2-metal interface dominates in the accumulation regime whereas the hot-carrier-assisted PTE prevails in the depletion regime. Besides, the anomalously large Seebeck coefficient observed in multilayer MoS2, which has also been reported by others, is caused by hot photo-excited carriers that are not in thermal equilibrium with the MoS2 lattice.

GaN-based light emitting diodes (LEDs) have been fabricated on sapphire substrates with different thicknesses of GaN buffer layer grown by a combination of hydride vapor phase epitaxy and metalorganic chemical vapor deposition. We analyzed the LED efficiency and modulation characteristics with buffer thicknesses of 12 µm and 30 µm. With the buffer thickness increase, cathodoluminescence hyperspectral imaging shows that the dislocation density in the buffer layer decreases from ∼1.3X10 8 cm-2 to∼1.0 X 10 8 cm-2, and Raman spectra suggest that the compressive stress in the quantum wells is partly relaxed, which leads to a large blue shift in the peak emission wavelength of the photoluminescence and electroluminescent spectra. The combined effects of the low dislocation density and stress relaxation lead to improvements in the efficiency of LEDs with the 30 µm GaN buffer, but the electrical-to-optical modulation bandwidth is higher for the LEDs with the 12 µm GaN buffer. A rate equation analysis suggests that defect-related nonradiative recombination can help increase the modulation bandwidth but reduce the LED efficiency at low currents, suggesting that a compromise should be made in the choice of defect density.

An extensive investigation of carrier mobility is presented for thin-film transistors (TFTs) with single-walled carbon nanotube (SWCNT) networks as the semiconductor channel. For TFTs particularly with low-density SWCNTs in the networks, the extracted mobility using the standard method for Si metal-oxide-semiconductor field-effect transistors is erroneous, mainly resulting from use of a parallel-plate capacitor model and assumption of the source-drain current being inversely proportional to the channel length. Large hysteresis in the transfer characteristics further complicates the extraction. By properly addressing all these challenges in this letter, a comprehensive methodology is established, leading to the extraction of mobility values that are independent of geometrical parameters.

A voltage-pulse method is utilized to investigate the charge-injection-induced time decay of the source-drain current of field-effect transistors with randomly networked single-walled carbon nanotubes (CNTs) as the conduction channel. The relaxation of trapped carriers in the CNT networks can be accounted for by assuming two exponential decays occurring simultaneously. The slow decay is characterized by a time constant comparable to literature data obtained for a carrier recombination in the semiconducting CNTs. The faster decay with a time constant that has a smaller order of magnitude is attributed to the annihilation of trapped carriers in metallic CNTs or at metal-CNT contacts. Both time constants are gate-bias dependent.

The ferroelectric random access memory (FRAM) which uses ferroelectric thin film as memory material is considered to be a candidate for the next generation memory application. In this work, we apply nano-embossing technology to fabricate Pb(Zr"0"."3,Ti"0"."7)O"3 (PZT) ferroelectric thin film nanostructures and investigate the influence of the patterning process on the material and ferroelectric properties by using SEM, XRD and Precision Ferroelectric Tester. Embossing process has been optimized for embossing depth and pattern profile. It was found that embossing will result in (100) preferred orientation of the PZT thin film. The electrical characteristics of patterned and un-patterned PZT films have been also studied for comparison.

Hysteresis in the current–voltage characteristics is one of the major obstacles to the implementation of organic thin-film transistors in large-area integrated circuits. The hysteresis has been correlated either extrinsically to various charge-trapping/transfer mechanisms arising from gate dielectrics or surrounding ambience or intrinsically to the polaron–bipolaron reaction in low-mobility conjugated polymer thin-film transistors. However, a comprehensive understanding essential for developing viable solutions to eliminate hysteresis is yet to be established. By embedding carbon nanotubes in the polymer-based conduction channel of various lengths, here we show that the bipolaron formation/recombination combined with the H2O/O2 electrochemical reaction is responsible for the hysteresis in organic thin-film transistors. The bipolaron-induced hysteresis is a thermally activated process with an apparent activation energy of 0.29 eV for the bipolaron dissociation. This finding leads to a hysteresis model that is generally valid for thin-film transistors with both band transport and hopping conduction in semiconducting thin films. Current hysteresis restricts the applications of organic thin-film transistors, and a mechanistic understanding is lacking despite extensive studies on it. Qu et al.demonstrate experimentally that current hysteresis is caused by an interaction between bipolaron and the water/oxygen redox couple.

In this work, complex 3D ferroelectric nanostructures on Poly(vinylidenefluoride-trifluoroethylene), P(VDF-TrFE), films have successfully been fabricated using a special hot-embossing process with two sequential shots on the same site with a grating template and a dot array template of the same periodicity at the same hot-embossing temperature. The nanostructures have been characterized with atomic force microscope (AFM), piezoresponse force microscope (PFM) and Fourier transformed infrared spectroscopy (FTIR). It is shown that sequential hot-embossing offers an effective way to fabricate complex 3D nanostructures of functional ferroelectric materials toward various applications.

This letter presents a systematic investigation of the gate capacitance CGof thin-film transistors (TFTs) based on randomly distributed single-walled carbon nanotubes (SWCNTs) in the channel. In order to reduce false counting of SWCNTs that do not contribute to current conduction, CG is directly measured on the TFTs using a well-established method for MOSFETs. Frequency dispersion of CG is observed, and it is found to depend on the percolation behavior in SWCNT networks. This dependence can be accounted for using an RC transmission line model. These results are of important implications for the determination of carrier mobility in nanoparticle-based TFTs. © 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.QC 20120214 VINNOVA “iPack Vinnex Excellence Center” VR 2009-8068

As metal - oxide - semiconductor field-effect transistors (MOSFETs) down scaling progresses into the nanometer regime, quantum mechanical effects are becoming more and more significant. In this work, a model for the surrounding-gate (SG) nMOSFET is developed. The Schrodinger equation is solved analytically and some of the results are verified via simulations. We find that the percentage of the electrons with a lighter conductivity mass increases as the temperature decreases, or as the gate voltage reduces. These imply that low temperature and low gate voltage will enhance the electron effective mobility, which is good for the device performance.

A thin Al2O3 dielectric film was directly grown onto graphene layers without any surface treatment prior to H2O-based atomic layer deposition for the first time. The growth mechanism of Al2O3 dielectric film has been studied by changing the growth temperature and purge time. We found that the film morphology was influenced by the amount and distribution of physically adsorbed precursor molecules on the graphene, especially by physically adsorbed H2O molecules. Within an optimal temperature window, conformal and uniform Al2O3 thin films were obtained as confirmed by atomic force microscopy and transmission electron microscopy results. Raman spectroscopy revealed that no extra defects are generated in the graphene layers. Furthermore, the low leakage current and interface traps in dual-gated graphene field-effect transistors demonstrate the high-quality dielectric/graphene stack.

The unique electronic properties of graphene are exploited for field-effect sensing in both capacitor and transistor modes when operating the sensor device in electrolyte. The device is fabricated using large-area graphene thin films prepared by means of layer-by-layer stacking. Although essentially the same device, its operation in the capacitor mode is found to yield more information than in the transistor mode. The capacitor sensor can simultaneously detect the variations of surface potential and electrical-double-layer capacitance at the graphene/electrolyte interface when altering the ion concentration. The capacitor-mode operation further facilitates studies of the molecular binding-adsorption kinetics by monitoring the capacitance transient.

A model for a metal–oxide–semiconductor field-effect transistor (MOSFET) with a double gate (DG) is developed. Quantum mechanical effects on the threshold voltage (V TH) are modeled and investigated analytically. The analytic model shows how V TH is increased with quantum mechanical effect. The model is applicable to both symmetric DG (SDG) and asymmetric DG (ADG) nMOSFETs, and is also applicable to both doped and undoped DG nMOSFETs. The analytic results are verified by comparing with the results obtained from simulations using Schred, and good agreement is observed. The V TH of an ADG nMOSFET will shift more than that of an SDG nMOSFET, and the V TH of a DG transistor with (110)-silicon (Si) orientation will shift more than that of a DG transistor with (100)-Si orientation. When the silicon thickness t si < 3 nm, the V TH shift will be significant, and one should be careful in the use of an extremely thin silicon body. When the body doping density (N A) is not high (18 cm-3), the V TH shift is almost the same for different N A. When N A > 1018 cm-3, the higher the N A, the more the V TH shift.