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Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics. [ABSTRACT FROM AUTHOR]

Hot electron trapping can significantly modify the performance of GaN-based HEMTs during hard switching operation. In this letter, we present a physics-based model based on rate equations to model the trapping kinetics of hot-electrons in GaN transistors submitted to semi-ON-state stress. The model is validated through comparison with the experimental data, obtained by means of a pulsed-drain current transient setup developed ad-hoc. Hot-electron trapping is found to have logarithmic time dependence; the first 10 μs of operation are critical in determining the current collapse during stress. [ABSTRACT FROM AUTHOR]

RON degradation due to stress in GaN-based power devices is a critical issue that limits, among other effects, long-term stable operation. Here, by means of 2-D device simulations, we show that the RON increase and decrease during stress and recovery experiments in carbon-doped AlGaN/GaN power metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) can be explained with a model based on the emission, redistribution, and retrapping of holes within the carbon-doped buffer (“hole redistribution” in short). By comparing simulation results with front- and back-gating OFF-state stress experiments, we provide an explanation for the puzzling observation of both stress and recovery transients being thermally activated with the same activation energy of about 0.9 eV. This finds a straightforward justification in a model in which both RON degradation and recovery processes are limited by hole emission by dominant carbon-related acceptors that are energetically located at about 0.9 eV from the GaN valence band. [ABSTRACT FROM AUTHOR]

The aim of this paper is to improve the understanding of gallium nitride (GaN) high electron mobility transistors (HEMTs) submitted to hard switching operation, with focus on the hot-electron phenomena. This is becoming a hot-topic both for the scientific community and for the industry. The analysis is carried out through a cross-comparison of three different experimental techniques: conventional Pulsed-IV characterization, a novel pulsed-drain current transient (P-DCT) method, and a custom-developed hard switching test protocol. Hard switching analysis was performed through a novel system able to test the device in hard-switching conditions with an unprecedented turn-on slew-rate of 25 V ns−1 on-wafer level. This allows μs to investigate the impact of hard switching in terms of (i) locus trajectory, (ii) dissipated power, and (iii) dynamic increase. Furthermore, the accumulation of switching stress is assessed by repeating the experiment with increasing frequency, from 1 kHz to 100 kHz. The extensive cross-analysis offers a novel insight on the degradation mechanisms occurring in power GaN HEMTs. The results collected within this paper allow: (1) to evaluate the dynamic behavior under both soft- and hard-switching stress, thus differentiating off-state and semi-on-state stress; (2) to pinpoint hot-electrons as the main cause of the current collapse observed in semi-on; (3) by comparing the results obtained from P-DCT and Hard Switching Analysis we demonstrate that the hot-electron trapping is a very fast process which can happen in few ns. The related trapping and de-trapping kinetics are investigated in detail. The results described within this paper provide novel insight on the important role of hot-electrons in the dynamic increase during hard switching operations. [ABSTRACT FROM AUTHOR]

In this article, pulsed measurements of thermal resistance in GaN-based high-electron mobility transistors (HEMTs) on silicon, with different gate geometries and gate-to-drain extensions, are analyzed and modeled. Simple expressions for the thermal resistance of silicon-on-insulator (SOI) MOSFETs, which take into account the gate width and channel length, can be adapted to model the thermal resistance of these GaN-based HEMTs. Narrow width effects and the increase in the heat flow through the gate as the channel length increases were correctly reproduced. In addition, numerical simulations were performed to explain the reduction obtained in thermal resistance as the gate-to-drain extension increases. Our approach can also be applied easily to other well-established models using circuit simulators. [ABSTRACT FROM AUTHOR]

This study presents a novel system to investigate the on-wafer level dynamic properties of GaN-based power transistors in hard-switching application conditions. The system is able to analyse devices with an on-resistance (RDSON) in the range from few ohms to hundreds of ohms, and can be effectively used to improve the development process of GaN high electron mobility transistors (HEMTs) power devices at the wafer level. Contrary to the conventional double-pulse setup, where a resistive load is usually used in combination with a very low duty cycle, the dynamic RDSON is acquired during realistic operating conditions, in a boost converter circuit. Consequently, the authors' system is able to study not only the field-activated trapping processes, but also those induced by hard-switching conditions, i.e. promoted by hot electrons and self-heating. The maximum working voltage (600 V) and the minimum RDSON measurement time after turn-on (2 µs) allow evaluating the operation limit of the devices in a voltage/frequency range close to real switching conditions. Working on the wafer level allows a more realistic assessment of the dynamic RDSON behaviour before the packaging phase, which is very important to improve the production and development process of GaN-HEMT devices. [ABSTRACT FROM AUTHOR]

This paper investigates the degradation of vertically aligned gallium nitride (GaN) nanowire (NW) arrays submitted to gate bias stress and UV light. Based on electrical tests and simulations, we demonstrate the existence of trapping processes that depend on the applied stress voltage ${V}_{\textsf {Gstress}}$ and on the applied light during stress (wavelength, $\lambda $). We demonstrate the following original results: 1) for positive and negative ${V}_{\textsf {Gstress}}$ conditions, no significant variation in dc characteristics is observed when the samples are stressed in dark and 2) when the devices are submitted to negative ${V}_{\textsf {Gstress}}$ and to UV light, a positive variation in threshold voltage (${V}_{\textsf {th}}$) is observed. The positive ${V}_{\textsf {th}}$ shift is ascribed to the transfer and trapping of electrons from the gate metal to the oxide, promoted by UV light. We also evaluated the temperature dependence of the threshold voltage shift under UV light. We demonstrated an increased trapping at higher temperatures, indicating a role of thermionic processes in electron trapping. On the other hand, detrapping from oxide states proceeds through defect-mediated conduction, i.e., is limited by the number of available states. [ABSTRACT FROM AUTHOR]

The gate reliability of p-GaN gate AlGaN/GaN high electron mobility transistors with a ring-gate structure is investigated by step-stress experiments under a gate bias, combined with electroluminescence imaging and pulsed measurements. For gate stress (${V} _{\text {Gstress}}$) from 0 to 13 V, the drain current is found to be stable and decreases at 13 V at OFF-state and increases at ON-state. For ${V} _{\text {Gstress}}$ from 13 to 31 V, the drain current increases at OFF-state and decreases at ON-state, whereas ${V} _{\text {TH}}$ is stable and increases slightly. The changes in drain current characteristic and ${V} _{\text {TH}}$ values of the device after applying various ${V} _{\text {Gstress}}$ are associated with the injection and trapping of holes from the p-GaN layer to the AlGaN layer, supported by the results of pulsed measurements and by the simulation of energy band diagrams. When ${V} _{\text {Gstress}}$ is further increased to a high voltage of 31 V, ${V} _{\text {TH}}$ becomes noisy and a strong luminescence signal occurs with a sudden reduction in the drain current, and finally, a catastrophic failure happens in the gate-channel region. [ABSTRACT FROM AUTHOR]

The gate conduction mechanisms in p-gallium nitride (GaN)/AlGaN/GaN enhancement mode transistors are investigated using temperature-dependent dc gate current measurements. In each of the different gate voltage regions, a physical model is proposed and compared to experiment. At negative gate bias, Poole–Frenkel emission (PFE) occurs within the passivation dielectric from gate to source. At positive gate bias, the p-GaN/AlGaN/GaN “p-i-n” diode is in forward operation mode, and the gate current is limited by hole supply at the Schottky contact. At low gate voltages, the current is governed by thermionic emission with Schottky barrier lowering in dislocation lines. Increasing the gate voltage and temperature results in thermally assisted tunneling (TAT) across the same barrier. An improved gate process reduces the gate current in the positive gate bias region and eliminates the onset of TAT. However, at high positive gate bias, a sharp increase in current is observed originating from PFE at the metal/ p-GaN interface. Using the extracted conduction mechanisms for both devices, accurate lifetime models are constructed. The device fabricated with the novel gate process exhibits a maximum gate voltage of 7.2 V at ${t}_{\textsf {1}\%}=\textsf {10}$ years. [ABSTRACT FROM AUTHOR]

This letter reports on the observation of hot-electron and impact-ionization mechanisms in N-polar GaN-based MIS-HEMTs designed for high frequency (RF) operation. Thanks to the extremely low gate leakage of such devices, we were able to demonstrate—for the first time—a correlation between electroluminescence (EL) and gate current in the semi-on state. In the semi-on state, the devices show a non-monotonic, bell-shaped behavior of the EL-versus- ${\text {V}}_{\text {GS}}$ and of the ${I}_{\text {G}}$ -versus- ${V}_{\text {GS}}$ characteristics, and the intensity of the EL signal is proportional to the ${I}_{G}\times {I}_{D}$ product. The results are experimental evidence for impact ionization: the related mechanisms are described in detail in the letter. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

GaN-based transistors are promising devices for power switching applications, but their unique properties require careful design of the circuit in order to achieve the best performance and reliability. The first part will focus on the characterisation of deep-level effects in enhancement- and depletion-mode HEMTs, which limit the performance of the transistor. Threshold voltage instabilities in MIS-HEMT structures, caused by charge trapping under the gate, and their dependence on SiN acting as the gate dielectric will be reviewed. ON-resistance increase, caused by charge trapping in the gate-drain access region, will then be discussed in normally off gate injection transistors, as well as the effect of the switching frequency on the trapping-de-trapping equilibrium condition. The second part of the paper will discuss possible failure modes related to operating conditions, starting with the oxidation of the surface and the inverse piezoelectric effect at high gate-drain voltage. To have a complete picture of high-field effects, the gate dielectric and passivation robustness will be investigated. Time-dependent degradation will then be analysed in both gate reverse and forward-bias conditions. Finally, failures related to off-state stress and to power dissipation and electric field during an ESD event in AlGaN/GaN-HEMTs will be discussed. [ABSTRACT FROM AUTHOR]

This paper demonstrates and investigates the time-dependent vertical breakdown of GaN-on-Si power transistors. The study is based on electrical characterization, dc stress tests and electroluminescence measurements. We demonstrate the following original results: 1) when submitted to two-terminal (drain-to-substrate) stress, the AlGaN/GaN transistors show a time-dependent degradation process, which leads to the catastrophic failure of the devices; 2) time-to-failure follows a Weibull distribution and is exponentially dependent on stress voltage; 3) the degradation mechanism is strongly field dependent and weakly thermally activated, with an activation energy of 0.25 eV; and 4) emission microscopy suggests that vertical current flows under the whole drain area, possibly through extended defects. The catastrophic failure occurs at random positions under the drain contact. The time-dependent failure is ascribed to a percolation process activated by the high-electric field that leads to the generation of localized shunt paths between drain and substrate. [ABSTRACT FROM PUBLISHER]

This paper demonstrates that—for high-electric fields and drain current levels—the electroluminescence (EL) versus VGS curves of GaN-on-Si radio frequency HEMTs significantly deviate from the well-known bell-shape, due to the turn-on of a secondary EL process that has not been described so far in the literature. Based on the combined EL measurements, electrical characterization, and thermal analysis, we demonstrate that: 1) for moderate gate and drain voltages, the EL versus VGS curve has the characteristic bell shape, and light emission originates from hot electrons injected from the source; EL signal is stronger at the edges of the gate, due to the higher electric field; 2) at high drain/gate bias and temperature, a second process induces a monotonic increase in the EL versus VGS curve; in this case, the EL signal is stronger at the center of the gate, and the EL intensity is directly correlated with the gate leakage current. Based on the experimental evidence collected within this paper, the secondary luminescence process is ascribed to: 1) the injection of carriers from the gate metal to the channel; 2) the acceleration of these electrons by the high gate–drain field; and c) the subsequent radiative emission. [ABSTRACT FROM AUTHOR]

The role of carbon-related traps in GaN-based ungated high-electron mobility transistor structures has been investigated both experimentally and by means of numerical simulations. A clear quantitative correlation between the experimental data and numerical simulations has been obtained. The observed current decrease in the tested structure during backgating measurements has been explained simply by means of a thermally activated hole-emission process with EA = 0.9 eV, corresponding to the distance of the acceptor-like hole-trap level from the GaN valence band. Moreover, it has been demonstrated by means of electrical measurements and numerical simulations that only a low percentage of the nominal carbon doping levels induces the observed current reduction when negative substrate bias is applied to the tested structure. [ABSTRACT FROM AUTHOR]

This paper reports an experimental demonstration of the time-dependent failure of GaN-on-Si power high-electron-mobility transistors with p-GaN gate, submitted to a forward gate stress. By means of combined dc, optical analysis, and 2-D simulations, we demonstrate the following original results: 1) when submitted to a positive voltage stress (in the range of 7–9 V), the transistors show a time-dependent failure, which leads to a sudden increase in the gate current; 2) the time-to-failure (TTF) is exponentially dependent on the stress voltage and Weibull-distributed; 3) the TTF depends on the initial gate leakage current, i.e., on the initial defectiveness of the devices; 4) during/after stress, the devices show a localized luminescence signal (hot spots); the spectral investigation mainly reveals a peak corresponding to yellow luminescence and a broadband related to bremsstrahlung radiation; and 5) 2-D simulations were carried out to clarify the origin of the degradation process. The results support the hypothesis that the electric field in the AlGaN has a negligible impact on the device failure; on the contrary, the electric field in the SiN and in the p-GaN gate can play an important role in favoring the failure, which is possibly due to a defect generation/percolation process. [ABSTRACT FROM PUBLISHER]

In this brief, traps-related dispersion phenomena are investigated on GaN/AlGaN MOS-high-electron mobility transistors. Pulsed $I$ – $V$ characteristics and low-frequency-noise measurements are the characterization vehicles used to get a direct insight of the device trap-states. By considering a set of ten samples, device-to-device fluctuation parameters extracted from trap-related measurements (1/ $f$ noise and gate bias instability) are systematically compared with conventional electrical parameters (threshold voltage and ON-current). Two separate trends are identified and ascribed to two different trap families. [ABSTRACT FROM AUTHOR]

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator. [ABSTRACT FROM PUBLISHER]

This paper reports an extensive analysis of the trapping and reliability issues in AlGaN/GaN metal insulator semiconductor (MIS) high electron mobility transistors (HEMTs). The study was carried out on three sets of devices with different gate insulators, namely PEALD SiN, RTCVD SiN and ALD Al 2 O 3 . Based on combined dc, pulsed and transient measurements we demonstrate the following: (i) the material/deposition technique used for the gate dielectric can significantly influence the main dc parameters (threshold current, subthreshold slope, gate leakage) and the current collapse; and (ii) current collapse is mainly due to a threshold voltage shift, which is ascribed to the trapping of electrons at the gate insulator and/or at the AlGaN/insulator interface. The threshold voltage shift (induced by a given quiescent bias) is directly correlated to the leakage current injected from the gate; this demonstrates the importance of reducing gate leakage for improving the dynamic performance of the devices. (iii) Frequency-dependent capacitance–voltage (C–V) measurements demonstrate that optimized dielectric allow to lower the threshold-voltage hysteresis, the frequency dependent capacitance dispersion, and the conductive losses under forward-bias. (iv) The material/deposition technique has a significant impact on device robustness against gate positive bias stress. Time to failure is Weibull-distributed with a beta factor not significantly influenced by the properties of the gate insulator. The results presented within this paper provide an up-to-date overview of the main advantages and limitations of GaN-based MIS HEMTs for power applications, on the related characterization techniques and on the possible strategies for improving device performance and reliability. [ABSTRACT FROM AUTHOR]

This paper reports an extensive analysis of the electrostatic discharge (ESD) robustness and of the corresponding failure mechanisms of AlGaN/gallium nitride high-electron mobility transistors. Based on transmission line pulse testing, we demonstrate the following results: 1) when ESD pulses are applied to the drain under pinchoff conditions, failure occurs through a field-dependent mechanism; the failure voltage is independent on the gate bias, and approximately equal to 300 V; 2) when ESD pulses are applied to the drain under ON-state conditions, a power-dependent mechanism prevails, lowering the ESD robustness; 3) vertical (drain substrate) breakdown does not significantly affect the ESD stability of the devices; the failure threshold for vertical failure is higher than 450 V; and 4) the length of the field plate can significantly impact the ESD behavior of the devices, by influencing the failure threshold and by favoring soft-degradation processes. Scanning electron microscopy was extensively used to achieve a complete description of the failure processes. [ABSTRACT FROM AUTHOR]

This paper reports the experimental demonstration of time-dependent dielectric breakdown in GaN-based high-electron mobility transistors (HEMTs) submitted to OFF-state stress. Based on combined breakdown measurements, constant voltage stress tests, and 2-D simulations, we demonstrate the following relevant results. First, GaN-based HEMTs with a breakdown voltage higher than 1000 V (evaluated by dc measurements) may show time-dependent failure when exposed to OFF-state stress with V\mathrm {DS} in the range 600–700 V. Second, time-to-failure (TTF) is Weibull-distributed, and has an exponential dependence on the stress voltage level. Third, time-dependent breakdown is ascribed to the failure of the SiN dielectric at the edge of the gate overhang, on the drain side. Fourth, 2-D simulations confirm that—in this region—the electric field exceeds 6 MV/cm, i.e., the dielectric strength of SiN. Finally, we demonstrate that by limiting the electric field in the nitride through epitaxy and process improvements, it is possible to increase the TTF by three orders of magnitude. [ABSTRACT FROM AUTHOR]

This paper reports an investigation of the trapping mechanisms responsible for the temperature-dependent dynamic- R\mathrm {\mathrm{{\scriptstyle ON}}} of GaN-based metal–insulator–semiconductor (MIS) high electron mobility transistors (HEMTs). More specifically, we perform the following. First, we propose a novel testing approach, based on combined OFF-state bias, backgating investigation, and positive substrate operation, to separately investigate the buffer- and the surface-related trapping processes. Then, we demonstrate that the dynamic R\mathrm {\mathrm{{\scriptstyle ON}}} of GaN-based MIS-HEMTs significantly increases when the devices are operated at high temperature levels. We explain this effect by demonstrating that it is due to the increased injection of electrons from the substrate to the buffer (under backgating conditions) and from the gate to the surface (under positive substrate operation). Finally, we demonstrate that by optimizing the buffer and by reducing the vertical leakage, substrate-related trapping effects can be completely suppressed. The results described within this paper provide general guidelines for the evaluation of the origin of dynamic R\mathrm {\mathrm{{\scriptstyle ON}}} in GaN power HEMTs and point out the important role of the buffer leakage in favouring the trapping processes. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but—more likely—to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

Results obtained during the evaluation of radio frequency (RF) reliability carried out on several devices fabricated with different epi-structure and field-plate geometries will be presented and discussed. Devices without a field-plate structure experienced a more severe degradation when compared to their counterparts while no significant correlation has been observed with respect of the different epi-structure tested. RF stress induced two main changes in the device electrical characteristics, i.e., an increase in drain current dispersion and a reduction in gate-leakage currents. Both of these phenomena can be explained by assuming a density increase of an acceptor trap located beneath the gate contact and in the device barrier layer. Numerical simulations carried out with the aim of supporting the proposed mechanism will also be presented. [ABSTRACT FROM AUTHOR]

This letter demonstrates that GaN-based MIS-HEMTs submitted to stress with high-temperature, high drain bias, and constant source current (HTSC stress) may show degradation modes that are not detectable during standard high temperature reverse bias (HTRB) stress. Based on a number of stress/recovery experiments, we demonstrate the following novel results: 1) the combined presence of high drain bias and constant drain–source current (HTSC stress) can lead to a significant increase in ON-resistance ( R\mathrm{\scriptscriptstyle ON} ) that is not detected under conventional HTRB stress; 2) R\mathrm{\scriptscriptstyle ON} increases without changes in the threshold voltage, indicating that charge trapping takes place in the access regions, and not under the gate; 3) the R\mathrm{\scriptscriptstyle ON} increase has a monotonic dependence on the source current flowing during stress; and 4) for the same stress current level, the R\mathrm{\scriptscriptstyle ON} increase has a negative dependence on temperature. The strong correlation between R\mathrm{\scriptscriptstyle ON} increase and source current and the negative temperature coefficient strongly support the hypothesis that trapping originates from the injection of hot electrons toward the gate–drain access region. [ABSTRACT FROM PUBLISHER]

This paper reports the experimental demonstration of a novel degradation mechanism of high-power AlGaN/GaN high electron mobility transistors (HEMTs), that is, time-dependent drain-source breakdown. With current-controlled breakdown measurements and constant voltage stress experiments we demonstrate that: 1) when submitted to constant voltage stress, in the OFF-state, the HEMTs can show a significant degradation; 2) the degradation process is time-dependent, and consists of a measurable increase in subthreshold drain-source leakage; this effect is ascribed to the accumulation of positive charge in proximity of the gate, consistently with previous theoretical calculations; and 3) a catastrophic (and permanent) failure is observed for long stress times, possibly due to thermal runaway or to the increase in the electric field in proximity of the localized drain-source leakage paths. [ABSTRACT FROM AUTHOR]

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum. [ABSTRACT FROM AUTHOR]

In this paper, we review and add additional data and understandings on our findings on the two most common failure modes of GaN-based HEMTs: 1) permanent gate leakage current increase and 2) output current drop. We suggested that they have different origins and one is not necessarily correlated to the other. Yet, they can both concur to the device degradation. First, we demonstrate that the phenomenon of gate leakage current increase has a voltage-accelerated degradation kinetic. Therefore, the identification of the critical voltage for leakage increase is meaningless. We demonstrate that the time-to-breakdown tBD data are Weibull distributed and we prove that they represent intrinsic failures. According to our data, this phenomenon is not related to the inverse piezoelectric effect. Finally, a new degradation model for the gate leakage current increase based on the percolation path theory is proposed. Second, we show that the permanent output current drop is a consequence of the relaxation of AlGaN layer. This occurs by means of formation of crystallographic defects as described by the inverse piezoelectric degradation model. Finally, we show an excellent stability of devices with reduced Al content in the AlGaN barrier, proving the crucial role of strain in the reliability of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

This paper critically investigates the advantages and limitations of the current-transient methods used for the study of the deep levels in GaN-based high-electron mobility transistors (HEMTs), by evaluating how the procedures adopted for measurement and data analysis can influence the results of the investigation. The article is divided in two parts within Part I. 1) We analyze how the choice of the measurement and analysis parameters (such as the voltage levels used to induce the trapping phenomena and monitor the current transients, the duration of the filling pulses, and the method used for the extrapolation of the time constants of the capture/emission processes) can influence the results of the drain current transient investigation and can provide information on the location of the trap levels responsible for current collapse. 2) We present a database of defects described in more than 60 papers on GaN technology, which can be used to extract information on the nature and origin of the trap levels responsible for current collapse in AlGaN/GaN HEMTs. Within Part II, we investigate how self-heating can modify the results of drain current transient measurements on the basis of combined experimental activity and device simulation. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of AlGaN/GaN high electron mobility transistor failure physics and reliability, focusing on mechanisms affecting the gate-drain edge, where maximum electric field and peak temperatures are reached. Physical effects at the origin of device degradation (inverse piezoelectric effect, time-dependent trap formation and percolative conductive paths formation, and electrochemical AlGaN and GaN degradation) are discussed on the basis of literature data and unpublished results. Thermally activated mechanisms involving metal-metal and metal-semiconductor interdiffusion at the gate Schottky junction are also discussed. [ABSTRACT FROM AUTHOR]

An analysis of the reliability of GaN high-electron-mobility transistors during dc and RF stress tests is presented. Competing degradation mechanisms have been observed during RF operation, demonstrating the dependence of device reliability on device RF driving conditions. DC tests revealed only one degradation pattern related to defect formation at the high-electric-field region of the gate contact. RF signals, however, allow for other physical phenomena to take place before the said defect formation. Electron injection on the gate–drain region decreases the electric field value, thus counteracting the electric-field-induced defect formation at the gate edge. [ABSTRACT FROM PUBLISHER]

In this paper, an extensive description of the main characteristics and possible applications of a double-halo metal–oxide–semiconductor (MOS) device is presented. In particular, the details concerning the prototype fabrication through a standard complementary MOS (CMOS) process and the obtained experimental results are reported. Extensive numerical device simulation has been carried out in order to deeply understand the new structure. Furthermore, to gain insight on the device behavior, an electrical model to be used in SPICE-like circuit simulation tools has been developed and verified. As shown by our analysis, digital integrated circuits employing the new technology introduce, with respect to standard CMOS ones, a drastic reduction of both the device number and the parasitic capacitances, leading to a significant improvement of the circuit performance. [ABSTRACT FROM AUTHOR]

This paper presents a fast methodology for the investigation of trapping and hot-electron effects in GaN-based high-electron mobility transistors (HEMTs). The presented method is based on pulsed ID–VG measurements and electroluminescence characterization and provides a rapid and effective evaluation of the following: 1) the presence of traps in the region under the gate; 2) trapping phenomena occurring in the gate–drain access region; 3) the role of traps in limiting the maximum gate–drain electric field and the equivalent electron temperature. The method is validated by means of a split-wafer experiment carried out on GaN-based HEMTs with different gate materials with and without passivation. [ABSTRACT FROM PUBLISHER]

The effects of direct-current (DC) stress on GaN high-electron-mobility transistors (HEMTs) are investigated by means of numerical simulations, by which the creation of an acceptor trap in the AlGaN barrier layer was correlated to the observed experimental degradation. An increase in the trap concentration induces a worsening of the saturated current I, transconductance g, and output conductance g. An increase in the length of the trapping region induces a degradation of I and g, but can reduce g. Analysis of scattering parameters in the saturation region shows that the cutoff frequency f matches the trend of g. [ABSTRACT FROM AUTHOR]

High-electric-field degradation phenomena are investigated in GaN-capped AIGaN/GaN HEMTs by comparing experimental data with numerical device simulations. Under power- and OFF-state conditions, 150-h DC stresses were carried out. Degradation effects characterizing both stress experiments were as follows: a drop in the dc drain current, the amplification of gate-lag effects, and a decrease in the reverse gate leakage current. Numerical simulations indicate that the simultaneous generation of surface (and/or barrier) and buffer traps can account for all of the aforementioned degradation modes. Experiments also showed that the power-state stress induced a drop in the transconductance at high gate—source voltages only, whereas the OFF-state stress led to a uniform transconductance drop over the entire gate—source-voltage range. This behavior can be reproduced by simulations provided that, under the power-state stress, traps are assumed to accumulate over a wide region extending laterally from the gate edge toward the drain contact, whereas, under the OFF-state stress, trap generation is supposed to take place in a narrower portion of the drain-access region close to the gate edge and to be accompanied by a significant degradation of the channel transport parameters. [ABSTRACT FROM AUTHOR]

Long-term ON-state and OFF-state high-electric-field stress results are presented for unpassivated GaN/AlGaN/GaN high-electron-mobility transistors on SiC substrates. Because of the thin GaN cap layer, devices show minimal current-collapse effects prior to high-electric-field stress, despite the fact that they are not passivated. This comes at the price of a relatively high gate-leakage current. Under the assumption that donor-like electron traps are present within the GaN cap, two-dimensional numerical device simulations provide an explanation for the influence of the GaN cap layer on current collapse and for the correlation between the latter and the gate-leakage current. Both ON-state and OFF-state stresses produce simultaneous current-collapse increase and gate-leakage-current decrease, which can be interpreted to be the result of gate-drain surface degradation and reduced gate electron injection. This study shows that although the thin GaN cap layer is effective in suppressing surface-related dispersion effects in virgin devices, it does not, per se, protect the device from high-electric-field degradation, and it should, to this aim, be adopted in conjunction with other technological solutions like surface passivation, prepassivation surface treatments, and/or field-plate gate. [ABSTRACT FROM AUTHOR]

An extensive characterization of the on-state breakdown characteristics of GaAs based MESFETs and HEMTs has been carried out by means of dc and pulsed measurements and of circuit simulations. A computer-controlled, three-terminals Transmission Line Pulse (TLP) system with 50-100 ns pulse width and sub-ns risetime has been developed, which allows automated pulsed measurements of device I-V characteristics. The TLP system has been adopted for nondestructive measurements of the on-state breakdown characteristics of GaAs MESFETs and HEMTs up to unprecedented values of gate current density (I[sub G]/W = 30 mA/mm has been reached), in strong avalanche conditions. The device behavior in strong avalanche conditions is dominated by a parasitic bipolar effect (PBE) similarly to SOI and bulk Si MOSFETs. By taking into account this and other parasitic effects, an equivalent circuit model, suitable for SPICE simulations has been developed. The proposed model is capable of predicting the exact behavior of the gate and drain currents in both weak and strong avalanche conditions. [ABSTRACT FROM AUTHOR]

This paper reviews most recent results concerning reliability of InP-based and metamorphic high electron mobility transistors (HEMTs). Thanks to research work carried out in the last 10 years, a deeper understanding of failure mechanisms of these devices has been achieved, and process and technology solutions have been found for the control of premature breakdown (related to the reduced energy gap of InGaAs) and of parasitic effects, such as “kink” effects, and transconductance frequency dispersion. After a brief description of impact-ionization effects in InGaAs, an analysis of failure modes and mechanisms of InP and metamorphic HEMTs is carried out, including hot-carrier-induced degradation, gate sinking and Schottky/ohmic contact interdiffusion, hydrogen effects, and donor compensation due to fluorine atoms indiffusion. Results show that reliability of these devices is continuously improving, opening the way for applications in microwave and millimeter-wave systems. [Copyright &y& Elsevier]

Analyzes carrier transport phenomena occuring in pseudomorphic AlGaAs/InGaAs high electronic mobility transistor (HEMT). Significance of hot-electron phenomena in the design power of AlGaAs/InGaAs pseudomorphic HEMT; Development of techniques to improve hot-electron characteristics and breakdown voltage of HEMT; Sample description and experimental apparatus; Electrical measurements.

Presents information on a study which focused on the on-state and off-state breakdown of GaInAs/InP composite-channel high electron mobility transistors. Device structure and performance; On-state and off-state breakdown characteristics; Discussion of the results; Conclusions.

Pulse behavior of insulated-gate double-field-plate power AlGaN/GaN HEMTs with C-doped buffers showing small current-collapse effects and dynamic RDS,on increase can accurately be reproduced by numerical device simulations that assume the CN\-CGa autocompensation model as carbon doping mechanism. Current-collapse effects much larger than experimentally observed are instead predicted by simulations if C doping is accounted by dominant acceptor states. This suggests that buffer growth conditions favoring CN\-CGa autocompensation can allow for the fabrication of power AlGaN/GaN HEMTs with reduced current-collapse effects. The drain-source capacitance of these devices is found to be a sensitive function of the C doping model, suggesting that its monitoring can be adopted as a fast technique to assess buffer compensation properties. [ABSTRACT FROM AUTHOR]

This paper reports on an extensive analysis of the degradation of AlGaN/GaN high electron mobility transistors (HEMTs) submitted to on-state and off-state stresses. The results of this study indicate that: (i) the analyzed devices do not show any degradation when submitted to off-state stress tests up to 100 V; (ii) during on-state stress, devices show a significant decrease in drain current and in the electroluminescence (EL) signal; (iii) degradation rate is strongly dependent on the intensity of the EL signal measured during stress on the devices, which is related to the concentration of hot electrons in the channel. Based on the experimental evidence collected within this paper, the on-state degradation of HEMTs is ascribed to the trapping of negative charge in the gate-drain access region, triggered by hot electrons. By considering the intensity of the EL signal as a measure of the stress acceleration factor, we have derived an acceleration law for the hot-electron induced degradation. [ABSTRACT FROM AUTHOR]

A multifunctional field-effect transistor (FET) for the manufacturing of high-density integrated circuits (ICs) has been developed and fabricated. Furthermore, an extensive numerical device simulation campaign has been carried out in order to characterize the new structure. Such device is a metal–oxide–semiconductor (MOS) FET that simultaneously performs the functions of two traditional FETs (an n-channel MOS and a p-channel MOS), working as one or as the other according to the voltage applied to the gate's terminal. Combinational and sequential circuits employing the new technology introduce, with respect to the standard complementary MOS (CMOS) ones, a drastic reduction of both the required device number and the parasitic capacitances. This leads to a significant increase in the circuit's speed. Furthermore, the ICs obtained with these transistors are fully compatible with the standard CMOS technology and fabrication process. [ABSTRACT FROM PUBLISHER]

In this letter, the effects of dc stress on GaN high-electron-mobility transistors' performance are investigated by means of experimental measurements and numerical simulation. A degradation of both dynamic (pulsed I-V) and static characteristics (dc) has been observed on stressed devices, and it has been experimentally related to the formation of an electron trap in the AIGaN barrier layer. Numerical simulations carried out on the tested structure by introducing a trapping region at the gate edge of the device barrier confirm the experimentally observed device degradation. The worsening of the dynamic performance is induced by both an increase in trap concentration and/or depth of the trapping region while the degradation of the dc characteristics can be explained by an increase in the trapping-region depth. [ABSTRACT FROM AUTHOR]

An anomalous kink effect has been observed in the room-temperature drain current ID versus drain voltage VDS characteristics of GaN high electron mobility transistors. The kink is originated by a buildup (at low VDS) and subsequent release (at high VDS) of negative charge, resulting in a shift of pinch-off voltage VP toward more negative voltages and in a sudden increase in ID. The kink is characterized by extremely long negative charge buildup times and by a nonmonotonic behavior as a function of photon energy under illumination. The presence of traps in the GaN buffer may explain both spectrally resolved photostimulation data and the slow negative charge buildup. [ABSTRACT FROM AUTHOR]

We investigated the origin of vertical leakage and breakdown in GaN-on-Si epitaxial structures. In order to understand the role of the nucleation layer, AlGaN buffer, and C-doped GaN, we designed a sequential growth experiment. Specifically, we analyzed three different structures grown on silicon substrates: AlN/Si, AlGaN/AlN/Si, C:GaN/AlGaN/AlN/Si. The results demonstrate that: (i) the AlN layer grown on silicon has a breakdown field of 3.25 MV/cm, which further decreases with temperature. This value is much lower than that of highly-crystalline AlN, and the difference can be ascribed to the high density of vertical leakage paths like V-pits or threading dislocations. (ii) the AlN/Si structures show negative charge trapping, due to the injection of electrons from silicon to deep traps in AlN. (iii) adding AlGaN on top of AlN significantly reduces the defect density, thus resulting in a more uniform sample-to-sample leakage. (iv) a substantial increase in breakdown voltage is obtained only in the C:GaN/AlGaN/AlN/Si structure, that allows it to reach VBD > 800 V. (v) remarkably, during a vertical I–V sweep, the C:GaN/AlGaN/AlN/Si stack shows evidence for positive charge trapping. Holes from C:GaN are trapped at the GaN/AlGaN interface, thus bringing a positive charge storage in the buffer. For the first time, the results summarized in this paper clarify the contribution of each buffer layer to vertical leakage and breakdown. [ABSTRACT FROM AUTHOR]

Extended abstract of a paper presented at Microscopy and Microanalysis 2010 in Portland, Oregon, USA, August 1 – August 5, 2010. [ABSTRACT FROM PUBLISHER]

We investigate the degradation of AlGaN/GaN MIS-HEMTs submitted to gate step-stress experiments, and demonstrate the existence of field- and hot-electron induced processes. When the devices are submitted to gate-step stress with high V DS > 50 V, four different regimes are identified: (i) for V GS < − 10 V, no significant degradation is observed, since the devices are in the off-state; (ii) for − 10 V < V GS < 0 V, hot electrons flow through the channel, as demonstrated by the (measurable) electroluminescence signal. These hot electrons can be trapped within device structure, inducing an increase in the threshold voltage. (iii) for V GS > 0 V, the density of hot electrons is significantly reduced, due to the increased interface scattering and device temperature. As a consequence, EL signal drops to zero, and the electrons trapped during phase (ii) are de-trapped back to the channel, where they are attracted by the high 2DEG potential. (iv) Finally, for V GS > 5 V, a significant increase in threshold voltage is detected. This effect is observed only for high positive voltages, i.e. when a significant leakage current flows through the gate. Such gradual degradation is ascribed to the injection of electrons from the 2DEG to the gate insulator, which is a field-driven effect. These results were obtained by combined electrical and optical characterization carried out at different voltages during the step stress. [ABSTRACT FROM AUTHOR]

This paper investigates the robustness of normally-off High Electron Mobility Transistors (HEMTs) with p-GaN gate submitted to forward gate bias overstress. By means of combined DC and spectral analysis we demonstrate the following results: (i) the devices demonstrate a time-dependent failure mechanism; (ii) time to failure (TTF) can be described by a Weibull distribution with a shape factor higher than 1, suggesting a wear-out failure; (iii) the devices have an estimated 20-years lifetime for a gate voltage of 7.2 V; (iv) TTF is temperature-dependent, with an activation energy of 0.5 eV; (v) emission microscopy reveals the presence of hot spots, whose emission originates from yellow luminescence and/or hot electron radiation. [ABSTRACT FROM AUTHOR]