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All electronic devices when used in a radiation environment undergo significant changes in their electrical properties. It is interesting to explore the effects of radiation, not only on conventional MOSFET devices but also on novel devices like FinFET, Tunneling Field Effect Transistor (TFET), and Junctionless Field Effect Transistor (JLFET). This study presents a systematic review of radiation studies on TFET and JLFET-based devices/circuits. TFET and JLFET have gained popularity in recent days due to their wide use in ultra-scaled designs than conventional CMOS. The effect of radiation on a divergent range of TFET and JLFET devices and circuits is explored. The variations in DC characteristics and electrical parameters under the influence of radiation strikes are analyzed in detail. The radiation effects like Total Ionizing Dose (TID), and Single Event Upset (SEU) are noted for these devices/circuits. The radiation study on different devices shows that these devices are sensitive to Single Event Effect (SEE), steeper Subthreshold Swing (SS), increase in Electron Hole Pair (EHP) production, increase in drain current (ID), and increase in collected charge (QC), decrease in bipolar gain and trans-conductance. [ABSTRACT FROM AUTHOR]

• Reliability aspect of the SFP-MISHEMT under the linearity and SEU environment have been demonstrated. • Temperature related degradation has also been explored and the results have been investigated with varying device parameters. • Compared to conventional MISHEMT, SFP-MISHEMT shows better linearity in terms of higher VIP 2 , IIP 3 and lower intermodulation distortion. • The influence of process variability has also been studied. • Improved reliability in terms of the lesser SEU generated effects has been observed from the SFP-MISHEMT. In this work, the reliability of Slant Field Plate SFP-MISHEMT has been discussed using linearity and Single Event Upset parameters for millimeter wave (mmW) applications in outer space environment. The influence of process variability on the RF and linearity parameters of SFP-MISHEMT like g m ' and g m ", higher VIP 2 , IIP 3 and IMD 3 has also been explored. For analyzing the SEU behavior, three different positions of the ion strike have been used and the investigation has been conducted with varying energy and device parameters like temperature. The impact of the gate to drain length (L gd) and oxide permittivity and gate length (varied from 60 nm to 210 nm keeping the length of the SFP constant as 20 nm (on both side)) on the device sensitivity has also been explored. Improved reliability in terms of the lesser SEU generated effects has also been observed from the SFP-MISHEMT in contrast with C-MISHEMT. [ABSTRACT FROM AUTHOR]

In radiation tests on SRAMs or field-programmable gate arrays (FPGAs), two or more independent bitflips can be misled with a multiple event if they accidentally occur in neighbor cells. In the past, different tests, such as the “birthday statistics,” have been proposed to estimate the accuracy of the experimental results. In this article, simple formulas are proposed to determine the expected number of false 2- and 3-bit multiple cell upsets (MCUs) from the number of bitflips, memory size, and the method used to search multiple events. These expressions are validated using the Monte Carlo simulations and experimental data, and a technique is proposed to refine the experimental data and thus partially removing possible false events. Finally, it is demonstrated that there is a physical limit to determine the cross section of memories with arbitrary accuracy from a single experiment. [ABSTRACT FROM AUTHOR]

This article proposes a method using electron and proton Single Event Upset sensitivities of a device to deduce all simulation parameters related to an RPP approach. It is shown that for 45-nm double data rate (DDR) memory, the RPP approach is still relevant and the crossing of proton and electron data makes it possible to constrain and properly define the associated parameters. Heavy ion prediction is also presented. [ABSTRACT FROM AUTHOR]

FPGAs (Field-Programmable Gate Array) and FPGA-based SoCs (System-on-chip) are electronic devices which offer high computational performance and low time-to-market for low and medium production volumes. They are gaining popularity in critical sectors, such as automotive, aerospace, avionics and railway, making their reliability evaluation mandatory. FPGAs are notoriously sensitive to SEUs (Single Event Upsets), which are random memory errors provoked by radiation particles. The failure rate of an FPGA varies with the implemented design, depending on the amount of used resources and the implemented redundancy schemes among others. FPGA-based circuits are being used in complex safety-critical engineering systems that are designed in compliance with dependability regulations. This work presents an emulation-based methodology for estimating the failure rate of designs implemented in FPGA SoCs, which is a key data in this scenario. [ABSTRACT FROM AUTHOR]

Radiation has been a traditional concern in microelectronic devices used in space applications, causing high probability of single event upsets (SEUs). SEUs induced by particle radiation are becoming an increasingly important threat to the reliability of memories. Moreover, recent studies reveals that single event multiple-node upsets (SEMNUs) is the prime effect of radiation in SRAM chips fabricated in nanoscale CMOS technologies. In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed in this paper to address the issues related to SEUs and SEMNUs. Hardness against radiation of the proposed bit-cell is compared with the recently reported radiation hardened bit-cells and popular SRAM bit-cell (6T). Radiation and its effect in the bit-cells under consideration are simulated with the help of 3-D Technology Computer Aided Design (TCAD) and Visual Particle (VP) tools. Radiation hardening capability of RHD14 over the existing and conventional bit-cells is demonstrated focusing on linear energy transfer (LET) threshold and recovery time. It is observed that the proposed radiation hardened cell needs lesser silicon area and performs better in terms of power dissipation. Other performance metrics like read delay, write delay are also evaluated in order to study ensuing trade-off. • In view of the weaknesses of the existing radiation hardened bit-cell configurations, a highly reliable radiation hardened by design (RHD14) bit-cell is proposed to address the issue related to SEUs and SEMNUs. • Considering radiation hardness ability and the overall performance, RHD14 bit-cell has a better composite indicator compared to recently proposed radiation-hardened (RHM [12]) and popular (6T) SRAM bit-cell. • RHD14 bit-cell offers 6.08 % smaller read delay compared to RHM bit-cell. The static power dissipation of RHM and RHD14 bit-cells are comparable. • This indicates that the proposed bit-cell offers better hardness against radiation compared to other bit-cells without any penalty in the overall performance. [ABSTRACT FROM AUTHOR]

A guard-gate based flip-flop circuit temporally hardened against single-event effects is presented in this paper. Compared to several existed techniques, the organization of components inside the proposed design allows the improved performance– only one $\tau $ (the maximum width of a single-event transient (SET) to tolerate) is added into the setup time. A previously reported low-power delay element is applied, which helps make the proposed design power-efficient. The proposed design was implemented in a 65 nm CMOS bulk technology. Alpha and heavy-ions radiation experiments were performed to characterize its soft-error rates. Experimental results show that the proposed design presents no error with LETs up to 37.3 MeV-cm2/mg. Simulation results from the TFIT further validate the experimental results. [ABSTRACT FROM AUTHOR]

With shrinking dimensions and increased number of on-chip transistors radiation can provoke faults in integrated circuits even at sea level. This paper presents a comparison of fully depleted SOI (FDSOI) and Bulk CMOS 6T SRAM cells' resilience to radiation effects. Both cells were simulated using TCAD tools, considering heavy-ion impacts in different locations of the transistor as well as using different impact angles. Two types of radiation effects have been considered: Single-Event Transients (SETs) and Single-Event Upsets (SEUs). The minimum critical collected charge (CC) to flip a cell is almost the same in both technologies. However, it is shown that a FDSOI SRAM cell needs a heavy-ion impact with a Linear Energy Transfer (LET) around 10 times greater than a Bulk-CMOS SRAM cell, to generate a similar CC and to flip a cell. [ABSTRACT FROM AUTHOR]

CMOS downscaling makes advanced memory and computing systems more vulnerable to radiation. Emerging non-volatile memories such as Magnetic RAM (MRAM) are under development to replace SRAM and FLASH memories. Spin Transfer Torque Magnetic Memory (STT-MRAM) is considered as one of the most promising memories for high reliability applications. This is due to its intrinsic hardness to radiation, as storage is based on the spin direction of electrons instead of the charge. Its peripheral CMOS circuits are sensitive to radiation; however we can recharge frequently the non-volatile storage to get correct data. Different from conventional MRAM based on magnetic field switching, STT-MRAM is unable to be used directly for hard radiation applications as the current pulses induced by radiation may change the storage due to the stochastic behaviors of spin transfer torque mechanism. In this paper, we analyze firstly this issue and propose a rad-hard design for STT-MRAM sensing circuit with low area overhead and negligible performance degradation. Both transient and Monte-Carlo simulation have been performed to demonstrate its performance and behaviors. [ABSTRACT FROM PUBLISHER]

Given their high computational power, General Purpose Graphics Processing Units (GPGPUs) are increasingly adopted: GPGPUs have begun to be preferred to CPUs for several computationally intensive applications, not necessarily related to computer graphics. However, their sensitivity to radiation still requires to be fully evaluated. In this context, GPGPU data caches and shared memory have a key role since they allow to increase performance by sharing data between the parallel resources of a GPGPU and minimizing the memory accesses overhead. In this paper we present three new algorithms designed to support radiation experiments aimed at evaluating the radiation sensitivity of GPGPU data caches and shared memory. We also report the cross-section and Failure In Time results from neutron testing experiments performed on a commercial-off-the-shelf GPGPU using the proposed algorithms, with particular emphasis on the shared memory and on the L1 and L2 data caches. [ABSTRACT FROM AUTHOR]

This paper proposes a highly reliable radiation-tolerant 13T (HRRT 13T) SRAM cell for deep-space applications. The proposed SRAM cell design can effectively tolerate radiation events. The design metrics of the proposed SRAM cell are compared with conventionally used SRAM cells like QUCCE 10T, QUCCE 12T and standard 6T SRAM cells. The proposed SRAM cell consumes 9.4% and 14% lesser hold power (H PWR) compared to QUCCE 10T and QUCCE 12T SRAM cells, respectively. The proposed SRAM cell exhibits 12.7%, 3.63% and 11.7% shorter read access time (T RA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at a nominal supply voltage (V DD) of 0.7 V. The proposed HRRT 13T SRAM cell exhibits higher read stability compared to other conventionally used SRAM cells. This has been validated by 2.92×, 2.33× and 2.06× higher read static noise margin (RSNM) exhibited by the proposed cell compared to the 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at V DD = 0.7 V. The proposed SRAM cell exhibits high radiation tolerance capability compared to the conventionally used SRAM cells. This has been proved by 94.1%, 17.8% and 10.0% higher critical charge (Q C) of the proposed cell compared to 6T, QUCCE 10T and QUCCE 12T SRAM cells, respectively at V DD = 0.7 V. The proposed cell achieves all these improvements at the expense of 1.05×, 1.38× and 1.36× longer write delay (T WA) compared to QUCCE 10T, QUCCE 12T and 6T SRAM cells, respectively at V DD = 0.7 V. Extensive simulations on SPICE using 16-nm CMOS technology are performed to validate the theoretical design of the proposed SRAM cell. • This paper proposes a highly reliable radiation-hardened 13T SRAM Cell. • The proposed cell employs a differential read technique to provide a shorter read access time. • It exhibits higher Read Static Noise Margin (RSNM), which makes it read upset tolerant. • It achieves 17.8% improvement in Critical Charge, which proves its robustness against radiation hazard. [ABSTRACT FROM AUTHOR]

SEUs in the configuration memory are the major cause of faults in SRAM-based FPGAs exposed to radiation. Most of the research about this topic focuses on studying the mechanism of random changes in the FPGA resources (logic blocks, flip-flops, IO, and interconnection network) for their impact on the overall device reliability and fault analysis, while much less effort has been spent in evaluating the effects of SEUs on power consumption. In this paper, we present a detailed analysis of the power consumption of a Xilinx Virtex 5 LX50T on the CORE, AUX, MGT and IO domains during irradiation with 62-MeV proton beams. The tests have been performed at the Superconductive Cyclotron of the LNS-INFN facility (Catania, Italy). Changes in power consumption (most notably in the logic core) are experienced. We present an analysis of the current trends and the results of fault injection tests, on the programmable routing resources, aimed at confirming or excluding possible fault mechanisms for the SEU-induced current variations. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new circuit level hardening techniques that can decrease the sensitivity of Static Random Access Memory (SRAM) cells to radiation induced Single Event Upsets (SEUs). Five different types of 32 nm double gate (DG)-FinFET-based SRAM cells are analyzed. Proposed SRAM cell outperforms over the unhardened SRAM when exposed to radiation. This is primarily due to the modification of the source potential used to reduce the effect of SEU without affecting normal operation. Static Noise Margin (SNM), Read Noise Margin (RNM), Write Noise Margin (WNM) and Power Delay Product (PDP) are the performance metrics computed for each type of SRAM cell. Effect of back gate voltage and back gate oxide thickness variation on device characteristic show detrimental effects on radiation hardened capabilities of a device. Benchmarking is done against DICE latch and it is found that as compared to DICE latch proposed DG-FinFET SRAM has low transistor count, less area, low recovery time and fault tolerance to internal as well as external nodes. [ABSTRACT FROM AUTHOR]

The thermal neutron SEU cross-section of the Toshiba SRAM memory used in the LHC RadMon system was measured at different voltages. A method using the difference in its response compared to mixed particle energy field is proposed to be used as a discriminator between thermal neutron and high-energy hadron fluences. For test purposes, the proposed method was used at the CNGS and CERF facilities to estimate the field composition by counting SEUs at two different voltages and the results were compared to simulations. [ABSTRACT FROM AUTHOR]

We investigate, for the first time, the potential for SEE mitigation of a newly-developed device architecture in a 3rd generation high-speed SiGe platform. This new device architecture is termed the "inverse-mode cascode SiGe HBT" and is comprised of two standard devices sharing a buried subcollector and operated in a cascode configuration. Verification of the TID immunity is demonstrated using 10 keV X-rays, while an investigation of the SEE susceptibility is performed using a 36 MeV16O ion. IBICC results show strong sensitivities to device bias with only marginal improvement when compared to a standard device; however, by providing a conductive path from the buried subcollector (C-Tap) to a voltage potential, almost all collected charge is induced on the C-Tap terminal instead of the collector terminal. These results are confirmed using full 3-D TCAD simulations which also provides insight into the physics of this new RHBD device architecture. The implications of biasing the C-Tap terminal in a circuit context are also addressed. [ABSTRACT FROM AUTHOR]

Monte-Carlo radiation transport code is coupled with SPICE circuit level simulation to identify regions of single event upset vulnerability in an SEU hardened flip-flop, as well as predict single event upset cross sections and on-orbit soft error rates under static and dynamic operating conditions. [ABSTRACT FROM PUBLISHER]

Abstract: The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today''s FPGAs to operate. The Single Event Upset rate, however, lies between 14min and 12h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector. [Copyright &y& Elsevier]

The neutron-induced SEU sensitivity in the 1-10 MeV energy range is investigated using monoenergetic neutron beams at 2.5, 4, 6, and 14 MeV. Below the 0.25 µm technology node, bulk technologies exhibit a relatively high sensitivity to neutrons between 4 and 6 MeV which is explained by the contribution of alpha particles coming from (n, a) reactions. In the terrestrial environment, the contribution to SER of neutrons in this energy range exceeds 10%. [ABSTRACT FROM AUTHOR]

With growing interest in the use of SRAM-based FPGAs in space and other radiation environments, there is a greater need for efficient and effective fault-tolerant design techniques specific to FPGAs. Triple-modular redundancy (TMR) is a common fault mitigation technique for FPGAs and has been successfully demonstrated by several organizations. This technique, however, requires significant hardware resources. This paper evaluates three additional mitigation techniques and compares them to TMR. These include quadded logic, state machine encoding, and temporal redundancy, all well-known techniques in custom circuit technologies. Each of these techniques are compared to TMR in both area cost and fault tolerance. The results from this paper suggest that none of these techniques provides greater reliability and often require more resources than TMR. [ABSTRACT FROM AUTHOR]

The appearance of nanometer technologies has produced a significant increase of integrated circuit sensitivity to radiation, making the occurrence of soft errors much more frequent, not only in applications working in harsh environments, like aerospace circuits, but also for applications working at the earth surface. Therefore, hardened circuits are currently demanded in many applications where fault tolerance was not a concern in the very near past. To this purpose, efficient hardness evaluation solutions are required to deal with the increasing size and complexity of modern VLSI circuits. In this paper, a very fast and cost effective solution for SEU sensitivity evaluation is presented. The proposed approach uses FPGA emulation in an autonomous manner to fully exploit the FPGA emulation speed. Three different techniques to implement it are proposed and analyzed. Experimental results show that the proposed Autonomous Emulation approach can reach execution rates higher than one million faults per second, providing a performance improvement of two orders of magnitude with respect to previous approaches. These rates give way to consider very large fault injection campaigns that were not possible in the past. [ABSTRACT FROM AUTHOR]

A simple methodology is necessary to characterize the SEU behavior of large quantities of RAM cell types, latches, flip-flops, other logic cells, I/O cells, etc. Such a methodology, called ‘Boxes’, is being used for the Honeywell S150 radiation-hard 0.15 μm partially-depleted SOI process. Using physics-based equations, this paper shows how to break up each critical transistor into several ‘boxes’, each with its own dimensions and critical charge, for the purpose of calculating soft error rate (SER). The Boxes methodology also allows for calculation of SER due to an ion that must simultaneously strike two separated sensitive volumes in order to cause an upset. This can be the dominant upset mechanism for many types of cells such as certain hardened SRAM's and other cells that obtain radiation hardness via extra transistors (such as triple modular redundancy, the DICE latch, etc.). Boxes also predicts upsets that can occur when an ion strike pulls a circuit node below ground or above the positive power supply. The boxes methodology was applied to a 6 T non-hardened SRAM, a hardened SRAM, and a D-type flip-flop. The theoretical predictions correlated well with experimental vertical ion strike data. [ABSTRACT FROM AUTHOR]

This paper presents a new way of investigation using the laser method. It is based on laser threshold mappings of electronic devices. The main idea is to use these mappings in order to extract physical parameters, for instance sizes and shapes of the different sensitive areas of a component. These parameters can be used as input parameters for analytical or Monte Carlo calculation codes in order to predict the behavior of sensitive components towards radiations. [ABSTRACT FROM AUTHOR]

The SEU sensitivity of 0.2 μm fully depleted silicon on ensulator (FD-SOI) devices to proton and neutron irradiations is investigated in a large energy range (14-500 MeV). The comparison to bulk devices with similar gate lengths shows an improvement of a factor of 50 with the presence of body ties. Monte Carlo simulations were performed to confirm that the low sensitivity of FD-SOI is mainly due to the reduced sensitive volume. These results were extrapolated to deca-nanometric technologies to predict the behavior of advanced SOI processes. We found that fully depleted devices will be far less sensitive than partially depleted technologies to the terrestrial radiative environment. [ABSTRACT FROM AUTHOR]

Abstract: The results of proton irradiation test of electronic devices, selected for the RPC trigger electronic system of the CMS detector, will be presented. For Xilinx Spartan-IIE FPGA the cross-section for Single Event Upsets (SEUs) in configuration bits was measured. The dynamic SEUs in flip-flops were also investigated, but not observed. For the FLASH memories no single upsets were detected. Only after irradiating with a huge dose permanent damages of devices were observed. For Synchronous Dynamic Random Access Memory (SDRAM), the SEU cross-section was measured. [Copyright &y& Elsevier]

The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 μm deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS. [Copyright &y& Elsevier]