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In this work, the electrostatic discharge (ESD) reliability of the OFF- and ON-state NMOS field-effect transistors in a bulk FinFET technology are investigated. The impacts of source and drain epitaxy influenced by the gate pitch (GP) and the gate length (${L}_{g}$) are studied. In the OFF-state NMOSFET, which is known as grounded-gate NMOS (ggNMOS), the large GP introduces nonuniform epitaxy on source and drain, which cause high power density localization in device. The large ${L}_{g}$ effectively helps the ESD performance of ggNMOS in ways of better turn-on and contact current uniformity. The ON-state NMOSFET as an active power-rail clamp is also studied in 3-D TCAD simulations. The device shows little difference to transient responses, while the clamping voltage can be different with ${L}_{g}$ and GPs. With the same gate space, the short ${L}_{g}$ device has a lower clamping voltage and ON-resistance, which reduces oxide breakdown risk and achieves better ESD performance. [ABSTRACT FROM AUTHOR]

Sequential 3-D stacking of multiple CMOS device tiers in a single fabrication flow requires the development of reliable high- ${k}$ /metal gate (HKMG) stacks at a reduced thermal budget (<525 °C). The omission of the customary high-temperature gate-stack annealing results in excessive dielectric defect densities. We have recently demonstrated on MOS capacitors the insertion of “defect decoupling” layers–LaSiOx for nMOS and Al2O3 for pMOS–at the interface between SiO2 and HfO2 as a promising approach to engineer the high- ${k}$ band lineup and minimize charge trapping for improved bias-temperature-instability (BTI) reliability. In this article, we demonstrate this approach in planar transistors, which allows assessing the impact of defect decoupling on carrier mobility. First, a comparative study on the impact of LaSiOx and Al2O3 insertion is performed, highlighting the different strategies for improving positive BTI (PBTI) and negative BTI (NBTI) reliability. Second, a comprehensive investigation on the effects of LaSiOx and Al2O3 insertion is conducted with a focus on BTI reliability and channel carrier mobility: a lack of penalty (Al2O3) or even improved carrier mobility (LaSiOx) is reported for the dipole-inserted gate stacks. Furthermore, we explore the simplified dual gate-stack integration for CMOS flow. A severe PBTI reliability penalty is observed if an Al2O3 layer (for hole trap decoupling) is deposited in the nMOS gate-stack, even if on top of the beneficial LaSiOx (for electron trap decoupling). In contrast, the pMOS gate-stack is found to be more tolerant to the presence of a residual LaSiOx layer on top of the beneficial Al2O3 layer, suggesting a viable strategy for the simplified dual gate-stack integration. Finally, the reliability improvement is validated also on a FinFET test vehicle. [ABSTRACT FROM AUTHOR]

A comprehensive investigation on the hot-carrier-induced interface state generation and its impact on carrier mobility in nMOSFET is performed. I – V compact modeling and charge pumping (CP) characterization are used as independent ways to evaluate the interface state density as a function of hot-carrier-induced aging. From the two techniques, similar power-law time exponents of the interface state density kinetics are obtained. Assisted by the quasi-spectroscopic (temperature-resolved) CP measurement, the extracted interface state density is further correlated with the I – V modeling results: an universal mobility degradation normalization parameter Nit,ref = ~ 4.1 × 1011/cm2 is reported, irrespective of the effective oxide thickness (EOT), stress temperature, or the relative degradation of the device under test (DUT). Supported by the fundamental principles deployed in the derivation and the broad range of experimental conditions considered for its validation, the reported normalization parameter could serve as a modeling constant in the commonly used I – V compact models to correlate the mobility degradation with the interface state density induced by hot carrier stress. [ABSTRACT FROM AUTHOR]

Synchronous buck converter comprises a low side (LS) and a high side (HS) switch, where the HS switch works in the first quadrant (forward conduction) whereas the LS switch works in the third quadrant (reverse conduction). However, the reliability of the p-GaN gate high electron mobility transistor (HEMT) in reverse conduction is unclear. In this work, a comprehensive evaluation of this conduction mode for 200-V HEMTs was conducted. First, devices were subjected to time-dependent breakdown (TDB) measurements. By comparing different device configurations, the time to failure (TTF) was found to only scale with the number of gate fingers instead of the gate width WG, proving the critical spots are the intersection of gate fingers over the N implantation isolation. The reverse operation voltage of VDS for ten years lifetime was extrapolated to be −5.4 V, corresponding to a failure of 0.01% and 100 gate fingers. Second, the devices were submitted to 200-V VDS OFF-state stress for 10 s, after which the reverse drain current saw a negligible degradation. Third, the reverse conduction of the HEMTs only showed a very limited deterioration after a long-time bias temperature instability (BTI) stress at VDS = - 5.5 V and VGS = 0 V. This work proves the p-GaN gate HEMTs bear a high reliability in reverse conduction, which can simplify the design of synchronous power system. [ABSTRACT FROM AUTHOR]

Low thermal budget junction-less transistors with back-gate are fabricated as top-tier devices for 3-D sequential integration. The impact of back-gate bias on carrier mobility and bias temperature instability (BTI) reliability is investigated. The back-gate bias is shown to modulate the carrier mobility: specifically, mobility is increased under forward back-gate bias (FBB), which is ascribed to the carrier redistribution from the front-gate interface toward back-gate interface. Regarding BTI reliability, if a back-gate bias (VBG) is applied only during ON-state and a constant front-gate stress VG is used, BTI reliability is not influenced by the applied VBG (due to its negligible impact on the front-gate oxide field, Eox). Therefore, supplying an FBB during ON-state can be used to adjust device performance—as VBG modulates the channel current through Vth and mobility—without reliability penalty. On the other hand, if the back-gate bias is applied during both ON- and OFF-states, while a constant stress Vov is maintained by adjusting the front-gate VG [i.e., VG – Vth (VBG) is kept constant under different VBG’s], the BTI reliability can be improved under FBB (due to a reduced Eox in the front-gate) without performance loss. The latter property can be used to improve the device reliability under circuit operation. [ABSTRACT FROM AUTHOR]

A comprehensive study on buffer vertical leakage mechanism and buffer reliability of 200-mm GaN-on-SOI is conducted in this paper. The buffer vertical leakage current versus bias is found to sequentially comprise three ranges of low-field leakage, variable-range hopping, and breakdown. The low-field leakage increase at high temperatures has been proven to be dominated by surface leakage. The stressing voltages of buffer time-dependent breakdown (TDB) measurements have a significant impact on shape factor $\beta $. Stress-induced leakage current is observed in the wear-out phase of the TDB curves. Stress-and-sense measurements in this phase indicate that defects are generated probably around the threading dislocations, where more localized Joule heating and more defects are created by a positive feedback, and finally, the buffer breaks down due to thermal runway. At last, based on the Weibull plot and E-model, the operating voltage is extrapolated to be 470 V corresponding to an expected lifetime of 10 years at 175 °C, with area scaling to the drain terminal of a 150-mm power transistor and failures scaling to 0.01%. The qualification of GaN-on-SOI is crucial for future 200-V GaN power integrated circuit on this platform. [ABSTRACT FROM AUTHOR]

Operating temperature has a significant imp-act on the reliability of metal–oxide–semiconductor field effect transistors (MOSFETs). In Si-channel MOSFETs, the effective density of charged oxide defects ($\Delta {N}_{\text {eff}}$) at operating condition typically shows an Arrhenius temperature dependence with ${E}_{\text {A}}$ ~ 0.1 eV. In contrast, apparent non-Arrhenius temperature dependence is reported here for InGaAs devices subjected to BTI stress in a wide range of temperature (77–373 K). This apparent non-Arrhenius temperature dependence is explained here by the presence of three distinct populations of electron traps. Capture–emission-time maps are derived from the experimental data, and are modeled by three bivariate distributions of energy barriers for the capture and emission processes. The total $\Delta {V}_{\text {th}}$ measured in bias-temperature-instability experiments reflects different contributions from the three defect populations, depending on the chosen temperature range, and on the measurement timing. We show that a correct description of the three defect distributions is crucial to properly assess their impact on the device performance. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) hafnium oxide is a promising candidate for memory applications. In this paper, endurance, imprint, and retention tests are carried out on FE aluminum-doped hafnium oxide thin films with different electrodes: 1) metal–insulator–metal (MIM) and 2) silicon–insulator–silicon(SIS). MIM devices exhibit higher endurance than SIS devices. However, SIS devices show superior imprint and retention, with an extrapolated retention time-to-failure larger than 10 years at 85 °C. These results are very promising to integrate FE-HfO2 in 3-D structures, either for dynamic random access memory or for NAND applications. [ABSTRACT FROM PUBLISHER]

Continuing CMOS performance scaling requires developing MOSFETs of high-mobility semiconductors and InGaAs is a strong candidate for n-channel. InGaAs MOSFETs, however, suffer from high densities of border traps, and their origin and impact on device characteristics are poorly understood at present. In this paper, the border traps in nMOSFETs with an In0.53Ga0.47As channel and Al2O3 gate oxide are investigated using the discharging-based energy profiling technique. By analyzing the trap energy distributions after charging under different gate biases, two types of border traps together with their energy distributions are identified. Their different dependences on temperature and charging time support that they have different physical origins. The impact of channel thickness on them is also discussed. Identifying and understanding these different types of border traps can assist in the future process optimization. Moreover, border trap study can yield crucial information for long-term reliability modeling and device time-to-failure projection. [ABSTRACT FROM AUTHOR]

This paper describes the implications of bias temperature instability (BTI)-induced time-dependent threshold voltage distributions on the performance and yield estimation of digital circuits. The statistical distributions encompassing both time-zero and time-dependent variability and their correlations are discussed. The impact of using normally distributed threshold voltages, imposed by state-of-the-art design approaches, is contrasted with our defect-centric approach. Extensive Monte Carlo simulation results are shown for static random access memory cell and ring oscillator structures. [ABSTRACT FROM PUBLISHER]

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with \N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high-k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG \sim VD/\2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis. [ABSTRACT FROM PUBLISHER]

In deeply scaled CMOS technology, time-dependent degradation mechanisms (TDDMs), such as Bias Temperature Instability (BTI), have threatened the transistor performance, hence the overall circuit/system reliability. Two well-known attempts to model BTI mechanism are the reaction-diffusion (R-D) model and the Atomistic trap-based model. This paper presents a thorough comparative analysis of the two models at the gate-level in order to explore when their predictions are the same and when not. The comparison is done by evaluating degradation trends in a set of CMOS logic gates (e.g., INV, NAND, NOR, etc.) while considering seven attributes: 1) gate type, 2) gate drive strength, 3) input frequency, 4) duty factor, 5) non-periodicity, 6) instant degradation versus long-term aging, and 7) simulation CPU time and memory usage. The simulation results show that two models are in consistency in terms of the gate degradation trends w.r.t. the first four attributes (gate type, input frequency, etc.). For the rest of the attributes, the workload-dependent solution of the Atomistic trap-based model is superior from the point of non-periodicity and instant degradation, while the R-D model gets advantageous in case of long-term aging, and simulation CPU time and memory usage due to its lite AC periodic and duty factor dependent solution. [ABSTRACT FROM PUBLISHER]

A methodology for the design of circuits robust to system-level electrostatic discharge (ESD) stress is presented and verified with two case studies. The combination of on-wafer characterization and transient simulations enables the ESD designer to study the behavior of the component-level ESD protection design during system-level ESD stress with and without adding off-chip protection devices. The design of a system-level ESD protection solution can be verified long before IC packaging and even before the final system is built. [ABSTRACT FROM PUBLISHER]

This paper presents an extensive statistical study on the impact of bias temperature instability (BTI) on digital circuits. A statistical framework for the evaluation of BTI at the electrical (SPICE) level, enhanced by an atomistic model for BTI, is introduced. This framework is then employed to perform the timing analysis of different combinational paths using cells from a given library, aiming to statistically model BTI at the higher abstraction level. A statistical static timing analysis (SSTA) method is then performed and the results are compared to detailed simulations using atomistic models based on experimental data. The comparison between the two methods shows that for large paths both methods converge to the same distribution for the delay while for short paths the delay distributions are different causing the SSTA method to generate misleading results. An analysis is then performed in order to understand and formalize the results. [ABSTRACT FROM AUTHOR]

Due to a significantly reduced negative-bias temperature instability (NBTI), (Si)Ge channel pMOSFETs are shown to offer sufficient reliability at ultrathin equivalent oxide thickness. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and a \SiO2/ \HfO2 dielectric stack is ascribed to a reduced availability of interface precursor defects and to a significantly reduced interaction of channel carriers with gate dielectric defects due to a favorable energy decoupling. Owing to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. The superior reliability is shown to be process and architecture independent by comparing both our results on a variety of Ge-based device families and published data of other groups. [ABSTRACT FROM PUBLISHER]

Positive charges (PCs) in gate dielectric shift the threshold voltage and cause a time-dependent device variability. To assess their impact on circuits, it is useful to know their distribution for a wide energy range both within and beyond silicon bandgap. Such a distribution is still missing, and a technique for its extraction has not been demonstrated yet. The central objective of this paper is, for the first time, to develop a new fast technique and to demonstrate its capability for probing the energy distribution of PCs over such a wide energy range. Results show that PCs can vary significantly with energy level. The PCs in different energy regions clearly originate from different defects. The PCs below the valence band edge are as-grown hole traps that are insensitive to stress time and temperature, and substantially higher in thermal SiON. The PCs above the valence-band edge are from created defects. The PCs within the bandgap have a peak near Ev + 0.8 eV and saturate for either longer stress time or higher stress temperature. In contrast, the PCs above a conduction band edge, namely the antineutralization positive charges, do not saturate, and their generation is clearly thermally accelerated. [ABSTRACT FROM AUTHOR]

Three system-level electrostatic discharge (ESD) design methodologies are compared using an RF buffer amplifier as case study. First, the system-level ESD protection is designed with datasheet information. The obtained overdesigned ESD protection is optimized with the System-Efficient ESD Design (SEED) methodology. The SEED-based protection design is further optimized using human metal model testing and transient simulations. The final ESD protection design requires five times less area on the application board, and the capacitive loading is six times lower than when designing with datasheet information. [ABSTRACT FROM PUBLISHER]

We report extensive experimental results of the negative bias temperature instability (NBTI) reliability of SiGe channel pMOSFETs as a function of the main gate-stack parameters. The results clearly show that this high-mobility channel technology offers significantly improved NBTI robustness compared with Si-channel devices, which can solve the reliability issue for sub-1-nm equivalent-oxide-thickness devices. A physical model is proposed to explain the intrinsically superior NBTI robustness. [ABSTRACT FROM AUTHOR]

The time-dependent variability of nanoscaled \Si0.45 \Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as \1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology. [ABSTRACT FROM AUTHOR]

The underlying physical mechanism of the Vth adjustment of nMOSFETs with HfSiO/TiN gate stack obtained by As and Ar implantation is investigated. It is experimentally proved that the trapped charge in the HfSiO bulk defects controls the initial Vth value in nMOSFETs. The reduction of the charged trap density in HfSiO by implant explains the tuned Vth values. [ABSTRACT FROM PUBLISHER]

We present an integrated reliability test methodology for electrostatic discharge (ESD) testing of micro-electromechanical systems (MEMS). It is shown that conventional ESD test methods for failure detection, like current and voltage waveforms during ESD stress and direct current leakage are insufficient for MEMS. A functionality-based approach using the mechanical response of the MEMS during ESD is needed to accurately and conclusively detect ESD failure in MEMS. A novel test setup with a probe-mountable human body model (HBM) tester is presented for this purpose. This setup can perform simultaneous measurements of MEMS out-of-plane displacement, HBM current and HBM voltage in the MEMS in situ during ESD stress. Using this setup, a few examples are demonstrated that show that traditional electrical characterization is overestimating the ESD robustness of MEMS devices. ESD testing of MEMS is performed at different pressures on RF MEMS actuators and show that more than one type of failure mechanism can occur due to ESD stress. ESD-induced charging and functionality degradation in RF MEMS actuators are also briefly discussed. [ABSTRACT FROM AUTHOR]

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition \HfO2 high-\kappa and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around \10^-8\ \cm^2, implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents. [ABSTRACT FROM PUBLISHER]

A methodology to incorporate the MOSFET gate dielectric breakdown (BD) failure mechanism in the design of complex systems is presented. The model accounts for the statistical nature of the BD phenomenon, is easily extensible to different device geometries and operation conditions (following the established scaling rules for the mechanism), considers the stress history, and can be easily implemented in circuit simulation tools. Device level characterization of the BD mechanism is presented, which is the base for model parameter extraction. The model has been introduced in a circuit simulator to show its suitability for evaluation of the BD effect in circuits and their reliability, taking ring oscillators as example. [ABSTRACT FROM PUBLISHER]

The off-state degradation of n-channel laterally diffused metal–oxide–semiconductor (MOS) silicon-controlled-rectifier electrostatic-discharge (ESD) devices for high-voltage applications in standard low-voltage complementary MOS technology is studied. Based on experimental data and technology computer-aided design simulations, impact ionization induced by conduction-band electrons tunneling from an \n^+ poly-Si gate to an n-well is identified to be the driving force of device degradation. Device optimization is proposed, which improves both off-state and ESD reliability. [ABSTRACT FROM AUTHOR]

A time-dependent dielectric breakdown (TDDB) lifetime model predicting the impact of line-edge roughness (LER) on Cu interconnect reliability is proposed. The structure, validity, and accuracy of the model are evaluated and discussed. The model is applied to an interconnect scaling scenario that includes conventional patterning and spacer-defined patterning of nanometer-scale Cu wires. LER-aware TDDB lifetime predictions are obtained from the model, and consequent recommendations on how to improve the TDDB lifetime of future interconnects are derived. [ABSTRACT FROM PUBLISHER]

In ultrascaled complimentary metal–oxide–semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (\SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal–oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or \SiO2 as a dielectric. [ABSTRACT FROM PUBLISHER]

Predicting negative bias temperature instability (NBTI) lifetime can be dangerous since it is difficult to assess its safety margin. The common technique uses gate bias Vg acceleration to reduce the test time, and the data were typically obtained from quasi-dc measurements. Recently, it has been shown that substantial recovery occurs during the quasi-dc measurement, and the suppression of recovery requires using ultrafast pulse measurement, where time was reduced to the order of microseconds. In a real circuit, different transistors have different levels of recovery, and the worst case scenario is when recovery is suppressed. At present, there is little information on how this worst case NBTI lifetime can be predicted and whether the traditional Vg acceleration technique can still be used. This work will show that the prediction based on the Vg acceleration results in a substantial error, and its cause will be analyzed. To predict the worst case lifetime, a model for NBTI kinetics under operation gate bias is developed. This kinetics includes contributions from both as-grown and generated defects, and it no longer follows a simple power law. Based on the new kinetics, a single-test prediction method is proposed, and its safety margin is estimated to be 50%. [ABSTRACT FROM AUTHOR]

In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting breakdown (SBD) and post-SBD wear-out (WO) parameters measuring the time to hard breakdown (tHBD) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model includes SBD and WO. [ABSTRACT FROM AUTHOR]

Positive charges in Hf-based gate stacks play an important role in the negative bias temperature instability of pMOSFETs, and their suppression is a pressing issue. The loca- tion of positive charges is not clear, and central to this letter is determining which layer of the stack dominates positive charging. The results clearly show that positive charges are dominated by the interfacial layer (IL) and that they do not pile up at the HfSiONIIL interface. The results support the assumption that positive charges are located close to the IL/substrate interface. Unlike electron trapping that reduces rapidly for thinner Hf dielectric layer, posi. tive charges cannot be reduced by using a thinner HfSiON film. Index Ternzs-Hf silicates, high-k gate dielectric, instability, negative bias temperature instability (NBTI), positive charges, reliability, spatial distribution. [ABSTRACT FROM AUTHOR]

After studying the properties of hole traps in Part I, attention is turned to the physical processes responsible for generating hole traps in Part II of this work. The applicability of four models to hole-trap creation will be examined. These are the trapped hole-electron recombination model, the electrical field energy model, the hole injection model, and the hydrogen model. To testify these models, stresses have to be carried out not only under substrate hole injection (SHI), but also under Fowler-Nordheim injection (FM). By combining FNI with SHI, we will be able to control hole fluency independent of the electron-induced hydrogen release. This allows us to determine how important hydrogen is for hole-trap generation. Although it was reported that hydrogen could play a major role in positive charge generation for devices with an Al gate or without a gate, we will show that hydrogen does not dominate hole-trap generation, when poly-si gated devices are stressed under our test conditions. Unambiguous results will also be given to show that key predictions of the recombination model and the electrical field energy model are not observed here. In this paper, the most important process for hole-trap generation is found to be the direct interaction of injected holes with the oxide. [ABSTRACT FROM AUTHOR]

As the downscaling of gate oxides continues, trap density in the oxide bulk will reduce, but positive charges formed near to the SiO2/ Si interface become relatively important. For gate oxides used in industry, hole trapping is the most important process for positive charge formation. Apart from as-grown hole traps, we recently reported that new hole traps were generated by electrical stresses. Information on these hole traps, however, is still limited. In part I of this work, properties of both generated and as-grown hole traps are investigated. For the first time, it will be clearly shown that generated hole traps consist of two components; cyclic positive charges (CPC) and anti-neutralization positive charges (ANPC). The charging and discharging rates of CPC are similar, while the neutralization of ANPC is much more difficult than its charging. Differences between them are also observed in generation kinetics and dependence on measurement temperature. Efforts will be made to explain their differences in terms of energy levels and to link them with positive charges reported in earlier works. We will also show that as-grown traps, regardless their distance from the interface, are not responsible for either ANPC or CPC. This is to say that generated hole traps are not the same as as-grown traps and their differences will be highlighted. In part II, hole trap generation mechanisms will be investigated. [ABSTRACT FROM AUTHOR]

Based on the so-called defect-centric statistics, we propose the average impact of a single charged trap on FET threshold voltage as a physically based measure of the random component of time-dependent variability. We show that it can be extracted using matched pairs, analogously to time-zero variability. To that end, the defect-centric statistics of matched pairs are discussed and the correlation between time-zero and time-dependent variances is formalized. [ABSTRACT FROM AUTHOR]

The high hole mobility of Ge makes it a strong candidate for end of roadmap pMOSFETs and low interface states have been achieved for the Al2O3/GeO2/Ge gate-stack. This structure, however, suffers from significant negative bias temperature instability (NBTI), dominated by positive charge (PC) in Al2O3GeO2. An in-depth understanding of the PCs will assist in the minimization of NBTI and the defect energy distribution will provide valuable information. The energy distribution also provides the effective charge density at a given surface potential, a key parameter required for simulating the impact of NBTI on device and circuit performance. For the first time, this letter reports the energy distribution of the PC in Al2O3GeO2 on Ge. It is found that the energy density of the PC has a clear peak near Ge Ec at the interface and a relatively low level between Ec and Ev. Below Ev at the interface, it increases rapidly and screens 20% of the Vg rise. [ABSTRACT FROM PUBLISHER]

We propose a novel metal/silicon/metal (MSM) selector using ultrathin (<10~nm) undoped amorphous silicon (a-Si) for resistive-RAM selector application. The new selector behaves as a bidirectional diode, showing a high current drive (\sim2.2~MA/cm)^2, high selectivity (\sim240 for 1/2 bias), fast switching speed (<1~ns), and excellent endurance (>10^8~cycles at target drive current). The doping-free a-Si structure alleviates the dopant-induced variability concerns for ultrascaled devices and eliminates the need for a dopant-activation anneal. Circuit simulations show feasibility of 1-Mb array, with over 25% read margin and 70% write margin, when using the new MSM structure as a selector for a HfO2-based resistive switching memory element. [ABSTRACT FROM AUTHOR]

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45^\circ rotated devices compared with the 0^\circ rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45^\circ rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv—exhibited when transitioning from planar to FinFET architecture at 45^\circ rotation—plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45^\circ rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho [ABSTRACT FROM AUTHOR]

A study of the negative and positive bias temperature instability (N/PBTI) reliability of FinFETs with different TiN metal gates deposited by either atomic layer deposition (ALD) or physical vapor deposition (PVD) on \HfO2 dielectrics found that the nonuniformity of the interfacial oxide layer is closely related to reliability characteristics. FinFETs with an ALD TiN gate exhibit better NBTI and PBTI lifetimes than those with a PVD TiN gate. In addition, the dependence of fin width on NBTI reliability appeared to be worse with narrower fins, whereas PBTI reliability improves. [ABSTRACT FROM PUBLISHER]

In this letter, endurance is investigated on one bulk FinFET transistor capacitorless random access memory, using the bipolar junction transistor (BJT) programming mode. For the first time, it is shown that endurance is an issue using the BJT-mode programming. The dominant degradation is due to the interface state generation by impact ionization used to write “1.” This degradation leads to the gate-induced drain leakage current increase, which results in shifts of the read state “0” current. [ABSTRACT FROM AUTHOR]

We focus on slow de-trapping phenomena in AlGaN/GaN MIS-HEMTs with a bilayer dielectric ( in-situ Si 3 N 4 /Al 2 O 3 ) with two different thicknesses of in-situ Si 3 N 4 (10 nm and 5 nm). By using a “filling pulse” at a positive gate voltage, a trap with activation energy of 0.69–0.7 eV was identified to be responsible for the V TH shift. Based on literature, filling conditions, and the simulated band diagrams, this trap is most probably located at the interface between the dielectrics and AlGaN barrier. A physical model is proposed to explain the V TH shift due to the trapping/de-trapping phenomena based on the occupation dynamics of donor traps at the interface between the in-situ Si 3 N 4 /Al 2 O 3 and the AlGaN barrier. [ABSTRACT FROM AUTHOR]

The reliability of Au-free Ohmic contacts has been evaluated under a constant current stress (500 mA/mm) in a high temperature environment (150 °C, 175 °C, and 200 °C). Two Ohmic contact schemes with different Ti/Al thicknesses (5 nm/100 nm and 10 nm/100 nm) have been tested. The results showed that the degradation of the resistance ( R increase ) is accelerated at a higher temperature condition. Moreover, R increase has a square root dependence with the time. This indicates that a diffusion process could be responsible for the observed degradation. This has been confirmed by means of physical failure analyses (FIB/TEM) performed on a highly degraded device: an apparent roughness of the interface between TiN and the Ohmic metal layer was observed. On top of this, Nitrogen out-diffusion into the Ohmic metal was observed in the EDS/EELS analyses, suggesting that a material diffusion phenomenon might play a role. In addition, we observed that the devices with a lower initial contact resistance ( R c ) showed lower degradation with respect to devices with a larger initial R c . This suggests that obtaining lower R c is beneficial not only for the performance but also for the reliability. [ABSTRACT FROM AUTHOR]

Abstract: In deeply scaled CMOS technologies, Bias Temperature Instability (BTI) is one of the most critical degradation mechanisms impacting the device reliability. This study presents the BTI evaluation of gates covering both the PMOS and NMOS degradation in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. In this paper, the impact of (1) duty factor, (2) periodic clock-based and non-periodic random input sequences, (3) gate, and (4) drive strength to the BTI degradation are investigated. Statistical studies show a mean degradation of 3% and a worst-case of 27%. Moreover, the near-critical paths with lower drive strength cells are 3.7× more susceptible to BTI degradation than the critical paths with higher drive strength cells. Next, the relative degradations of the propagation delays for the well-known gates (i.e. INV, NAND, NOR, AOI) are presented. Under the same stress stimuli, degradations of the gate propagation delays differ by 4.5×. [Copyright &y& Elsevier]

The reliability of ultra-thin silicon oxynitride gate dielectrics was investigated in terms of the Weibull slope of the tbd distributions, and the voltage acceleration factor. High field tBD statistics were extrapolated using a worst-case linear fit, to the low field region. The samples showed low voltage acceleration, which degrades reliability, but this is overcome by high Weibull slopes (β), which improve reliability. The high β values were investigated by monitoring the change in β as gate current increased during CVS. We saw the Weibull slope change from &ap;1 at low current to 2 at high current, indicating that breakdown results from 2-trap conduction. Charge pumping measurements showed that the trap generation rate at the SiON/Si interface, where most of the Nitrogen resides was very low. Thus it was concluded that there is a much higher trap generation rate in the bulk than at the interface and this is responsible for the values of β. [Copyright &y& Elsevier]