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Resistance drift in phase change memory (PCM) reduces the accuracy of analog computing applications such as neural network inference. Recently, PCMs based on superlattice (SL) phase change layers have shown low resistance drift, however the origin of this low drift remains unexplored. Here, we uncover that resistance drift in SL-PCM based on alternating layers of Sb2Te3 and Ge2Sb2Te5 (GST) is controlled by the number of SL interfaces as well as the degree of SL intermixing. Temperature-dependent measurements reveal smaller and more stable activation energy upon annealing (thus suppressed structural relaxation) in our SL-PCM vs. control GST devices, accounting for the low resistance drift. By controlling SL interfaces, we achieve low resistance drift coefficient ${v} < 0.01$ in these SL-PCMs, maintained after extensive cycling and at various read voltages and intervals - showing robustness required for analog computing with PCM. [ABSTRACT FROM AUTHOR]

Large switching current density and resistance drift remain challenges for phase change memory (PCM) in data storage and neuromorphic computing applications. Here, we address these by electro-thermal and structural confinement in a GeTe/Sb2Te3 superlattice PCM (SL-PCM) with thermally-induced phase change, while observing scalability with bottom electrode diameter. We demonstrate ~ $\text{8-10}\times $ reduction of reset current density $({J}_{\text {reset}})$ and ~ $\text{25-30}\times $ reduction of power $({P}_{\text {reset}})$ in our mushroom cell SL-PCM compared to control Ge2Sb2Te5 (GST) PCM with the same device structure. The SL-PCM devices also exhibit multi-level states with $\sim 10\times $ lower resistance drift compared to control GST PCM. Material characterization and electro-thermal simulations confirm the role of heat confinement in SL-PCM, paving the way towards low-power, high-density memory and data storage. [ABSTRACT FROM AUTHOR]

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability. [ABSTRACT FROM AUTHOR]

One of the major roadblocks for filamentary type resistive random access memory is variations in both the write voltage and the read resistance. The variation is inevitable because of the stochastic nature of oxygen ion movement inside the metal oxide. In this letter, we show that by inserting a thin SnO2 layer within the HfO2 switching layer, these variations can be significantly reduced. The TiN/HfO2/SnO2/HfO2/Pt material stack achieves ~ 10 times smaller standard deviation for the high resistance state($>100\text{k}\Omega $) cycle to cycle distribution compared with the control group without the SnO2 layer. The tight high resistance state distribution retained after 107 pulse cycling. Incremental RESET pulse measurement indicates that the thin SnO2 acts as an oxygen stopping layer and thus explains the origin of reduced variability. The concept of an oxygen stopping layer is promising for reducing variability for resistive memory. [ABSTRACT FROM AUTHOR]

HfO2-based resistive RAM (RRAM) is an emerging nonvolatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for multiple bits-per-cell RRAM, especially when resistance ranges are allocated to account for retention. We present a new technique, Range-Dependent Adaptive Resistance (RADAR) Tuning, for fast and energy-efficient programming of multiple bits-per-cell RRAM arrays, using a combination of coarse- and fine-grained RRAM resistance tuning. Experimental data are collected on 16k cells from two 1Megacell (1M physical cells) 1T1R HfO2-based RRAM arrays fabricated in a 130-nm CMOS process. RADAR reduces the programming pulse count by 2.4X (for both uncycled cells and cells that have undergone 8k cycles) on average over existing programming techniques tested on the same RRAM arrays, with the same bit error rate targets. [ABSTRACT FROM AUTHOR]

High switching current density has been a key bottleneck for phase change memory (PCM) technology. Here, we demonstrate interfacial thermoelectric heating (TEH) as a promising way of tackling this challenge. We use TEH induced by a thin Bi2Te3 interfacial layer to demonstrate $\sim 2\times $ reduction of reset current density (${J} _{\text{reset}}$) and power (${P} _{\text{reset}}$) compared to control PCM devices based on Ge2Sb2Te5 (GST). Measurements of polarity-dependent reset current and power in well-cycled devices reveal the strong TEH caused by the Bi2Te3 interfacial layer. The TEH origin of ${J} _{\text{reset}}$ reduction is further confirmed by electro-thermal simulations. Such TEH-engineered PCM devices are scalable with the bottom electrode diameter and thus could be promising for high density data storage applications. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RSM) shows potentials for high-capacity storage because of its simple cell structure, small footprint, and good scalability. This two-part article discusses how to implement ultrahigh-density (~terabits) storage with RSM covering design considerations from device to memory array architecture. In Part I of this two-part article, an accurate and computationally efficient model is developed to study 3-D vertical RSM (VRSM). In this article, we use 3-D VRSM with a hexagon-patterned pillar layout (3-D hexagon VRSM) as an example to elaborate our approach. Using the parasitic resistance extracted from physics-based 2-D field solver as the reference, we develop a lumped resistor network for SPICE simulation to accurately capture all leakage currents of the array. This full resistor network is further simplified to a reduced network to achieve high computational efficiency and maintain the full network accuracy (with a relative error <2%). Without this simplification, practical memory array sizes cannot be simulated efficiently. The interplay between the memory cell resistance values and selector nonlinearity (NL) on the maximum array size and the write/read margins under the worst case scenarios is discussed. Large memory cell resistance (low-resistance states ≥100 k) with enough NL (~103) from the selector is recommended for successful write/read operations in a single 3-D hexagonal VRSM array of megabit scale. [ABSTRACT FROM AUTHOR]

A physics-based compact model for retention behaviors of conductive-bridge random access memory (CBRAM) is developed by modeling: 1) the material-dependent metal atom transport from the conductive filament into the electrolyte; and 2) the conduction percolation controlled by the atom concentration. Considering the material properties of the metal and electrolyte, this compact model can well reproduce the retention behaviors of the CBRAM in both low resistance state and high resistance state (HRS) for various material stacks under various operating temperatures. Two types of HRS resistance shift can be reproduced by accurately modeling the percolation paths. The compact model can enable the reliability projection of cells in a crossbar array. [ABSTRACT FROM AUTHOR]

We demonstrate, for the first time, resistive RAM (RRAM) arrays where each cell can store 3 bits. Such full array-level demonstration is possible through special techniques (e.g., that exploit RRAM-specific characteristics of variations in cell resistances), presented in this paper, which efficiently allocate resistance range corresponding to each bit combination (required for proper write operation) while maintaining appropriate sensing margin (required for proper read operation). Our techniques are not restricted to 3 bits-per-cell only (and, in this paper, we demonstrate 2 bits-per-cell at the array level as well). Our measured results are based on multiple 4 Kbit arrays of 1T1R HfOx-based RRAM integrated in the back end of the line of 130-nm silicon CMOS technology. We achieve 3 bits-per-cell (2 bits-per-cell) RRAM with 11 (3) programing iterations on average. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade. [ABSTRACT FROM AUTHOR]

A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array. [ABSTRACT FROM AUTHOR]

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/ $n$ architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance. [ABSTRACT FROM PUBLISHER]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

This paper describes the improvement of pull-in stability, contact properties, and reliability of laterally actuated nanoelectromechanical relays by partitioning the mechanical and electrostatic domains in the relay structure. Separation of the two physics allows us to individually optimize the structural stiffness and the actuation voltage to increase the contact pressure and reduce the ON-state resistance without applying excessive drain voltage. The devices can tolerate more than 200% overdrive gate voltage, resulting in near 100% increase in contact force, and reducing the contact resistance from $\sim 10$ G $\Omega $ to $\sim 23$ K $\Omega $ . For a given overall device dimension, tailoring the mechanical and electrostatic elements independently also enables us to control the pull-in and pull-out voltages, which have different design requirements for different applications. The measurement results show that the pull-in/pull-out hysteresis could vary between 30% and 60% of the actuation (pull-in) voltage. Increasing the mechanical force without affecting the device actuation voltage improves the relay reliability by reducing the possibility of failure due to source–drain stiction when the relay is switched ON. As a proof of concept, mechanical relays are fabricated using polycrystalline silicon coated by a titanium nitride layer deposited via plasma enhanced atomic layer deposition. [2014-0018] [ABSTRACT FROM AUTHOR]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

Electrothermal transport and crystallization dynamics govern the speed and bit stability of multibit phase-change memory (PCM). This paper develops a transient simulation methodology incorporating electrical, thermal, and phase transition models to investigate multibit PCM cell structures and programming strategies. The simulations evaluate two standard PCM structures, namely, the mushroom cell and the confined pillar cell, with feature sizes smaller than 40 nm. The transient simulation captures the phase distribution and cell resistance profile, which are corroborated by transmission electron microscope imaging and the corresponding measured resistance values. This paper also explores a more compact architecture, i.e., the stacked vertical cell, with precise control of Joule heating and potentially more stable intermediate resistance levels. For an electrode area of 10 nm \times 20 nm, a low programming current of \60-\90\ \mu\A generates sufficient heating power to amorphize the phase-change elements sequentially, resulting in four distinct resistance levels distributed over a two-order-of-magnitude resistance range with promise for multibit storage. [ABSTRACT FROM AUTHOR]

In this paper, recent progress of binary metal–oxide resistive switching random access memory (RRAM) is reviewed. The physical mechanism, material properties, and electrical characteristics of a variety of binary metal–oxide RRAM are discussed, with a focus on the use of RRAM for nonvolatile memory application. A review of recent development of large-scale RRAM arrays is given. Issues such as uniformity, endurance, retention, multibit operation, and scaling trends are discussed. [ABSTRACT FROM PUBLISHER]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

The subthreshold conduction in the amorphous state of the phase-change material is dominated by the hopping of the carriers through the trap states or localized states with the assistance of the electric field across the material. It is important to understand the nature and number of these traps to properly model the physics of the conduction, threshold switching, and drift in phase-change materials. In this paper, we present a device structure and a methodology to extract the trap spacing directly from the I–V characteristics of the device. Furthermore, the dependence of the trap spacing on the amorphous region thickness, reset voltage, and drift is also discussed. These results are then correlated with the \1/f noise measurements of the device. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

The multilevel capability of metal oxide resistive switching memory was explored for the potential use as a single-element electronic synapse device. \TiN/HfOx/\AlOx/ \Pt resistive switching cells were fabricated. Multilevel resistance states were obtained by varying the programming voltage amplitudes during the pulse cycling. The cell conductance could be continuously increased or decreased from cycle to cycle, and about \10^5 endurance cycles were obtained. Nominal energy consumption per operation is in the subpicojoule range with a maximum measured value of 6 pJ. This low energy consumption is attractive for the large-scale hardware implementation of neuromorphic computing and brain simulation. The property of gradual resistance change by pulse amplitudes was exploited to demonstrate the spike-timing-dependent plasticity learning rule, suggesting that metal oxide memory can potentially be used as an electronic synapse device for the emerging neuromorphic computation system. [ABSTRACT FROM PUBLISHER]

A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I–V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the \Ag/Ge0.3\Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation. [ABSTRACT FROM PUBLISHER]

To address the scalability of phase change memory (PCM), we study a 1-D thickness scaling effect on threshold switching voltage (Vth), Vth drift, high resistance state (RESET) resistance (RRESET) drift, and crystallization temperature (Tcrys). We use a pseudo three-terminal device to accurately correlate the amorphous region thickness to the observed characteristics. The pseudo 3-terminal device is a fully functional PCM cell and enables 1-D thickness scaling study down to 6 nm without the need for ultrafine lithography. Vth scales down to 0.65–0.5 V (at 25 ^ \circ\C–75 ^\circ\C) for 6-nm-thick \Ge2\Sb2\Te5 (GST), showing that stable read operation is possible in scaled PCM devices. The Vth drift measurement suggests that Vth drift can be attributed to threshold switching field (Eth) drift, whereas Vth0, i.e., Vth at zero thickness, stays almost constant. RRESET drift shows no dependence on the amorphous GST thickness. Tcrys is \sim\!\175 \ ^\circ\C for the device with 6-nm-thick GST, compared with \sim\!\145 \ ^\circ\C of thick GST. From the 1-D scaling study, no significant hurdles against scaling are found down to 6 nm. Further study of scaling effect on endurance and development of scalable selection device is needed to assess the ultimate scalability of PCM. [ABSTRACT FROM PUBLISHER]

We study the drift behavior of RESET resistance RRESET and threshold switching voltage Vth in phase-change memory (PCM) and their temperature dependence. To extend the temperature-dependent measurement to microsecond time scales, we integrate an innovative micro-thermal stage (MTS) on the PCM cell. The MTS changes the temperature of the programmed region of the PCM cell within a few microseconds by placing the Pt heater in close proximity of the programmed region. First, we experimentally verify the existing phenomenological RRESET and Vth drift model for constant annealing temperature at various temperatures between 25 ^\circ\C and 185 ^ \circ\C down to 100 \mu\s and show that the measured temperature dependence of the drift coefficient agrees well with what is expected from the existing drift models. Based on the existing drift model for a constant annealing temperature, we derive the analytical expression for the RRESET drift for time-varying annealing temperature and experimentally verify the analytical expression. The derived analytical expression is important to understand the impact of thermal disturbance on PCM reliability such as variations in RRESET and Vth. [ABSTRACT FROM PUBLISHER]

Ge N-MOSFETs have exhibited poor drive currents and low mobility, as reported by several different research groups in the past. The major mechanisms behind poor Ge NMOS performance have not been completely understood yet. In this paper, mechanisms responsible for poor Ge NMOS performance in the past are investigated with detailed gate dielectric stack characterizations and Hall mobility analysis. High source/drain (S/D) parasitic resistance, inversion charge loss due to trapping in the high-K gate dielectric, and high interface trap density are identified as the mechanisms responsible for Ge NMOS performance degradation. After eliminating the degradation mechanisms, the highest electron mobility in Ge NMOS to date, which is, to the best of our knowledge, \sim1.5 times the universal Si mobility, is experimentally demonstrated for the Ge N-MOSFETs fabricated with ozone-oxidation surface passivation and low temperature S/D activation processes. [ABSTRACT FROM AUTHOR]

Carbon-based nanomaterials such as metallic single-walled carbon nanotubes, multiwalled carbon nanotubes (MWCNTs), and graphene have been considered as some of the most promising candidates for future interconnect technology because of their high current-carrying capacity and conductivity in the nanoscale, and immunity to electromigration, which has been a great challenge for scaling down the traditional copper interconnects. Therefore, studies on the performance and optimization of carbon-based interconnects working in a realistic operational environment are needed in order to advance the technology beyond the exploratory discovery phase. In this paper, we present the first demonstration of graphene interconnects monolithically integrated with industry-standard complementary metal–oxide–semiconductor technology, as well as the first experimental results that compare the performance of high-speed on-chip graphene and MWCNT interconnects. The graphene interconnects operate up to 1.3-GHz frequency, which is a speed that is commensurate with the fastest high-speed processor chips today. A low-swing signaling technique has been applied to improve the speed of carbon interconnects up to 30%. [ABSTRACT FROM PUBLISHER]

Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach \10^6 with a signal swing > 50% of the reading voltage when Ron is beyond 3 \M\Omega and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I–V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design. [ABSTRACT FROM PUBLISHER]

In this letter, we report ultra-low power (sub-30-nA reset current, I\mathrm {reset}) Ni/HfO2/TiOx/TiN RRAM devices that were fabricated with the rapid thermal oxidation of evaporated titanium. RRAM devices show forming-free, bipolar resistive switching behavior, low-resistive state (LRS) nonlinearity, good data retention, and stability. The resistive switching mechanism is mainly attributed to Schottky barrier modulation induced by \textO^2- migration at the Ni/HfO2 interface. LRS/high-resistive state current conduction is controlled by Schottky emission/trap-controlled space-charge-limited current. The TiOx film is believed to provide a local high-density current for the device, confirmed by conductive atomic force microscope results. [ABSTRACT FROM PUBLISHER]

This letter presents the novel CMOS-compatible all-metal-nitride resistive random access memory (RRAM) devices based on the TiN/AlN/TiN stack. The device has low operation current <100 \mu A, retention of > 3\times 10^{5} s at 150 °C, and ac endurance of up to 10^{5}$ Hz. The device switch characteristics are found to agree with the filamentary switch mechanism. In addition, the RRAM devices built with an additional hafnium nitride capping layer have showed less switch voltage variations and stable switch characteristics. [ABSTRACT FROM PUBLISHER]

In this letter, we examine the role of the Ti capping layer in HfOx-based resistive random access memory (RRAM) devices on the memory performance. It is found that with a thicker Ti capping layer, the fresh device initial leakage current increases and as a result, the forming voltage decreases. In addition, with a thin Ti layer of <3 nm (on top of 8-nm HfOx), there is no resistive switching, while by inserting a thicker Ti layer of 10 nm, the memory window enlarges to about two orders. Very good uniformity has also been observed in thick Ti capping devices, demonstrating the effectiveness in RRAM device engineering. It is believed that the Ti layer serves as an oxygen reservoir, by extracting oxygen during device formation and electrical forming process and facilitates resistive switching thereafter. [ABSTRACT FROM AUTHOR]

A SPICE compact model is developed for metal-oxide-based resistive random access memory (RRAM). The model includes the critical impact of temperature change and temporal variation. Using experimental data from \HfOx-based RRAM, the model reproduces both the voltage–time relationship and the cycle-to-cycle variation in the RESET of the memory cells. [ABSTRACT FROM AUTHOR]

This letter describes a novel experimental structure that captures the impact of rapid temperature transients and repetitive cycling on the thermal and electrical properties of \Ge2 \Sb2\Te5 (GST). The microthermal stage dramatically improves the temporal resolution for heating and enables simultaneous thermal and electrical characterizations. Thermal conductivity measurements show phase transitions of GST accompanied by abrupt changes in electrical resistance. Repetitive cycling with durations down to 100 ns produces melt-quenched amorphous GST with the thermal conductivity 40% lower than that of crystalline GST. Recrystallization increases conductivity but not up to the value achieved by long-timescale bulk annealing. This is potentially because the rapidly recrystallized GST contains more disorder near the interface. [ABSTRACT FROM AUTHOR]

The reset mechanism of metal oxide RRAM has been attributed to oxygen ion migration assisted by Joule heating. Here, we present a phenomenological model to provide a unified explanation for both the unipolar and bipolar resistive switching mechanisms. Numerical simulation results reveal that the switching mode is determined by the electrode/oxide interface property. Without/with an interfacial barrier, unipolar/bipolar switching behavior is obtained. This model combines the previous thermal dissolution model and ion migration model and thus can explain many experimental observations such as the electrode-material-dependent switching polarity and the voltage–time dilemma between fast switching and long retention. [ABSTRACT FROM AUTHOR]

\Al2\O3-based RRAM devices were fabricated using atomic layer deposition under 100 ^\circ\C and 300 ^\circ\C deposition temperatures, respectively, and their resistance-switching behaviors were investigated. Both devices show unipolar switching if the top electrode (TE) is made of Ti/Al, whereas the bipolar phenomenon is observed when TE is pure aluminum. Devices fabricated at higher temperature give better uniformity and higher resistance ratio. Ultralow RESET current (\sim\!\!\1\ \mu\A) was obtained, together with adequate voltage margin. [ABSTRACT FROM AUTHOR]