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In the present work, impact of Double Gate RingFET (DG-RingFET) has been investigated for better gate control and suppressed Short Channel Effects (SCEs) using ATLAS 3D device simulator. The analog performance metrics explored in this paper are drain current (Ids - Vgs), trans-conductance (gm), device efficiency (gm/Ids), and early voltage (Vea). In addition to this linearity behaviour of DGRingFET has been investigated in terms of third-order voltage intercept point (VIP3), third-order current intercept point (IIP3), third-order inter modulation distortion (IMD3) and results are also compared with the single gate architecture. The two-dimensional analytical model for DG-RingFET architecture has also been developed in this paper using parabolic approach. Moreover, the impact of technology variations like drain radii and position of drain, i.e. inside or outside the channel ring on the performance of DG-RingFET architecture has also been assessed. [ABSTRACT FROM AUTHOR]

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices. [ABSTRACT FROM AUTHOR]

In this paper, we report the 2-D drain current model for asymmetric dual material (DM) junctionless double gate transistor. On the basis of channel potential, transconductance and its higher order derivatives are estimated and verified with the ATLAS 3-D device simulator results. The developed model is also applicable to investigate the digital performance of the device in terms of voltage transfer characteristics of nMOS inverter circuit. The impact of the length of control gate on the analog performance has also been investigated. Results also highlight the advantage of DM gate over the single material gate for digital and analog applications using CMOS inverter and common source amplifier through exhaustive circuit simulation. [ABSTRACT FROM PUBLISHER]

In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications. [ABSTRACT FROM PUBLISHER]

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-\kappa), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier. [ABSTRACT FROM PUBLISHER]

The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure. [ABSTRACT FROM AUTHOR]

Abstract: A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software. [Copyright &y& Elsevier]

Two-dimensional (2-D) analytical modeling for a novel multiple region MOSFET device architecture—Tri-Material Gate Stack MOSFET—is presented, which shows reduced short-channel effects at short gate lengths. Using a three-region analysis in the horizontal direction and a universal depletion width boundary condition, the 2-D potential and electric field distribution in the channel region along with the threshold voltage of the device are obtained. The proposed model is capable of modeling electrical characteristics like surface potential, electric field, and threshold voltage of various other existent MOSFET structures like dual-material-gate, electrically induced shallow junction/straddle-gate (side-gate), and single-material-gate MOSFETs, with arid without the gate stack architecture. The 2-D device simulator ATLAS is used over a wide range of parameters and bias conditions to validate the analytical results. [ABSTRACT FROM AUTHOR]

In this paper we propose and investigate the application of Electromagnetic Band Gap (EBG) substrate for improving the performance of Hemispherical Dielectric Resonator Antenna (HDRA). Our designed EBG shows a band gap in the frequency range of 1.75–2.25 GHz and the HDRA is resonant at 2 GHz which falls within the bandgap of the EBG. When combined with the EBG substrate the −10 dB bandwidth shows an improvement from 11.25% to 30%. On engineering the height of the HDRA on EBG substrate the gain is improved from 6.13 dBi to 9 dBi. To validate the results, simulations are carried out on CST Microwave Studio and HFSS. [ABSTRACT FROM AUTHOR]

Abstract: In Single Gate HEMT (SGHEMT) shortening of gate length below 100 nm leads to reduction in Transconductance , which reduces the unloaded voltage gain of the device, thereby reducing the maximum frequency of oscillation . The main reason for this reduction in with in the Single Gate HEMT (SGHEMT) is its inability to maintain the desired channel aspect ratio (). At such a miniaturization level, not only depends on the channel depth but also on the channel thickness of the device . Moreover, the variation of may switch the device characteristics from quantum regime to classical regime . The Double Gate HEMT (DGHEMT)  has emerged as a solution for further reduction in and provides enhancements over SGHEMT by virtue of its double gate and also for same due to double heterojunctions, which virtually increases the value of . In the present work, extensive simulation work has been carried out using ATLAS device simulator  in order to study the effect of and on DGHEMT and SGHEMT. An analytical model has also been proposed for SGHEMT and DGHEMT to incorporate the effect of variation of and . [Copyright &y& Elsevier]

Abstract: This paper presents an approximate solution of a 2-D Poisson’s equation in the channel region, based on physical correspondence between MOSFET and HEMT, with the approximation that the vertical channel potential distribution is a cubic function of position to study not only tied gate but separate gate bias conditions as well. An analytical expression for both front and back heterointerface potential is derived and threshold voltage is obtained iteratively from the proposed potential model. The threshold voltage behavior for tied and separated double-gate HEMT is investigated for various device dimensions. The back gate effect of the separated double gate HEMT is investigated for the depleted back channel only. The results obtained are verified by comparing them with simulated and experimental results. [Copyright &y& Elsevier]

Abstract: Double gate MOSFET has been regarded as the most promising candidate for future CMOS devices, for excellent short channel effects (SCEs) immunity and high current drivability due to double gate coupling. The alignment between the top and bottom gates should be concern to fully realize the benefits of the double-gate configuration, as gate misalignment causes degradation in the device performance. Use of graded channel architectures somehow reduces the effect of gate misalignment. We scrutinize that how the misalignment affects the small signal behavior and device characteristics like conductances, capacitances and cut-off frequency, for uniformly doped and graded channel double gate architectures. Considering the fact that gate misalignment can occur on any side of the gate, extensive simulations have been carried out using high–low (H–L), low–high (L–H) and low–high–low (L–H–L) doping profiles for both source (DGS) and drain side (DGD) gate misalignment. [Copyright &y& Elsevier]

The paper presents the results of a systematic analytical characterization, supplemented by 2D device simulation, applied to novel device architecture: hetero-material double-gate (HEM-DG) MOSFET with effective channel length down to 30 nm. A new approach to explain the pertinent device physics is presented, which can facilitate device design and technology selection for enhanced performance. Numerical device simulation data, obtained using 2D device simulator: ATLAS, for threshold voltage, drain induced barrier lowering (DIBL) and subthreshold swing (S) were compared to the model to validate the analytical formulation. The comparison of symmetric DG (SDG) MOSFET and HEM-DG MOSFET configurations demonstrated superiority of HEM-DG MOSFET: ideal S and reduced DIBL. Comparison with simulated results reveals excellent quantitative agreement. [Copyright &y& Elsevier]

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation. [ABSTRACT FROM AUTHOR]

In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation. [ABSTRACT FROM AUTHOR]

Abstract: An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model. [Copyright &y& Elsevier]

Highlights: [•] A temperature dependent model is developed for GAA MOSFET having localized charges. [•] Analytical results are verified with simulation results of ATLAS 3D simulator. [•] Variations in temperature sensitivity due to localized charges are studied. [•] Degradation is higher at low temperatures and in subthreshold region. [ABSTRACT FROM AUTHOR]

Abstract: This paper presents two dimensional temperature dependent analytical model of Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data using ATLAS 3D device simulator for wide operating temperature i.e. 300–500K for channel length down to 32nm technology node. In this work, a temperature dependent analytical expression of drain current for sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reduced leakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverter performance and hence ISESON can be widely used in CCD camera as well as for fast switching applications. Further, we have also investigated the impact of temperature on electrical characteristics of ISESON MOSFET which are important for analog applications. [Copyright &y& Elsevier]

Abstract: The paper presents a simulation study of Nanoscale Cylindrical Surrounding Gate (SRG) MOSFET with localised interface charges. The objective of the present work is to study the performance degradation due to hot carrier induced/radiation induced/stress induced damage in the form of localised/fixed charges at the semiconductor/oxide interface of the device. Impact of fixed charges has been studied on the characteristics such as drain current, transconductance and its higher order terms, device efficiency and linearity FOMs. Effect of nature and extension of interface fixed charges has been discussed in detail through extensive simulation. Circuit reliability issues of the device are discussed in terms of DC bias point degradation. [Copyright &y& Elsevier]

Abstract: In this paper, the RF performance for Gate Material Engineered-Trapezoidal Recessed Channel (GME-TRC) MOSFET has been investigated and the results so obtained are compared with Trapezoidal Recessed Channel (TRC) MOSFET and Rectangle Recessed Channel (RRC) MOSFET, using device simulators; ATLAS and DEVEDIT. Further, the impact of technology parameter variations in terms of negative junction depth (NJD), gate metal workfunction difference, substrate doping (N A) and corner angle, on GME-TRC MOSFET has also been evaluated. The simulation study shows the increase in transconductance and decrease in parasitic capacitance, which further contributes towards a significant improvement in cut-off frequency (f t) in GME-TRC MOSFET as compared to conventional TRC and RRC MOSFETs. Moreover, the significant enhancement in maximum available power gain (Gma), maximum transducer power gain (G MT), maximum unilateral power gain (MUG), maximum frequency of oscillation (f MAX) and stern stability factor (K) have also been observed for GME-TRC MOSFET due to reduced short channel effects (SCEs) and enhanced current driving capabilities. Further, the experimental data for grooved gate MOSFET has also been verified with the simulated data and a good agreement between their results is obtained. [Copyright &y& Elsevier]

Abstract: This paper analyses the RF performance of the symmetric tied-gate In0.52Al0.48As/In0.53Ga0.47As DG-HEMT in terms of its maximum frequency of oscillation (f max) and the other important figures of merit that include Maximum Unilateral Transducer Power Gain and the Maximum Stable Gain. This comprehensive investigation has been done on the basis of scattering parameters in order to judge the potential of InAlAs/InGaAs DG-HEMT as the device for future millimeter wave frequency applications. The effect of parasitic elements has also been included in the analytical model which leads to better correspondence with the experimental results. The analytical results thus obtained using the charge control model are compared and found to agree well with both the ATLAS-3D device simulation results as well as the experimental results. [Copyright &y& Elsevier]

Abstract: In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal–insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n+-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268–2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal–Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534–2540] are also being fabricated these days, mainly at the drain end (-gate) having Metal–Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal–Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189–198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model. [Copyright &y& Elsevier]

Abstract: The present work explores the features of gate material engineered (GME) AlGaN/GaN high electron mobility transistor (HEMT) for enhanced carrier transport efficiency (CTE) and suppressed short channel effects (SCEs) using 2-D sub-threshold analysis and device simulation. The model accurately predicts the channel potential, electric field and sub-threshold current for the conventional and GME HEMT, taking into account the effect of work function difference of the two metal gates. This is verified by comparing the model results with the ATLAS simulation results. Further, simulation study has been extended to reflect the wide range of benefits exhibited by GME HEMT for its on-state and analog performance. The simulation results demonstrate that the GME HEMT exhibits much higher on current, lower conductance and higher transconductance as compared to the conventional HEMT due to improved CTE and reduced SCEs. This in turn has a direct bearing on the device figure of merits (FOMs) such as intrinsic gain, device efficiency and early voltage. Tuning of GME HEMT in terms of the relative lengths of the two metal gates, their work function difference and barrier layer thickness has further been carried out to enhance the drive current, transconductance and the device FOMs illustrating the superior performance of GME HEMT for future high-performance high-speed switching, digital and analog applications. [Copyright &y& Elsevier]